1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPI0</name> 5 <description>SPI peripheral.</description> 6 <baseAddress>0x40046000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>SPI0</name> 14 <value>16</value> 15 </interrupt> 16 <registers> 17 <register> 18 <name>FIFO32</name> 19 <description>Register for reading and writing the FIFO.</description> 20 <addressOffset>0x00</addressOffset> 21 <size>32</size> 22 <access>read-write</access> 23 <fields> 24 <field> 25 <name>DATA</name> 26 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <dim>2</dim> 34 <dimIncrement>2</dimIncrement> 35 <name>FIFO16[%s]</name> 36 <description>Register for reading and writing the FIFO.</description> 37 <addressOffset>0x00</addressOffset> 38 <size>16</size> 39 <access>read-write</access> 40 <fields> 41 <field> 42 <name>DATA</name> 43 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 44 <bitOffset>0</bitOffset> 45 <bitWidth>16</bitWidth> 46 </field> 47 </fields> 48 </register> 49 <register> 50 <dim>4</dim> 51 <dimIncrement>1</dimIncrement> 52 <name>FIFO8[%s]</name> 53 <description>Register for reading and writing the FIFO.</description> 54 <addressOffset>0x00</addressOffset> 55 <size>8</size> 56 <access>read-write</access> 57 <fields> 58 <field> 59 <name>DATA</name> 60 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 61 <bitOffset>0</bitOffset> 62 <bitWidth>8</bitWidth> 63 </field> 64 </fields> 65 </register> 66 <register> 67 <name>CTRL0</name> 68 <description>Register for controlling SPI peripheral.</description> 69 <addressOffset>0x04</addressOffset> 70 <access>read-write</access> 71 <fields> 72 <field> 73 <name>EN</name> 74 <description>SPI Enable.</description> 75 <bitOffset>0</bitOffset> 76 <bitWidth>1</bitWidth> 77 <enumeratedValues> 78 <enumeratedValue> 79 <name>dis</name> 80 <description>SPI is disabled.</description> 81 <value>0</value> 82 </enumeratedValue> 83 <enumeratedValue> 84 <name>en</name> 85 <description>SPI is enabled.</description> 86 <value>1</value> 87 </enumeratedValue> 88 </enumeratedValues> 89 </field> 90 <field> 91 <name>MST_MODE</name> 92 <description>Master Mode Enable.</description> 93 <bitOffset>1</bitOffset> 94 <bitWidth>1</bitWidth> 95 <enumeratedValues> 96 <enumeratedValue> 97 <name>dis</name> 98 <description>SPI is Slave mode.</description> 99 <value>0</value> 100 </enumeratedValue> 101 <enumeratedValue> 102 <name>en</name> 103 <description>SPI is Master mode.</description> 104 <value>1</value> 105 </enumeratedValue> 106 </enumeratedValues> 107 </field> 108 <field> 109 <name>SS_IO</name> 110 <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 111 <bitOffset>4</bitOffset> 112 <bitWidth>1</bitWidth> 113 <enumeratedValues> 114 <enumeratedValue> 115 <name>output</name> 116 <description>Slave select 0 is output.</description> 117 <value>0</value> 118 </enumeratedValue> 119 <enumeratedValue> 120 <name>input</name> 121 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 122 <value>1</value> 123 </enumeratedValue> 124 </enumeratedValues> 125 </field> 126 <field> 127 <name>START</name> 128 <description>Start Transmit.</description> 129 <bitOffset>5</bitOffset> 130 <bitWidth>1</bitWidth> 131 <enumeratedValues> 132 <enumeratedValue> 133 <name>start</name> 134 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description> 135 <value>1</value> 136 </enumeratedValue> 137 </enumeratedValues> 138 </field> 139 <field> 140 <name>SS_CTRL</name> 141 <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description> 142 <bitOffset>8</bitOffset> 143 <bitWidth>1</bitWidth> 144 <enumeratedValues> 145 <enumeratedValue> 146 <name>DEASSERT</name> 147 <description>SPI De-asserts Slave Select at the end of a transaction.</description> 148 <value>0</value> 149 </enumeratedValue> 150 <enumeratedValue> 151 <name>ASSERT</name> 152 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 153 <value>1</value> 154 </enumeratedValue> 155 </enumeratedValues> 156 </field> 157 <field> 158 <name>SS_ACTIVE</name> 159 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 160 <bitOffset>16</bitOffset> 161 <bitWidth>4</bitWidth> 162 <enumeratedValues> 163 <enumeratedValue> 164 <name>SS0</name> 165 <description>SS0 is selected.</description> 166 <value>0x1</value> 167 </enumeratedValue> 168 <enumeratedValue> 169 <name>SS1</name> 170 <description>SS1 is selected.</description> 171 <value>0x2</value> 172 </enumeratedValue> 173 <enumeratedValue> 174 <name>SS2</name> 175 <description>SS2 is selected.</description> 176 <value>0x4</value> 177 </enumeratedValue> 178 <enumeratedValue> 179 <name>SS3</name> 180 <description>SS3 is selected.</description> 181 <value>0x8</value> 182 </enumeratedValue> 183 </enumeratedValues> 184 </field> 185 </fields> 186 </register> 187 <register> 188 <name>CTRL1</name> 189 <description>Register for controlling SPI peripheral.</description> 190 <addressOffset>0x08</addressOffset> 191 <access>read-write</access> 192 <fields> 193 <field> 194 <name>TX_NUM_CHAR</name> 195 <description>Nubmer of Characters to transmit.</description> 196 <bitOffset>0</bitOffset> 197 <bitWidth>16</bitWidth> 198 </field> 199 <field> 200 <name>RX_NUM_CHAR</name> 201 <description>Nubmer of Characters to receive.</description> 202 <bitOffset>16</bitOffset> 203 <bitWidth>16</bitWidth> 204 </field> 205 </fields> 206 </register> 207 <register> 208 <name>CTRL2</name> 209 <description>Register for controlling SPI peripheral.</description> 210 <addressOffset>0x0C</addressOffset> 211 <access>read-write</access> 212 <fields> 213 <field> 214 <name>CLKPHA</name> 215 <description>Clock Phase.</description> 216 <bitOffset>0</bitOffset> 217 <bitWidth>1</bitWidth> 218 <enumeratedValues> 219 <enumeratedValue> 220 <name>Rising_Edge</name> 221 <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description> 222 <value>0</value> 223 </enumeratedValue> 224 <enumeratedValue> 225 <name>Falling_Edge</name> 226 <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description> 227 <value>1</value> 228 </enumeratedValue> 229 </enumeratedValues> 230 </field> 231 <field> 232 <name>CLKPOL</name> 233 <description>Clock Polarity.</description> 234 <bitOffset>1</bitOffset> 235 <bitWidth>1</bitWidth> 236 <enumeratedValues> 237 <enumeratedValue> 238 <name>Normal</name> 239 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 240 <value>0</value> 241 </enumeratedValue> 242 <enumeratedValue> 243 <name>Inverted</name> 244 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 245 <value>1</value> 246 </enumeratedValue> 247 </enumeratedValues> 248 </field> 249 <field> 250 <name>SCLK_FB_INV</name> 251 <description>Clock Polarity.</description> 252 <bitOffset>4</bitOffset> 253 <bitWidth>1</bitWidth> 254 <enumeratedValues> 255 <enumeratedValue> 256 <name>Normal</name> 257 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 258 <value>0</value> 259 </enumeratedValue> 260 <enumeratedValue> 261 <name>Inverted</name> 262 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 263 <value>1</value> 264 </enumeratedValue> 265 </enumeratedValues> 266 </field> 267 <field> 268 <name>NUMBITS</name> 269 <description>Number of Bits per character.</description> 270 <bitOffset>8</bitOffset> 271 <bitWidth>4</bitWidth> 272 <enumeratedValues> 273 <enumeratedValue> 274 <name>16</name> 275 <description>16 bits per character.</description> 276 <value>0</value> 277 </enumeratedValue> 278 <enumeratedValue> 279 <name>1</name> 280 <description>1 bits per character.</description> 281 <value>1</value> 282 </enumeratedValue> 283 <enumeratedValue> 284 <name>2</name> 285 <description>2 bits per character.</description> 286 <value>2</value> 287 </enumeratedValue> 288 <enumeratedValue> 289 <name>3</name> 290 <description>3 bits per character.</description> 291 <value>3</value> 292 </enumeratedValue> 293 <enumeratedValue> 294 <name>4</name> 295 <description>4 bits per character.</description> 296 <value>4</value> 297 </enumeratedValue> 298 <enumeratedValue> 299 <name>5</name> 300 <description>5 bits per character.</description> 301 <value>5</value> 302 </enumeratedValue> 303 <enumeratedValue> 304 <name>6</name> 305 <description>6 bits per character.</description> 306 <value>6</value> 307 </enumeratedValue> 308 <enumeratedValue> 309 <name>7</name> 310 <description>7 bits per character.</description> 311 <value>7</value> 312 </enumeratedValue> 313 <enumeratedValue> 314 <name>8</name> 315 <description>8 bits per character.</description> 316 <value>8</value> 317 </enumeratedValue> 318 <enumeratedValue> 319 <name>9</name> 320 <description>9 bits per character.</description> 321 <value>9</value> 322 </enumeratedValue> 323 <enumeratedValue> 324 <name>10</name> 325 <description>10 bits per character.</description> 326 <value>10</value> 327 </enumeratedValue> 328 <enumeratedValue> 329 <name>11</name> 330 <description>11 bits per character.</description> 331 <value>11</value> 332 </enumeratedValue> 333 <enumeratedValue> 334 <name>12</name> 335 <description>12 bits per character.</description> 336 <value>12</value> 337 </enumeratedValue> 338 <enumeratedValue> 339 <name>13</name> 340 <description>13 bits per character.</description> 341 <value>13</value> 342 </enumeratedValue> 343 <enumeratedValue> 344 <name>14</name> 345 <description>14 bits per character.</description> 346 <value>14</value> 347 </enumeratedValue> 348 <enumeratedValue> 349 <name>15</name> 350 <description>15 bits per character.</description> 351 <value>15</value> 352 </enumeratedValue> 353 </enumeratedValues> 354 </field> 355 <field> 356 <name>DATA_WIDTH</name> 357 <description>SPI Data width.</description> 358 <bitOffset>12</bitOffset> 359 <bitWidth>2</bitWidth> 360 <enumeratedValues> 361 <enumeratedValue> 362 <name>Mono</name> 363 <description>1 data pin.</description> 364 <value>0</value> 365 </enumeratedValue> 366 <enumeratedValue> 367 <name>Dual</name> 368 <description>2 data pins.</description> 369 <value>1</value> 370 </enumeratedValue> 371 <enumeratedValue> 372 <name>Quad</name> 373 <description>4 data pins.</description> 374 <value>2</value> 375 </enumeratedValue> 376 </enumeratedValues> 377 </field> 378 <field> 379 <name>THREE_WIRE</name> 380 <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description> 381 <bitOffset>15</bitOffset> 382 <bitWidth>1</bitWidth> 383 <enumeratedValues> 384 <enumeratedValue> 385 <name>dis</name> 386 <description>Use four wire mode (Mono only).</description> 387 <value>0</value> 388 </enumeratedValue> 389 <enumeratedValue> 390 <name>en</name> 391 <description>Use three wire mode.</description> 392 <value>1</value> 393 </enumeratedValue> 394 </enumeratedValues> 395 </field> 396 <field> 397 <name>SS_POL</name> 398 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 399 <bitOffset>16</bitOffset> 400 <bitWidth>8</bitWidth> 401 <enumeratedValues> 402 <enumeratedValue> 403 <name>SS0_high</name> 404 <description>SS0 active high.</description> 405 <value>0x1</value> 406 </enumeratedValue> 407 <enumeratedValue> 408 <name>SS1_high</name> 409 <description>SS1 active high.</description> 410 <value>0x2</value> 411 </enumeratedValue> 412 <enumeratedValue> 413 <name>SS2_high</name> 414 <description>SS2 active high.</description> 415 <value>0x4</value> 416 </enumeratedValue> 417 <enumeratedValue> 418 <name>SS3_high</name> 419 <description>SS3 active high.</description> 420 <value>0x8</value> 421 </enumeratedValue> 422 </enumeratedValues> 423 </field> 424 </fields> 425 </register> 426 <register> 427 <name>SSTIME</name> 428 <description>Register for controlling SPI peripheral/Slave Select Timing.</description> 429 <addressOffset>0x10</addressOffset> 430 <access>read-write</access> 431 <fields> 432 <field> 433 <name>PRE</name> 434 <description>Slave Select Pre delay 1.</description> 435 <bitOffset>0</bitOffset> 436 <bitWidth>8</bitWidth> 437 <enumeratedValues> 438 <enumeratedValue> 439 <name>256</name> 440 <description>256 system clocks between SS active and first serial clock edge.</description> 441 <value>0</value> 442 </enumeratedValue> 443 </enumeratedValues> 444 </field> 445 <field> 446 <name>POST</name> 447 <description>Slave Select Post delay 2.</description> 448 <bitOffset>8</bitOffset> 449 <bitWidth>8</bitWidth> 450 <enumeratedValues> 451 <enumeratedValue> 452 <name>256</name> 453 <description>256 system clocks between last serial clock edge and SS inactive.</description> 454 <value>0</value> 455 </enumeratedValue> 456 </enumeratedValues> 457 </field> 458 <field> 459 <name>INACT</name> 460 <description>Slave Select Inactive delay.</description> 461 <bitOffset>16</bitOffset> 462 <bitWidth>8</bitWidth> 463 <enumeratedValues> 464 <enumeratedValue> 465 <name>256</name> 466 <description>256 system clocks between transactions.</description> 467 <value>0</value> 468 </enumeratedValue> 469 </enumeratedValues> 470 </field> 471 </fields> 472 </register> 473 <register> 474 <name>CLKCTRL</name> 475 <description>Register for controlling SPI clock rate.</description> 476 <addressOffset>0x14</addressOffset> 477 <access>read-write</access> 478 <fields> 479 <field> 480 <name>LO</name> 481 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 482 <bitOffset>0</bitOffset> 483 <bitWidth>8</bitWidth> 484 <enumeratedValues> 485 <enumeratedValue> 486 <name>Dis</name> 487 <description>Duty cycle control of serial clock generation is disabled.</description> 488 <value>0</value> 489 </enumeratedValue> 490 </enumeratedValues> 491 </field> 492 <field> 493 <name>HI</name> 494 <description>High duty cycle control. In timer mode, reload[15:8].</description> 495 <bitOffset>8</bitOffset> 496 <bitWidth>8</bitWidth> 497 <enumeratedValues> 498 <enumeratedValue> 499 <name>Dis</name> 500 <description>Duty cycle control of serial clock generation is disabled.</description> 501 <value>0</value> 502 </enumeratedValue> 503 </enumeratedValues> 504 </field> 505 <field> 506 <name>CLKDIV</name> 507 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 508 <bitOffset>16</bitOffset> 509 <bitWidth>4</bitWidth> 510 </field> 511 <field> 512 <name>AFP_FCD</name> 513 <description>AFP FCD.</description> 514 <bitOffset>24</bitOffset> 515 <bitWidth>3</bitWidth> 516 </field> 517 </fields> 518 </register> 519 <register> 520 <name>DMA</name> 521 <description>Register for controlling DMA.</description> 522 <addressOffset>0x1C</addressOffset> 523 <access>read-write</access> 524 <fields> 525 <field> 526 <name>TX_THD_VAL</name> 527 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 528 <bitOffset>0</bitOffset> 529 <bitWidth>5</bitWidth> 530 </field> 531 <field> 532 <name>TX_FIFO_EN</name> 533 <description>Transmit FIFO enabled for SPI transactions.</description> 534 <bitOffset>6</bitOffset> 535 <bitWidth>1</bitWidth> 536 <enumeratedValues> 537 <enumeratedValue> 538 <name>dis</name> 539 <description>Transmit FIFO is not enabled.</description> 540 <value>0</value> 541 </enumeratedValue> 542 <enumeratedValue> 543 <name>en</name> 544 <description>Transmit FIFO is enabled.</description> 545 <value>1</value> 546 </enumeratedValue> 547 </enumeratedValues> 548 </field> 549 <field> 550 <name>TX_FLUSH</name> 551 <description>Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 552 <bitOffset>7</bitOffset> 553 <bitWidth>1</bitWidth> 554 <enumeratedValues> 555 <enumeratedValue> 556 <name>CLEAR</name> 557 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 558 <value>1</value> 559 </enumeratedValue> 560 </enumeratedValues> 561 </field> 562 <field> 563 <name>TX_LVL</name> 564 <description>Count of entries in TX FIFO.</description> 565 <bitOffset>8</bitOffset> 566 <bitWidth>6</bitWidth> 567 <access>read-only</access> 568 </field> 569 <field> 570 <name>TX_EN</name> 571 <description>TX DMA Enable.</description> 572 <bitOffset>15</bitOffset> 573 <bitWidth>1</bitWidth> 574 <enumeratedValues> 575 <enumeratedValue> 576 <name>DIS</name> 577 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 578 <value>0</value> 579 </enumeratedValue> 580 <enumeratedValue> 581 <name>en</name> 582 <description>TX DMA requests are enabled.</description> 583 <value>1</value> 584 </enumeratedValue> 585 </enumeratedValues> 586 </field> 587 <field> 588 <name>RX_THD_VAL</name> 589 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 590 <bitOffset>16</bitOffset> 591 <bitWidth>5</bitWidth> 592 </field> 593 <field> 594 <name>RX_FIFO_EN</name> 595 <description>Receive FIFO enabled for SPI transactions.</description> 596 <bitOffset>22</bitOffset> 597 <bitWidth>1</bitWidth> 598 <enumeratedValues> 599 <enumeratedValue> 600 <name>DIS</name> 601 <description>Receive FIFO is not enabled.</description> 602 <value>0</value> 603 </enumeratedValue> 604 <enumeratedValue> 605 <name>en</name> 606 <description>Receive FIFO is enabled.</description> 607 <value>1</value> 608 </enumeratedValue> 609 </enumeratedValues> 610 </field> 611 <field> 612 <name>RX_FLUSH</name> 613 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 614 <bitOffset>23</bitOffset> 615 <bitWidth>1</bitWidth> 616 <enumeratedValues> 617 <enumeratedValue> 618 <name>CLEAR</name> 619 <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description> 620 <value>1</value> 621 </enumeratedValue> 622 </enumeratedValues> 623 </field> 624 <field> 625 <name>RX_LVL</name> 626 <description>Count of entries in RX FIFO.</description> 627 <bitOffset>24</bitOffset> 628 <bitWidth>6</bitWidth> 629 <access>read-only</access> 630 </field> 631 <field> 632 <name>RX_EN</name> 633 <description>RX DMA Enable.</description> 634 <bitOffset>31</bitOffset> 635 <bitWidth>1</bitWidth> 636 <enumeratedValues> 637 <enumeratedValue> 638 <name>dis</name> 639 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 640 <value>0</value> 641 </enumeratedValue> 642 <enumeratedValue> 643 <name>en</name> 644 <description>RX DMA requests are enabled.</description> 645 <value>1</value> 646 </enumeratedValue> 647 </enumeratedValues> 648 </field> 649 </fields> 650 </register> 651 <register> 652 <name>INTFL</name> 653 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 654 <addressOffset>0x20</addressOffset> 655 <access>read-write</access> 656 <fields> 657 <field> 658 <name>TX_THD</name> 659 <description>TX FIFO Threshold Crossed.</description> 660 <bitOffset>0</bitOffset> 661 <bitWidth>1</bitWidth> 662 <enumeratedValues> 663 <enumeratedValue> 664 <name>clear</name> 665 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 666 <value>1</value> 667 </enumeratedValue> 668 </enumeratedValues> 669 </field> 670 <field> 671 <name>TX_EM</name> 672 <description>TX FIFO Empty.</description> 673 <bitOffset>1</bitOffset> 674 <bitWidth>1</bitWidth> 675 <enumeratedValues> 676 <enumeratedValue> 677 <name>clear</name> 678 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 679 <value>1</value> 680 </enumeratedValue> 681 </enumeratedValues> 682 </field> 683 <field> 684 <name>RX_THD</name> 685 <description>RX FIFO Threshold Crossed.</description> 686 <bitOffset>2</bitOffset> 687 <bitWidth>1</bitWidth> 688 <enumeratedValues> 689 <enumeratedValue> 690 <name>clear</name> 691 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 692 <value>1</value> 693 </enumeratedValue> 694 </enumeratedValues> 695 </field> 696 <field> 697 <name>RX_FULL</name> 698 <description>RX FIFO FULL.</description> 699 <bitOffset>3</bitOffset> 700 <bitWidth>1</bitWidth> 701 <enumeratedValues> 702 <enumeratedValue> 703 <name>clear</name> 704 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 705 <value>1</value> 706 </enumeratedValue> 707 </enumeratedValues> 708 </field> 709 <field> 710 <name>SSA</name> 711 <description>Slave Select Asserted.</description> 712 <bitOffset>4</bitOffset> 713 <bitWidth>1</bitWidth> 714 <enumeratedValues> 715 <enumeratedValue> 716 <name>clear</name> 717 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 718 <value>1</value> 719 </enumeratedValue> 720 </enumeratedValues> 721 </field> 722 <field> 723 <name>SSD</name> 724 <description>Slave Select Deasserted.</description> 725 <bitOffset>5</bitOffset> 726 <bitWidth>1</bitWidth> 727 <enumeratedValues> 728 <enumeratedValue> 729 <name>clear</name> 730 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 731 <value>1</value> 732 </enumeratedValue> 733 </enumeratedValues> 734 </field> 735 <field> 736 <name>FAULT</name> 737 <description>Multi-Master Mode Fault.</description> 738 <bitOffset>8</bitOffset> 739 <bitWidth>1</bitWidth> 740 <enumeratedValues> 741 <enumeratedValue> 742 <name>clear</name> 743 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 744 <value>1</value> 745 </enumeratedValue> 746 </enumeratedValues> 747 </field> 748 <field> 749 <name>ABORT</name> 750 <description>Slave Abort Detected.</description> 751 <bitOffset>9</bitOffset> 752 <bitWidth>1</bitWidth> 753 <enumeratedValues> 754 <enumeratedValue> 755 <name>clear</name> 756 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 757 <value>1</value> 758 </enumeratedValue> 759 </enumeratedValues> 760 </field> 761 <field> 762 <name>MST_DONE</name> 763 <description>Master Done, set when SPI Master has completed any transactions.</description> 764 <bitOffset>11</bitOffset> 765 <bitWidth>1</bitWidth> 766 <enumeratedValues> 767 <enumeratedValue> 768 <name>clear</name> 769 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 770 <value>1</value> 771 </enumeratedValue> 772 </enumeratedValues> 773 </field> 774 <field> 775 <name>TX_OV</name> 776 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 777 <bitOffset>12</bitOffset> 778 <bitWidth>1</bitWidth> 779 <enumeratedValues> 780 <enumeratedValue> 781 <name>clear</name> 782 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 783 <value>1</value> 784 </enumeratedValue> 785 </enumeratedValues> 786 </field> 787 <field> 788 <name>TX_UN</name> 789 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 790 <bitOffset>13</bitOffset> 791 <bitWidth>1</bitWidth> 792 <enumeratedValues> 793 <enumeratedValue> 794 <name>clear</name> 795 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 796 <value>1</value> 797 </enumeratedValue> 798 </enumeratedValues> 799 </field> 800 <field> 801 <name>RX_OV</name> 802 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 803 <bitOffset>14</bitOffset> 804 <bitWidth>1</bitWidth> 805 <enumeratedValues> 806 <enumeratedValue> 807 <name>clear</name> 808 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 809 <value>1</value> 810 </enumeratedValue> 811 </enumeratedValues> 812 </field> 813 <field> 814 <name>RX_UN</name> 815 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 816 <bitOffset>15</bitOffset> 817 <bitWidth>1</bitWidth> 818 <enumeratedValues> 819 <enumeratedValue> 820 <name>clear</name> 821 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 822 <value>1</value> 823 </enumeratedValue> 824 </enumeratedValues> 825 </field> 826 </fields> 827 </register> 828 <register> 829 <name>INTEN</name> 830 <description>Register for enabling interrupts.</description> 831 <addressOffset>0x24</addressOffset> 832 <access>read-write</access> 833 <fields> 834 <field> 835 <name>TX_THD</name> 836 <description>TX FIFO Threshold interrupt enable.</description> 837 <bitOffset>0</bitOffset> 838 <bitWidth>1</bitWidth> 839 <enumeratedValues> 840 <enumeratedValue> 841 <name>dis</name> 842 <description>Interrupt is disabled.</description> 843 <value>0</value> 844 </enumeratedValue> 845 <enumeratedValue> 846 <name>en</name> 847 <description>Interrupt is enabled.</description> 848 <value>1</value> 849 </enumeratedValue> 850 </enumeratedValues> 851 </field> 852 <field> 853 <name>TX_EM</name> 854 <description>TX FIFO Empty interrupt enable.</description> 855 <bitOffset>1</bitOffset> 856 <bitWidth>1</bitWidth> 857 <enumeratedValues> 858 <enumeratedValue> 859 <name>dis</name> 860 <description>Interrupt is disabled.</description> 861 <value>0</value> 862 </enumeratedValue> 863 <enumeratedValue> 864 <name>en</name> 865 <description>Interrupt is enabled.</description> 866 <value>1</value> 867 </enumeratedValue> 868 </enumeratedValues> 869 </field> 870 <field> 871 <name>RX_THD</name> 872 <description>RX FIFO Threshold Crossed interrupt enable.</description> 873 <bitOffset>2</bitOffset> 874 <bitWidth>1</bitWidth> 875 <enumeratedValues> 876 <enumeratedValue> 877 <name>dis</name> 878 <description>Interrupt is disabled.</description> 879 <value>0</value> 880 </enumeratedValue> 881 <enumeratedValue> 882 <name>en</name> 883 <description>Interrupt is enabled.</description> 884 <value>1</value> 885 </enumeratedValue> 886 </enumeratedValues> 887 </field> 888 <field> 889 <name>RX_FULL</name> 890 <description>RX FIFO FULL interrupt enable.</description> 891 <bitOffset>3</bitOffset> 892 <bitWidth>1</bitWidth> 893 <enumeratedValues> 894 <enumeratedValue> 895 <name>dis</name> 896 <description>Interrupt is disabled.</description> 897 <value>0</value> 898 </enumeratedValue> 899 <enumeratedValue> 900 <name>en</name> 901 <description>Interrupt is enabled.</description> 902 <value>1</value> 903 </enumeratedValue> 904 </enumeratedValues> 905 </field> 906 <field> 907 <name>SSA</name> 908 <description>Slave Select Asserted interrupt enable.</description> 909 <bitOffset>4</bitOffset> 910 <bitWidth>1</bitWidth> 911 <enumeratedValues> 912 <enumeratedValue> 913 <name>dis</name> 914 <description>Interrupt is disabled.</description> 915 <value>0</value> 916 </enumeratedValue> 917 <enumeratedValue> 918 <name>en</name> 919 <description>Interrupt is enabled.</description> 920 <value>1</value> 921 </enumeratedValue> 922 </enumeratedValues> 923 </field> 924 <field> 925 <name>SSD</name> 926 <description>Slave Select Deasserted interrupt enable.</description> 927 <bitOffset>5</bitOffset> 928 <bitWidth>1</bitWidth> 929 <enumeratedValues> 930 <enumeratedValue> 931 <name>dis</name> 932 <description>Interrupt is disabled.</description> 933 <value>0</value> 934 </enumeratedValue> 935 <enumeratedValue> 936 <name>en</name> 937 <description>Interrupt is enabled.</description> 938 <value>1</value> 939 </enumeratedValue> 940 </enumeratedValues> 941 </field> 942 <field> 943 <name>FAULT</name> 944 <description>Multi-Master Mode Fault interrupt enable.</description> 945 <bitOffset>8</bitOffset> 946 <bitWidth>1</bitWidth> 947 <enumeratedValues> 948 <enumeratedValue> 949 <name>dis</name> 950 <description>Interrupt is disabled.</description> 951 <value>0</value> 952 </enumeratedValue> 953 <enumeratedValue> 954 <name>en</name> 955 <description>Interrupt is enabled.</description> 956 <value>1</value> 957 </enumeratedValue> 958 </enumeratedValues> 959 </field> 960 <field> 961 <name>ABORT</name> 962 <description>Slave Abort Detected interrupt enable.</description> 963 <bitOffset>9</bitOffset> 964 <bitWidth>1</bitWidth> 965 <enumeratedValues> 966 <enumeratedValue> 967 <name>dis</name> 968 <description>Interrupt is disabled.</description> 969 <value>0</value> 970 </enumeratedValue> 971 <enumeratedValue> 972 <name>en</name> 973 <description>Interrupt is enabled.</description> 974 <value>1</value> 975 </enumeratedValue> 976 </enumeratedValues> 977 </field> 978 <field> 979 <name>MST_DONE</name> 980 <description>Master Done interrupt enable.</description> 981 <bitOffset>11</bitOffset> 982 <bitWidth>1</bitWidth> 983 <enumeratedValues> 984 <enumeratedValue> 985 <name>dis</name> 986 <description>Interrupt is disabled.</description> 987 <value>0</value> 988 </enumeratedValue> 989 <enumeratedValue> 990 <name>en</name> 991 <description>Interrupt is enabled.</description> 992 <value>1</value> 993 </enumeratedValue> 994 </enumeratedValues> 995 </field> 996 <field> 997 <name>TX_OV</name> 998 <description>Transmit FIFO Overrun interrupt enable.</description> 999 <bitOffset>12</bitOffset> 1000 <bitWidth>1</bitWidth> 1001 <enumeratedValues> 1002 <enumeratedValue> 1003 <name>dis</name> 1004 <description>Interrupt is disabled.</description> 1005 <value>0</value> 1006 </enumeratedValue> 1007 <enumeratedValue> 1008 <name>en</name> 1009 <description>Interrupt is enabled.</description> 1010 <value>1</value> 1011 </enumeratedValue> 1012 </enumeratedValues> 1013 </field> 1014 <field> 1015 <name>TX_UN</name> 1016 <description>Transmit FIFO Underrun interrupt enable.</description> 1017 <bitOffset>13</bitOffset> 1018 <bitWidth>1</bitWidth> 1019 <enumeratedValues> 1020 <enumeratedValue> 1021 <name>dis</name> 1022 <description>Interrupt is disabled.</description> 1023 <value>0</value> 1024 </enumeratedValue> 1025 <enumeratedValue> 1026 <name>en</name> 1027 <description>Interrupt is enabled.</description> 1028 <value>1</value> 1029 </enumeratedValue> 1030 </enumeratedValues> 1031 </field> 1032 <field> 1033 <name>RX_OV</name> 1034 <description>Receive FIFO Overrun interrupt enable.</description> 1035 <bitOffset>14</bitOffset> 1036 <bitWidth>1</bitWidth> 1037 <enumeratedValues> 1038 <enumeratedValue> 1039 <name>dis</name> 1040 <description>Interrupt is disabled.</description> 1041 <value>0</value> 1042 </enumeratedValue> 1043 <enumeratedValue> 1044 <name>en</name> 1045 <description>Interrupt is enabled.</description> 1046 <value>1</value> 1047 </enumeratedValue> 1048 </enumeratedValues> 1049 </field> 1050 <field> 1051 <name>RX_UN</name> 1052 <description>Receive FIFO Underrun interrupt enable.</description> 1053 <bitOffset>15</bitOffset> 1054 <bitWidth>1</bitWidth> 1055 <enumeratedValues> 1056 <enumeratedValue> 1057 <name>dis</name> 1058 <description>Interrupt is disabled.</description> 1059 <value>0</value> 1060 </enumeratedValue> 1061 <enumeratedValue> 1062 <name>en</name> 1063 <description>Interrupt is enabled.</description> 1064 <value>1</value> 1065 </enumeratedValue> 1066 </enumeratedValues> 1067 </field> 1068 </fields> 1069 </register> 1070 <register> 1071 <name>WKFL</name> 1072 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 1073 <addressOffset>0x28</addressOffset> 1074 <access>read-write</access> 1075 <fields> 1076 <field> 1077 <name>TX_THD</name> 1078 <description>Wake on TX FIFO Threshold Crossed.</description> 1079 <bitOffset>0</bitOffset> 1080 <bitWidth>1</bitWidth> 1081 <enumeratedValues> 1082 <enumeratedValue> 1083 <name>clear</name> 1084 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1085 <value>1</value> 1086 </enumeratedValue> 1087 </enumeratedValues> 1088 </field> 1089 <field> 1090 <name>TX_EM</name> 1091 <description>Wake on TX FIFO Empty.</description> 1092 <bitOffset>1</bitOffset> 1093 <bitWidth>1</bitWidth> 1094 <enumeratedValues> 1095 <enumeratedValue> 1096 <name>clear</name> 1097 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1098 <value>1</value> 1099 </enumeratedValue> 1100 </enumeratedValues> 1101 </field> 1102 <field> 1103 <name>RX_THD</name> 1104 <description>Wake on RX FIFO Threshold Crossed.</description> 1105 <bitOffset>2</bitOffset> 1106 <bitWidth>1</bitWidth> 1107 <enumeratedValues> 1108 <enumeratedValue> 1109 <name>clear</name> 1110 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1111 <value>1</value> 1112 </enumeratedValue> 1113 </enumeratedValues> 1114 </field> 1115 <field> 1116 <name>RX_FULL</name> 1117 <description>Wake on RX FIFO Full.</description> 1118 <bitOffset>3</bitOffset> 1119 <bitWidth>1</bitWidth> 1120 <enumeratedValues> 1121 <enumeratedValue> 1122 <name>clear</name> 1123 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1124 <value>1</value> 1125 </enumeratedValue> 1126 </enumeratedValues> 1127 </field> 1128 </fields> 1129 </register> 1130 <register> 1131 <name>WKEN</name> 1132 <description>Register for wake up enable.</description> 1133 <addressOffset>0x2C</addressOffset> 1134 <access>read-write</access> 1135 <fields> 1136 <field> 1137 <name>TX_THD</name> 1138 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 1139 <bitOffset>0</bitOffset> 1140 <bitWidth>1</bitWidth> 1141 <enumeratedValues> 1142 <enumeratedValue> 1143 <name>dis</name> 1144 <description>Wakeup source disabled.</description> 1145 <value>0</value> 1146 </enumeratedValue> 1147 <enumeratedValue> 1148 <name>en</name> 1149 <description>Wakeup source enabled.</description> 1150 <value>1</value> 1151 </enumeratedValue> 1152 </enumeratedValues> 1153 </field> 1154 <field> 1155 <name>TX_EM</name> 1156 <description>Wake on TX FIFO Empty Enable.</description> 1157 <bitOffset>1</bitOffset> 1158 <bitWidth>1</bitWidth> 1159 <enumeratedValues> 1160 <enumeratedValue> 1161 <name>dis</name> 1162 <description>Wakeup source disabled.</description> 1163 <value>0</value> 1164 </enumeratedValue> 1165 <enumeratedValue> 1166 <name>en</name> 1167 <description>Wakeup source enabled.</description> 1168 <value>1</value> 1169 </enumeratedValue> 1170 </enumeratedValues> 1171 </field> 1172 <field> 1173 <name>RX_THD</name> 1174 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 1175 <bitOffset>2</bitOffset> 1176 <bitWidth>1</bitWidth> 1177 <enumeratedValues> 1178 <enumeratedValue> 1179 <name>dis</name> 1180 <description>Wakeup source disabled.</description> 1181 <value>0</value> 1182 </enumeratedValue> 1183 <enumeratedValue> 1184 <name>en</name> 1185 <description>Wakeup source enabled.</description> 1186 <value>1</value> 1187 </enumeratedValue> 1188 </enumeratedValues> 1189 </field> 1190 <field> 1191 <name>RX_FULL</name> 1192 <description>Wake on RX FIFO Full Enable.</description> 1193 <bitOffset>3</bitOffset> 1194 <bitWidth>1</bitWidth> 1195 <enumeratedValues> 1196 <enumeratedValue> 1197 <name>dis</name> 1198 <description>Wakeup source disabled.</description> 1199 <value>0</value> 1200 </enumeratedValue> 1201 <enumeratedValue> 1202 <name>en</name> 1203 <description>Wakeup source enabled.</description> 1204 <value>1</value> 1205 </enumeratedValue> 1206 </enumeratedValues> 1207 </field> 1208 </fields> 1209 </register> 1210 <register> 1211 <name>STAT</name> 1212 <description>SPI Status register.</description> 1213 <addressOffset>0x30</addressOffset> 1214 <access>read-only</access> 1215 <fields> 1216 <field> 1217 <name>BUSY</name> 1218 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description> 1219 <bitOffset>0</bitOffset> 1220 <bitWidth>1</bitWidth> 1221 <enumeratedValues> 1222 <enumeratedValue> 1223 <name>not</name> 1224 <description>SPI not active.</description> 1225 <value>0</value> 1226 </enumeratedValue> 1227 <enumeratedValue> 1228 <name>active</name> 1229 <description>SPI active.</description> 1230 <value>1</value> 1231 </enumeratedValue> 1232 </enumeratedValues> 1233 </field> 1234 </fields> 1235 </register> 1236 </registers> 1237 </peripheral> 1238 <!-- SPI: Serial Peripheral Interface --> 1239</device>
