1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPI0</name> 5 <description>SPI peripheral.</description> 6 <baseAddress>0x40046000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>SPI0</name> 14 <value>16</value> 15 </interrupt> 16 <registers> 17 <register> 18 <name>FIFO32</name> 19 <description>Register for reading and writing the FIFO.</description> 20 <addressOffset>0x00</addressOffset> 21 <size>32</size> 22 <access>read-write</access> 23 <fields> 24 <field> 25 <name>DATA</name> 26 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <dim>2</dim> 34 <dimIncrement>2</dimIncrement> 35 <name>FIFO16[%s]</name> 36 <description>Register for reading and writing the FIFO.</description> 37 <alternateRegister>FIFO32</alternateRegister> 38 <addressOffset>0x00</addressOffset> 39 <size>16</size> 40 <access>read-write</access> 41 <fields> 42 <field> 43 <name>DATA</name> 44 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 45 <bitOffset>0</bitOffset> 46 <bitWidth>16</bitWidth> 47 </field> 48 </fields> 49 </register> 50 <register> 51 <dim>4</dim> 52 <dimIncrement>1</dimIncrement> 53 <name>FIFO8[%s]</name> 54 <description>Register for reading and writing the FIFO.</description> 55 <alternateRegister>FIFO32</alternateRegister> 56 <addressOffset>0x00</addressOffset> 57 <size>8</size> 58 <access>read-write</access> 59 <fields> 60 <field> 61 <name>DATA</name> 62 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 63 <bitOffset>0</bitOffset> 64 <bitWidth>8</bitWidth> 65 </field> 66 </fields> 67 </register> 68 <register> 69 <name>CTRL0</name> 70 <description>Register for controlling SPI peripheral.</description> 71 <addressOffset>0x04</addressOffset> 72 <access>read-write</access> 73 <fields> 74 <field> 75 <name>SPI_EN</name> 76 <description>SPI Enable.</description> 77 <bitOffset>0</bitOffset> 78 <bitWidth>1</bitWidth> 79 <enumeratedValues> 80 <enumeratedValue> 81 <name>dis</name> 82 <description>SPI is disabled.</description> 83 <value>0</value> 84 </enumeratedValue> 85 <enumeratedValue> 86 <name>en</name> 87 <description>SPI is enabled.</description> 88 <value>1</value> 89 </enumeratedValue> 90 </enumeratedValues> 91 </field> 92 <field> 93 <name>MM_EN</name> 94 <description>Master Mode Enable.</description> 95 <bitOffset>1</bitOffset> 96 <bitWidth>1</bitWidth> 97 <enumeratedValues> 98 <enumeratedValue> 99 <name>dis</name> 100 <description>SPI is Slave mode.</description> 101 <value>0</value> 102 </enumeratedValue> 103 <enumeratedValue> 104 <name>en</name> 105 <description>SPI is Master mode.</description> 106 <value>1</value> 107 </enumeratedValue> 108 </enumeratedValues> 109 </field> 110 <field> 111 <name>SS_IO</name> 112 <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 113 <bitOffset>4</bitOffset> 114 <bitWidth>1</bitWidth> 115 <enumeratedValues> 116 <enumeratedValue> 117 <name>output</name> 118 <description>Slave select 0 is output.</description> 119 <value>0</value> 120 </enumeratedValue> 121 <enumeratedValue> 122 <name>input</name> 123 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 124 <value>1</value> 125 </enumeratedValue> 126 </enumeratedValues> 127 </field> 128 <field> 129 <name>START</name> 130 <description>Start Transmit.</description> 131 <bitOffset>5</bitOffset> 132 <bitWidth>1</bitWidth> 133 <enumeratedValues> 134 <enumeratedValue> 135 <name>start</name> 136 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description> 137 <value>1</value> 138 </enumeratedValue> 139 </enumeratedValues> 140 </field> 141 <field> 142 <name>SS_CTRL</name> 143 <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description> 144 <bitOffset>8</bitOffset> 145 <bitWidth>1</bitWidth> 146 <enumeratedValues> 147 <enumeratedValue> 148 <name>deassert</name> 149 <description>SPI De-asserts Slave Select at the end of a transaction.</description> 150 <value>0</value> 151 </enumeratedValue> 152 <enumeratedValue> 153 <name>assert</name> 154 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 155 <value>1</value> 156 </enumeratedValue> 157 </enumeratedValues> 158 </field> 159 <field> 160 <name>SS_SEL</name> 161 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 162 <bitOffset>16</bitOffset> 163 <bitWidth>4</bitWidth> 164 <enumeratedValues> 165 <enumeratedValue> 166 <name>SS0</name> 167 <description>SS0 is selected.</description> 168 <value>0x1</value> 169 </enumeratedValue> 170 <enumeratedValue> 171 <name>SS1</name> 172 <description>SS1 is selected.</description> 173 <value>0x2</value> 174 </enumeratedValue> 175 <enumeratedValue> 176 <name>SS2</name> 177 <description>SS2 is selected.</description> 178 <value>0x4</value> 179 </enumeratedValue> 180 <enumeratedValue> 181 <name>SS3</name> 182 <description>SS3 is selected.</description> 183 <value>0x8</value> 184 </enumeratedValue> 185 </enumeratedValues> 186 </field> 187 </fields> 188 </register> 189 <register> 190 <name>CTRL1</name> 191 <description>Register for controlling SPI peripheral.</description> 192 <addressOffset>0x08</addressOffset> 193 <access>read-write</access> 194 <fields> 195 <field> 196 <name>TX_NUM_CHAR</name> 197 <description>Nubmer of Characters to transmit.</description> 198 <bitOffset>0</bitOffset> 199 <bitWidth>16</bitWidth> 200 </field> 201 <field> 202 <name>RX_NUM_CHAR</name> 203 <description>Nubmer of Characters to receive.</description> 204 <bitOffset>16</bitOffset> 205 <bitWidth>16</bitWidth> 206 </field> 207 </fields> 208 </register> 209 <register> 210 <name>CTRL2</name> 211 <description>Register for controlling SPI peripheral.</description> 212 <addressOffset>0x0C</addressOffset> 213 <access>read-write</access> 214 <fields> 215 <field> 216 <name>CLK_PHA</name> 217 <description>Clock Phase.</description> 218 <bitOffset>0</bitOffset> 219 <bitWidth>1</bitWidth> 220 <enumeratedValues> 221 <enumeratedValue> 222 <name>risingEdge</name> 223 <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description> 224 <value>0</value> 225 </enumeratedValue> 226 <enumeratedValue> 227 <name>fallingEdge</name> 228 <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description> 229 <value>1</value> 230 </enumeratedValue> 231 </enumeratedValues> 232 </field> 233 <field> 234 <name>CLK_POL</name> 235 <description>Clock Polarity.</description> 236 <bitOffset>1</bitOffset> 237 <bitWidth>1</bitWidth> 238 <enumeratedValues> 239 <enumeratedValue> 240 <name>Normal</name> 241 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 242 <value>0</value> 243 </enumeratedValue> 244 <enumeratedValue> 245 <name>Inverted</name> 246 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 247 <value>1</value> 248 </enumeratedValue> 249 </enumeratedValues> 250 </field> 251 <field> 252 <name>NUM_BITS</name> 253 <description>Number of Bits per character.</description> 254 <bitOffset>8</bitOffset> 255 <bitWidth>4</bitWidth> 256 <enumeratedValues> 257 <enumeratedValue> 258 <name>16BITS</name> 259 <description>16 bits per character.</description> 260 <value>0</value> 261 </enumeratedValue> 262 <enumeratedValue> 263 <name>1BITS</name> 264 <description>1 bits per character.</description> 265 <value>1</value> 266 </enumeratedValue> 267 <enumeratedValue> 268 <name>2BITS</name> 269 <description>2 bits per character.</description> 270 <value>2</value> 271 </enumeratedValue> 272 <enumeratedValue> 273 <name>3BITS</name> 274 <description>3 bits per character.</description> 275 <value>3</value> 276 </enumeratedValue> 277 <enumeratedValue> 278 <name>4BITS</name> 279 <description>4 bits per character.</description> 280 <value>4</value> 281 </enumeratedValue> 282 <enumeratedValue> 283 <name>5BITS</name> 284 <description>5 bits per character.</description> 285 <value>5</value> 286 </enumeratedValue> 287 <enumeratedValue> 288 <name>6BITS</name> 289 <description>6 bits per character.</description> 290 <value>6</value> 291 </enumeratedValue> 292 <enumeratedValue> 293 <name>7BITS</name> 294 <description>7 bits per character.</description> 295 <value>7</value> 296 </enumeratedValue> 297 <enumeratedValue> 298 <name>8BITS</name> 299 <description>8 bits per character.</description> 300 <value>8</value> 301 </enumeratedValue> 302 <enumeratedValue> 303 <name>9BITS</name> 304 <description>9 bits per character.</description> 305 <value>9</value> 306 </enumeratedValue> 307 <enumeratedValue> 308 <name>10BITS</name> 309 <description>10 bits per character.</description> 310 <value>10</value> 311 </enumeratedValue> 312 <enumeratedValue> 313 <name>11BITS</name> 314 <description>11 bits per character.</description> 315 <value>11</value> 316 </enumeratedValue> 317 <enumeratedValue> 318 <name>12BITS</name> 319 <description>12 bits per character.</description> 320 <value>12</value> 321 </enumeratedValue> 322 <enumeratedValue> 323 <name>13BITS</name> 324 <description>13 bits per character.</description> 325 <value>13</value> 326 </enumeratedValue> 327 <enumeratedValue> 328 <name>14BITS</name> 329 <description>14 bits per character.</description> 330 <value>14</value> 331 </enumeratedValue> 332 <enumeratedValue> 333 <name>15BITS</name> 334 <description>15 bits per character.</description> 335 <value>15</value> 336 </enumeratedValue> 337 </enumeratedValues> 338 </field> 339 <field> 340 <name>BUS_WIDTH</name> 341 <description>SPI Data width.</description> 342 <bitOffset>12</bitOffset> 343 <bitWidth>2</bitWidth> 344 <enumeratedValues> 345 <enumeratedValue> 346 <name>Mono</name> 347 <description>1 data pin.</description> 348 <value>0</value> 349 </enumeratedValue> 350 <enumeratedValue> 351 <name>Dual</name> 352 <description>2 data pins.</description> 353 <value>1</value> 354 </enumeratedValue> 355 <enumeratedValue> 356 <name>Quad</name> 357 <description>4 data pins.</description> 358 <value>2</value> 359 </enumeratedValue> 360 </enumeratedValues> 361 </field> 362 <field> 363 <name>THREE_WIRE</name> 364 <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description> 365 <bitOffset>15</bitOffset> 366 <bitWidth>1</bitWidth> 367 <enumeratedValues> 368 <enumeratedValue> 369 <name>4wire</name> 370 <description>Use four wire mode (Mono only).</description> 371 <value>0</value> 372 </enumeratedValue> 373 <enumeratedValue> 374 <name>3wire</name> 375 <description>Use three wire mode.</description> 376 <value>1</value> 377 </enumeratedValue> 378 </enumeratedValues> 379 </field> 380 <field> 381 <name>SS_POL</name> 382 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 383 <bitOffset>16</bitOffset> 384 <bitWidth>8</bitWidth> 385 <enumeratedValues> 386 <enumeratedValue> 387 <name>SS0_high</name> 388 <description>SS0 active high.</description> 389 <value>0x1</value> 390 </enumeratedValue> 391 <enumeratedValue> 392 <name>SS1_high</name> 393 <description>SS1 active high.</description> 394 <value>0x2</value> 395 </enumeratedValue> 396 <enumeratedValue> 397 <name>SS2_high</name> 398 <description>SS2 active high.</description> 399 <value>0x4</value> 400 </enumeratedValue> 401 <enumeratedValue> 402 <name>SS3_high</name> 403 <description>SS3 active high.</description> 404 <value>0x8</value> 405 </enumeratedValue> 406 </enumeratedValues> 407 </field> 408 </fields> 409 </register> 410 <register> 411 <name>SS_TIME</name> 412 <description>Register for controlling SPI peripheral/Slave Select Timing.</description> 413 <addressOffset>0x10</addressOffset> 414 <access>read-write</access> 415 <fields> 416 <field> 417 <name>SSACT1</name> 418 <description>Slave Select Pre delay 1.</description> 419 <bitOffset>0</bitOffset> 420 <bitWidth>8</bitWidth> 421 <enumeratedValues> 422 <enumeratedValue> 423 <name>256</name> 424 <description>256 system clocks between SS active and first serial clock edge.</description> 425 <value>0</value> 426 </enumeratedValue> 427 </enumeratedValues> 428 </field> 429 <field> 430 <name>SSACT2</name> 431 <description>Slave Select Post delay 2.</description> 432 <bitOffset>8</bitOffset> 433 <bitWidth>8</bitWidth> 434 <enumeratedValues> 435 <enumeratedValue> 436 <name>256</name> 437 <description>256 system clocks between last serial clock edge and SS inactive.</description> 438 <value>0</value> 439 </enumeratedValue> 440 </enumeratedValues> 441 </field> 442 <field> 443 <name>SSINACT</name> 444 <description>Slave Select Inactive delay.</description> 445 <bitOffset>16</bitOffset> 446 <bitWidth>8</bitWidth> 447 <enumeratedValues> 448 <enumeratedValue> 449 <name>256</name> 450 <description>256 system clocks between transactions.</description> 451 <value>0</value> 452 </enumeratedValue> 453 </enumeratedValues> 454 </field> 455 </fields> 456 </register> 457 <register> 458 <name>CLK_CFG</name> 459 <description>Register for controlling SPI clock rate.</description> 460 <addressOffset>0x14</addressOffset> 461 <access>read-write</access> 462 <fields> 463 <field> 464 <name>LO</name> 465 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 466 <bitOffset>0</bitOffset> 467 <bitWidth>8</bitWidth> 468 </field> 469 <field> 470 <name>HI</name> 471 <description>High duty cycle control. In timer mode, reload[15:8].</description> 472 <bitOffset>8</bitOffset> 473 <bitWidth>8</bitWidth> 474 </field> 475 <field> 476 <name>SCALE</name> 477 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 478 <bitOffset>16</bitOffset> 479 <bitWidth>4</bitWidth> 480 <enumeratedValues> 481 <enumeratedValue> 482 <name>DIV1</name> 483 <description>Divide SPI Clock Frequency by 1.</description> 484 <value>0</value> 485 </enumeratedValue> 486 <enumeratedValue> 487 <name>DIV2</name> 488 <description>Divide SPI Clock Frequency by 2.</description> 489 <value>1</value> 490 </enumeratedValue> 491 <enumeratedValue> 492 <name>DIV4</name> 493 <description>Divide SPI Clock Frequency by 4.</description> 494 <value>2</value> 495 </enumeratedValue> 496 <enumeratedValue> 497 <name>DIV8</name> 498 <description>Divide SPI Clock Frequency by 8.</description> 499 <value>3</value> 500 </enumeratedValue> 501 <enumeratedValue> 502 <name>DIV16</name> 503 <description>Divide SPI Clock Frequency by 16.</description> 504 <value>4</value> 505 </enumeratedValue> 506 <enumeratedValue> 507 <name>DIV32</name> 508 <description>Divide SPI Clock Frequency by 32.</description> 509 <value>5</value> 510 </enumeratedValue> 511 <enumeratedValue> 512 <name>DIV64</name> 513 <description>Divide SPI Clock Frequency by 64.</description> 514 <value>6</value> 515 </enumeratedValue> 516 <enumeratedValue> 517 <name>DIV128</name> 518 <description>Divide SPI Clock Frequency by 128.</description> 519 <value>7</value> 520 </enumeratedValue> 521 <enumeratedValue> 522 <name>DIV256</name> 523 <description>Divide SPI Clock Frequency by 256.</description> 524 <value>8</value> 525 </enumeratedValue> 526 </enumeratedValues> 527 </field> 528 </fields> 529 </register> 530 <register> 531 <name>DMA</name> 532 <description>Register for controlling DMA.</description> 533 <addressOffset>0x1C</addressOffset> 534 <access>read-write</access> 535 <fields> 536 <field> 537 <name>TX_FIFO_LEVEL</name> 538 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 539 <bitOffset>0</bitOffset> 540 <bitWidth>5</bitWidth> 541 </field> 542 <field> 543 <name>TX_FIFO_EN</name> 544 <description>Transmit FIFO enabled for SPI transactions.</description> 545 <bitOffset>6</bitOffset> 546 <bitWidth>1</bitWidth> 547 <enumeratedValues> 548 <enumeratedValue> 549 <name>dis</name> 550 <description>Transmit FIFO is not enabled.</description> 551 <value>0</value> 552 </enumeratedValue> 553 <enumeratedValue> 554 <name>en</name> 555 <description>Transmit FIFO is enabled.</description> 556 <value>1</value> 557 </enumeratedValue> 558 </enumeratedValues> 559 </field> 560 <field> 561 <name>TX_FIFO_CLEAR</name> 562 <description>Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 563 <bitOffset>7</bitOffset> 564 <bitWidth>1</bitWidth> 565 <enumeratedValues> 566 <enumeratedValue> 567 <name>CLEAR</name> 568 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 569 <value>1</value> 570 </enumeratedValue> 571 </enumeratedValues> 572 </field> 573 <field> 574 <name>TX_FIFO_CNT</name> 575 <description>Count of entries in TX FIFO.</description> 576 <bitOffset>8</bitOffset> 577 <bitWidth>6</bitWidth> 578 <access>read-only</access> 579 </field> 580 <field> 581 <name>TX_DMA_EN</name> 582 <description>TX DMA Enable.</description> 583 <bitOffset>15</bitOffset> 584 <bitWidth>1</bitWidth> 585 <enumeratedValues> 586 <enumeratedValue> 587 <name>dis</name> 588 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 589 <value>0</value> 590 </enumeratedValue> 591 <enumeratedValue> 592 <name>en</name> 593 <description>TX DMA requests are enabled.</description> 594 <value>1</value> 595 </enumeratedValue> 596 </enumeratedValues> 597 </field> 598 <field> 599 <name>RX_FIFO_LEVEL</name> 600 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 601 <bitOffset>16</bitOffset> 602 <bitWidth>5</bitWidth> 603 </field> 604 <field> 605 <name>RX_FIFO_EN</name> 606 <description>Receive FIFO enabled for SPI transactions.</description> 607 <bitOffset>22</bitOffset> 608 <bitWidth>1</bitWidth> 609 <enumeratedValues> 610 <enumeratedValue> 611 <name>dis</name> 612 <description>Receive FIFO is not enabled.</description> 613 <value>0</value> 614 </enumeratedValue> 615 <enumeratedValue> 616 <name>en</name> 617 <description>Receive FIFO is enabled.</description> 618 <value>1</value> 619 </enumeratedValue> 620 </enumeratedValues> 621 </field> 622 <field> 623 <name>RX_FIFO_CLEAR</name> 624 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 625 <bitOffset>23</bitOffset> 626 <bitWidth>1</bitWidth> 627 <enumeratedValues> 628 <enumeratedValue> 629 <name>CLEAR</name> 630 <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description> 631 <value>1</value> 632 </enumeratedValue> 633 </enumeratedValues> 634 </field> 635 <field> 636 <name>RX_FIFO_CNT</name> 637 <description>Count of entries in RX FIFO.</description> 638 <bitOffset>24</bitOffset> 639 <bitWidth>6</bitWidth> 640 <access>read-only</access> 641 </field> 642 <field> 643 <name>RX_DMA_EN</name> 644 <description>RX DMA Enable.</description> 645 <bitOffset>31</bitOffset> 646 <bitWidth>1</bitWidth> 647 <enumeratedValues> 648 <enumeratedValue> 649 <name>dis</name> 650 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 651 <value>0</value> 652 </enumeratedValue> 653 <enumeratedValue> 654 <name>en</name> 655 <description>RX DMA requests are enabled.</description> 656 <value>1</value> 657 </enumeratedValue> 658 </enumeratedValues> 659 </field> 660 </fields> 661 </register> 662 <register> 663 <name>INT_FL</name> 664 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 665 <addressOffset>0x20</addressOffset> 666 <access>read-write</access> 667 <fields> 668 <field> 669 <name>TX_LEVEL</name> 670 <description>TX FIFO Threshold Crossed.</description> 671 <bitOffset>0</bitOffset> 672 <bitWidth>1</bitWidth> 673 <enumeratedValues> 674 <enumeratedValue> 675 <name>clear</name> 676 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 677 <value>1</value> 678 </enumeratedValue> 679 </enumeratedValues> 680 </field> 681 <field> 682 <name>TX_EMPTY</name> 683 <description>TX FIFO Empty.</description> 684 <bitOffset>1</bitOffset> 685 <bitWidth>1</bitWidth> 686 <enumeratedValues> 687 <enumeratedValue> 688 <name>clear</name> 689 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 690 <value>1</value> 691 </enumeratedValue> 692 </enumeratedValues> 693 </field> 694 <field> 695 <name>RX_LEVEL</name> 696 <description>RX FIFO Threshold Crossed.</description> 697 <bitOffset>2</bitOffset> 698 <bitWidth>1</bitWidth> 699 <enumeratedValues> 700 <enumeratedValue> 701 <name>clear</name> 702 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 703 <value>1</value> 704 </enumeratedValue> 705 </enumeratedValues> 706 </field> 707 <field> 708 <name>RX_FULL</name> 709 <description>RX FIFO FULL.</description> 710 <bitOffset>3</bitOffset> 711 <bitWidth>1</bitWidth> 712 <enumeratedValues> 713 <enumeratedValue> 714 <name>clear</name> 715 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 716 <value>1</value> 717 </enumeratedValue> 718 </enumeratedValues> 719 </field> 720 <field> 721 <name>SSA</name> 722 <description>Slave Select Asserted.</description> 723 <bitOffset>4</bitOffset> 724 <bitWidth>1</bitWidth> 725 <enumeratedValues> 726 <enumeratedValue> 727 <name>clear</name> 728 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 729 <value>1</value> 730 </enumeratedValue> 731 </enumeratedValues> 732 </field> 733 <field> 734 <name>SSD</name> 735 <description>Slave Select Deasserted.</description> 736 <bitOffset>5</bitOffset> 737 <bitWidth>1</bitWidth> 738 <enumeratedValues> 739 <enumeratedValue> 740 <name>clear</name> 741 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 742 <value>1</value> 743 </enumeratedValue> 744 </enumeratedValues> 745 </field> 746 <field> 747 <name>FAULT</name> 748 <description>Multi-Master Mode Fault.</description> 749 <bitOffset>8</bitOffset> 750 <bitWidth>1</bitWidth> 751 <enumeratedValues> 752 <enumeratedValue> 753 <name>clear</name> 754 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 755 <value>1</value> 756 </enumeratedValue> 757 </enumeratedValues> 758 </field> 759 <field> 760 <name>ABORT</name> 761 <description>Slave Abort Detected.</description> 762 <bitOffset>9</bitOffset> 763 <bitWidth>1</bitWidth> 764 <enumeratedValues> 765 <enumeratedValue> 766 <name>clear</name> 767 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 768 <value>1</value> 769 </enumeratedValue> 770 </enumeratedValues> 771 </field> 772 <field> 773 <name>M_DONE</name> 774 <description>Master Done, set when SPI Master has completed any transactions.</description> 775 <bitOffset>11</bitOffset> 776 <bitWidth>1</bitWidth> 777 <enumeratedValues> 778 <enumeratedValue> 779 <name>clear</name> 780 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 781 <value>1</value> 782 </enumeratedValue> 783 </enumeratedValues> 784 </field> 785 <field> 786 <name>TX_OVR</name> 787 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 788 <bitOffset>12</bitOffset> 789 <bitWidth>1</bitWidth> 790 <enumeratedValues> 791 <enumeratedValue> 792 <name>clear</name> 793 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 794 <value>1</value> 795 </enumeratedValue> 796 </enumeratedValues> 797 </field> 798 <field> 799 <name>TX_UND</name> 800 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 801 <bitOffset>13</bitOffset> 802 <bitWidth>1</bitWidth> 803 <enumeratedValues> 804 <enumeratedValue> 805 <name>clear</name> 806 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 807 <value>1</value> 808 </enumeratedValue> 809 </enumeratedValues> 810 </field> 811 <field> 812 <name>RX_OVR</name> 813 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 814 <bitOffset>14</bitOffset> 815 <bitWidth>1</bitWidth> 816 <enumeratedValues> 817 <enumeratedValue> 818 <name>clear</name> 819 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 820 <value>1</value> 821 </enumeratedValue> 822 </enumeratedValues> 823 </field> 824 <field> 825 <name>RX_UND</name> 826 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 827 <bitOffset>15</bitOffset> 828 <bitWidth>1</bitWidth> 829 <enumeratedValues> 830 <enumeratedValue> 831 <name>clear</name> 832 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 833 <value>1</value> 834 </enumeratedValue> 835 </enumeratedValues> 836 </field> 837 </fields> 838 </register> 839 <register> 840 <name>INT_EN</name> 841 <description>Register for enabling interrupts.</description> 842 <addressOffset>0x24</addressOffset> 843 <access>read-write</access> 844 <fields> 845 <field> 846 <name>TX_LEVEL</name> 847 <description>TX FIFO Threshold interrupt enable.</description> 848 <bitOffset>0</bitOffset> 849 <bitWidth>1</bitWidth> 850 <enumeratedValues> 851 <enumeratedValue> 852 <name>dis</name> 853 <description>Interrupt is disabled.</description> 854 <value>0</value> 855 </enumeratedValue> 856 <enumeratedValue> 857 <name>en</name> 858 <description>Interrupt is enabled.</description> 859 <value>1</value> 860 </enumeratedValue> 861 </enumeratedValues> 862 </field> 863 <field> 864 <name>TX_EMPTY</name> 865 <description>TX FIFO Empty interrupt enable.</description> 866 <bitOffset>1</bitOffset> 867 <bitWidth>1</bitWidth> 868 <enumeratedValues> 869 <enumeratedValue> 870 <name>dis</name> 871 <description>Interrupt is disabled.</description> 872 <value>0</value> 873 </enumeratedValue> 874 <enumeratedValue> 875 <name>en</name> 876 <description>Interrupt is enabled.</description> 877 <value>1</value> 878 </enumeratedValue> 879 </enumeratedValues> 880 </field> 881 <field> 882 <name>RX_LEVEL</name> 883 <description>RX FIFO Threshold Crossed interrupt enable.</description> 884 <bitOffset>2</bitOffset> 885 <bitWidth>1</bitWidth> 886 <enumeratedValues> 887 <enumeratedValue> 888 <name>dis</name> 889 <description>Interrupt is disabled.</description> 890 <value>0</value> 891 </enumeratedValue> 892 <enumeratedValue> 893 <name>en</name> 894 <description>Interrupt is enabled.</description> 895 <value>1</value> 896 </enumeratedValue> 897 </enumeratedValues> 898 </field> 899 <field> 900 <name>RX_FULL</name> 901 <description>RX FIFO FULL interrupt enable.</description> 902 <bitOffset>3</bitOffset> 903 <bitWidth>1</bitWidth> 904 <enumeratedValues> 905 <enumeratedValue> 906 <name>dis</name> 907 <description>Interrupt is disabled.</description> 908 <value>0</value> 909 </enumeratedValue> 910 <enumeratedValue> 911 <name>en</name> 912 <description>Interrupt is enabled.</description> 913 <value>1</value> 914 </enumeratedValue> 915 </enumeratedValues> 916 </field> 917 <field> 918 <name>SSA</name> 919 <description>Slave Select Asserted interrupt enable.</description> 920 <bitOffset>4</bitOffset> 921 <bitWidth>1</bitWidth> 922 <enumeratedValues> 923 <enumeratedValue> 924 <name>dis</name> 925 <description>Interrupt is disabled.</description> 926 <value>0</value> 927 </enumeratedValue> 928 <enumeratedValue> 929 <name>en</name> 930 <description>Interrupt is enabled.</description> 931 <value>1</value> 932 </enumeratedValue> 933 </enumeratedValues> 934 </field> 935 <field> 936 <name>SSD</name> 937 <description>Slave Select Deasserted interrupt enable.</description> 938 <bitOffset>5</bitOffset> 939 <bitWidth>1</bitWidth> 940 <enumeratedValues> 941 <enumeratedValue> 942 <name>dis</name> 943 <description>Interrupt is disabled.</description> 944 <value>0</value> 945 </enumeratedValue> 946 <enumeratedValue> 947 <name>en</name> 948 <description>Interrupt is enabled.</description> 949 <value>1</value> 950 </enumeratedValue> 951 </enumeratedValues> 952 </field> 953 <field> 954 <name>FAULT</name> 955 <description>Multi-Master Mode Fault interrupt enable.</description> 956 <bitOffset>8</bitOffset> 957 <bitWidth>1</bitWidth> 958 <enumeratedValues> 959 <enumeratedValue> 960 <name>dis</name> 961 <description>Interrupt is disabled.</description> 962 <value>0</value> 963 </enumeratedValue> 964 <enumeratedValue> 965 <name>en</name> 966 <description>Interrupt is enabled.</description> 967 <value>1</value> 968 </enumeratedValue> 969 </enumeratedValues> 970 </field> 971 <field> 972 <name>ABORT</name> 973 <description>Slave Abort Detected interrupt enable.</description> 974 <bitOffset>9</bitOffset> 975 <bitWidth>1</bitWidth> 976 <enumeratedValues> 977 <enumeratedValue> 978 <name>dis</name> 979 <description>Interrupt is disabled.</description> 980 <value>0</value> 981 </enumeratedValue> 982 <enumeratedValue> 983 <name>en</name> 984 <description>Interrupt is enabled.</description> 985 <value>1</value> 986 </enumeratedValue> 987 </enumeratedValues> 988 </field> 989 <field> 990 <name>M_DONE</name> 991 <description>Master Done interrupt enable.</description> 992 <bitOffset>11</bitOffset> 993 <bitWidth>1</bitWidth> 994 <enumeratedValues> 995 <enumeratedValue> 996 <name>dis</name> 997 <description>Interrupt is disabled.</description> 998 <value>0</value> 999 </enumeratedValue> 1000 <enumeratedValue> 1001 <name>en</name> 1002 <description>Interrupt is enabled.</description> 1003 <value>1</value> 1004 </enumeratedValue> 1005 </enumeratedValues> 1006 </field> 1007 <field> 1008 <name>TX_OVR</name> 1009 <description>Transmit FIFO Overrun interrupt enable.</description> 1010 <bitOffset>12</bitOffset> 1011 <bitWidth>1</bitWidth> 1012 <enumeratedValues> 1013 <enumeratedValue> 1014 <name>dis</name> 1015 <description>Interrupt is disabled.</description> 1016 <value>0</value> 1017 </enumeratedValue> 1018 <enumeratedValue> 1019 <name>en</name> 1020 <description>Interrupt is enabled.</description> 1021 <value>1</value> 1022 </enumeratedValue> 1023 </enumeratedValues> 1024 </field> 1025 <field> 1026 <name>TX_UND</name> 1027 <description>Transmit FIFO Underrun interrupt enable.</description> 1028 <bitOffset>13</bitOffset> 1029 <bitWidth>1</bitWidth> 1030 <enumeratedValues> 1031 <enumeratedValue> 1032 <name>dis</name> 1033 <description>Interrupt is disabled.</description> 1034 <value>0</value> 1035 </enumeratedValue> 1036 <enumeratedValue> 1037 <name>en</name> 1038 <description>Interrupt is enabled.</description> 1039 <value>1</value> 1040 </enumeratedValue> 1041 </enumeratedValues> 1042 </field> 1043 <field> 1044 <name>RX_OVR</name> 1045 <description>Receive FIFO Overrun interrupt enable.</description> 1046 <bitOffset>14</bitOffset> 1047 <bitWidth>1</bitWidth> 1048 <enumeratedValues> 1049 <enumeratedValue> 1050 <name>dis</name> 1051 <description>Interrupt is disabled.</description> 1052 <value>0</value> 1053 </enumeratedValue> 1054 <enumeratedValue> 1055 <name>en</name> 1056 <description>Interrupt is enabled.</description> 1057 <value>1</value> 1058 </enumeratedValue> 1059 </enumeratedValues> 1060 </field> 1061 <field> 1062 <name>RX_UND</name> 1063 <description>Receive FIFO Underrun interrupt enable.</description> 1064 <bitOffset>15</bitOffset> 1065 <bitWidth>1</bitWidth> 1066 <enumeratedValues> 1067 <enumeratedValue> 1068 <name>dis</name> 1069 <description>Interrupt is disabled.</description> 1070 <value>0</value> 1071 </enumeratedValue> 1072 <enumeratedValue> 1073 <name>en</name> 1074 <description>Interrupt is enabled.</description> 1075 <value>1</value> 1076 </enumeratedValue> 1077 </enumeratedValues> 1078 </field> 1079 </fields> 1080 </register> 1081 <register> 1082 <name>WAKE_FL</name> 1083 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 1084 <addressOffset>0x28</addressOffset> 1085 <access>read-write</access> 1086 <fields> 1087 <field> 1088 <name>TX_LEVEL</name> 1089 <description>Wake on TX FIFO Threshold Crossed.</description> 1090 <bitOffset>0</bitOffset> 1091 <bitWidth>1</bitWidth> 1092 <enumeratedValues> 1093 <enumeratedValue> 1094 <name>clear</name> 1095 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1096 <value>1</value> 1097 </enumeratedValue> 1098 </enumeratedValues> 1099 </field> 1100 <field> 1101 <name>TX_EMPTY</name> 1102 <description>Wake on TX FIFO Empty.</description> 1103 <bitOffset>1</bitOffset> 1104 <bitWidth>1</bitWidth> 1105 <enumeratedValues> 1106 <enumeratedValue> 1107 <name>clear</name> 1108 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1109 <value>1</value> 1110 </enumeratedValue> 1111 </enumeratedValues> 1112 </field> 1113 <field> 1114 <name>RX_LEVEL</name> 1115 <description>Wake on RX FIFO Threshold Crossed.</description> 1116 <bitOffset>2</bitOffset> 1117 <bitWidth>1</bitWidth> 1118 <enumeratedValues> 1119 <enumeratedValue> 1120 <name>clear</name> 1121 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1122 <value>1</value> 1123 </enumeratedValue> 1124 </enumeratedValues> 1125 </field> 1126 <field> 1127 <name>RX_FULL</name> 1128 <description>Wake on RX FIFO Full.</description> 1129 <bitOffset>3</bitOffset> 1130 <bitWidth>1</bitWidth> 1131 <enumeratedValues> 1132 <enumeratedValue> 1133 <name>clear</name> 1134 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1135 <value>1</value> 1136 </enumeratedValue> 1137 </enumeratedValues> 1138 </field> 1139 </fields> 1140 </register> 1141 <register> 1142 <name>WAKE_EN</name> 1143 <description>Register for wake up enable.</description> 1144 <addressOffset>0x2C</addressOffset> 1145 <access>read-write</access> 1146 <fields> 1147 <field> 1148 <name>TX_LEVEL</name> 1149 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 1150 <bitOffset>0</bitOffset> 1151 <bitWidth>1</bitWidth> 1152 <enumeratedValues> 1153 <enumeratedValue> 1154 <name>dis</name> 1155 <description>Wakeup source disabled.</description> 1156 <value>0</value> 1157 </enumeratedValue> 1158 <enumeratedValue> 1159 <name>en</name> 1160 <description>Wakeup source enabled.</description> 1161 <value>1</value> 1162 </enumeratedValue> 1163 </enumeratedValues> 1164 </field> 1165 <field> 1166 <name>TX_EMPTY</name> 1167 <description>Wake on TX FIFO Empty Enable.</description> 1168 <bitOffset>1</bitOffset> 1169 <bitWidth>1</bitWidth> 1170 <enumeratedValues> 1171 <enumeratedValue> 1172 <name>dis</name> 1173 <description>Wakeup source disabled.</description> 1174 <value>0</value> 1175 </enumeratedValue> 1176 <enumeratedValue> 1177 <name>en</name> 1178 <description>Wakeup source enabled.</description> 1179 <value>1</value> 1180 </enumeratedValue> 1181 </enumeratedValues> 1182 </field> 1183 <field> 1184 <name>RX_LEVEL</name> 1185 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 1186 <bitOffset>2</bitOffset> 1187 <bitWidth>1</bitWidth> 1188 <enumeratedValues> 1189 <enumeratedValue> 1190 <name>dis</name> 1191 <description>Wakeup source disabled.</description> 1192 <value>0</value> 1193 </enumeratedValue> 1194 <enumeratedValue> 1195 <name>en</name> 1196 <description>Wakeup source enabled.</description> 1197 <value>1</value> 1198 </enumeratedValue> 1199 </enumeratedValues> 1200 </field> 1201 <field> 1202 <name>RX_FULL</name> 1203 <description>Wake on RX FIFO Full Enable.</description> 1204 <bitOffset>3</bitOffset> 1205 <bitWidth>1</bitWidth> 1206 <enumeratedValues> 1207 <enumeratedValue> 1208 <name>dis</name> 1209 <description>Wakeup source disabled.</description> 1210 <value>0</value> 1211 </enumeratedValue> 1212 <enumeratedValue> 1213 <name>en</name> 1214 <description>Wakeup source enabled.</description> 1215 <value>1</value> 1216 </enumeratedValue> 1217 </enumeratedValues> 1218 </field> 1219 </fields> 1220 </register> 1221 <register> 1222 <name>STAT</name> 1223 <description>SPI Status register.</description> 1224 <addressOffset>0x30</addressOffset> 1225 <access>read-only</access> 1226 <fields> 1227 <field> 1228 <name>BUSY</name> 1229 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description> 1230 <bitOffset>0</bitOffset> 1231 <bitWidth>1</bitWidth> 1232 <enumeratedValues> 1233 <enumeratedValue> 1234 <name>notActive</name> 1235 <description>SPI not active.</description> 1236 <value>0</value> 1237 </enumeratedValue> 1238 <enumeratedValue> 1239 <name>active</name> 1240 <description>SPI active.</description> 1241 <value>1</value> 1242 </enumeratedValue> 1243 </enumeratedValues> 1244 </field> 1245 </fields> 1246 </register> 1247 </registers> 1248 </peripheral> 1249 <!-- SPI: Serial Peripheral Interface --> 1250</device>
