1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPI0</name> 5 <description>SPI peripheral.</description> 6 <baseAddress>0x40046000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>SPI0</name> 14 <value>16</value> 15 </interrupt> 16 <registers> 17 <register> 18 <name>DATA32</name> 19 <description>Register for reading and writing the FIFO.</description> 20 <addressOffset>0x00</addressOffset> 21 <size>32</size> 22 <access>read-write</access> 23 <fields> 24 <field> 25 <name>DATA</name> 26 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <dim>2</dim> 34 <dimIncrement>2</dimIncrement> 35 <name>DATA16[%s]</name> 36 <description>Register for reading and writing the FIFO.</description> 37 <alternateRegister>DATA32</alternateRegister> 38 <addressOffset>0x00</addressOffset> 39 <size>16</size> 40 <access>read-write</access> 41 <fields> 42 <field> 43 <name>DATA</name> 44 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 45 <bitOffset>0</bitOffset> 46 <bitWidth>16</bitWidth> 47 </field> 48 </fields> 49 </register> 50 <register> 51 <dim>4</dim> 52 <dimIncrement>1</dimIncrement> 53 <name>DATA8[%s]</name> 54 <description>Register for reading and writing the FIFO.</description> 55 <alternateRegister>DATA32</alternateRegister> 56 <addressOffset>0x00</addressOffset> 57 <size>8</size> 58 <access>read-write</access> 59 <fields> 60 <field> 61 <name>DATA</name> 62 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 63 <bitOffset>0</bitOffset> 64 <bitWidth>8</bitWidth> 65 </field> 66 </fields> 67 </register> 68 <register> 69 <name>MSTR_CNTL</name> 70 <description>Register for controlling SPI peripheral.</description> 71 <addressOffset>0x04</addressOffset> 72 <access>read-write</access> 73 <fields> 74 <field> 75 <name>SPIEN</name> 76 <description>SPI Enable.</description> 77 <bitOffset>0</bitOffset> 78 <bitWidth>1</bitWidth> 79 <enumeratedValues> 80 <enumeratedValue> 81 <name>dis</name> 82 <description>SPI is disabled.</description> 83 <value>0</value> 84 </enumeratedValue> 85 <enumeratedValue> 86 <name>en</name> 87 <description>SPI is enabled.</description> 88 <value>1</value> 89 </enumeratedValue> 90 </enumeratedValues> 91 </field> 92 <field> 93 <name>MMEN</name> 94 <description>Master Mode Enable.</description> 95 <bitOffset>1</bitOffset> 96 <bitWidth>1</bitWidth> 97 <enumeratedValues> 98 <enumeratedValue> 99 <name>dis</name> 100 <description>SPI is Slave mode.</description> 101 <value>0</value> 102 </enumeratedValue> 103 <enumeratedValue> 104 <name>en</name> 105 <description>SPI is Master mode.</description> 106 <value>1</value> 107 </enumeratedValue> 108 </enumeratedValues> 109 </field> 110 <field> 111 <name>SSIO</name> 112 <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 113 <bitOffset>4</bitOffset> 114 <bitWidth>1</bitWidth> 115 <enumeratedValues> 116 <enumeratedValue> 117 <name>output</name> 118 <description>Slave select 0 is output.</description> 119 <value>0</value> 120 </enumeratedValue> 121 <enumeratedValue> 122 <name>input</name> 123 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 124 <value>1</value> 125 </enumeratedValue> 126 </enumeratedValues> 127 </field> 128 <field> 129 <name>START</name> 130 <description>Start Transmit.</description> 131 <bitOffset>5</bitOffset> 132 <bitWidth>1</bitWidth> 133 <enumeratedValues> 134 <enumeratedValue> 135 <name>start</name> 136 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description> 137 <value>1</value> 138 </enumeratedValue> 139 </enumeratedValues> 140 </field> 141 <field> 142 <name>SSCTRL</name> 143 <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description> 144 <bitOffset>8</bitOffset> 145 <bitWidth>1</bitWidth> 146 <enumeratedValues> 147 <enumeratedValue> 148 <name>deassert</name> 149 <description>SPI De-asserts Slave Select at the end of a transaction.</description> 150 <value>0</value> 151 </enumeratedValue> 152 <enumeratedValue> 153 <name>assert</name> 154 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 155 <value>1</value> 156 </enumeratedValue> 157 </enumeratedValues> 158 </field> 159 <field> 160 <name>SS</name> 161 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 162 <bitOffset>16</bitOffset> 163 <bitWidth>3</bitWidth> 164 <enumeratedValues> 165 <enumeratedValue> 166 <name>ss0</name> 167 <description>SS0 is selected.</description> 168 <value>0x1</value> 169 </enumeratedValue> 170 <enumeratedValue> 171 <name>ss1</name> 172 <description>SS1 is selected.</description> 173 <value>0x2</value> 174 </enumeratedValue> 175 <enumeratedValue> 176 <name>ss2</name> 177 <description>SS2 is selected.</description> 178 <value>0x4</value> 179 </enumeratedValue> 180 </enumeratedValues> 181 </field> 182 </fields> 183 </register> 184 <register> 185 <name>TRNMT_SIZE</name> 186 <description>Register for controlling SPI peripheral.</description> 187 <addressOffset>0x08</addressOffset> 188 <access>read-write</access> 189 <fields> 190 <field> 191 <name>TX_NUM_CHAR</name> 192 <description>Nubmer of Characters to transmit.</description> 193 <bitOffset>0</bitOffset> 194 <bitWidth>16</bitWidth> 195 </field> 196 <field> 197 <name>RX_NUM_CHAR</name> 198 <description>Nubmer of Characters to receive.</description> 199 <bitOffset>16</bitOffset> 200 <bitWidth>16</bitWidth> 201 </field> 202 </fields> 203 </register> 204 <register> 205 <name>STATIC_CONFIG</name> 206 <description>Register for controlling SPI peripheral.</description> 207 <addressOffset>0x0C</addressOffset> 208 <access>read-write</access> 209 <fields> 210 <field> 211 <name>PHASE</name> 212 <description>Clock Phase.</description> 213 <bitOffset>0</bitOffset> 214 <bitWidth>1</bitWidth> 215 <enumeratedValues> 216 <enumeratedValue> 217 <name>rising_edge</name> 218 <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description> 219 <value>0</value> 220 </enumeratedValue> 221 <enumeratedValue> 222 <name>falling_edge</name> 223 <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description> 224 <value>1</value> 225 </enumeratedValue> 226 </enumeratedValues> 227 </field> 228 <field> 229 <name>CLKPOL</name> 230 <description>Clock Polarity.</description> 231 <bitOffset>1</bitOffset> 232 <bitWidth>1</bitWidth> 233 <enumeratedValues> 234 <enumeratedValue> 235 <name>normal</name> 236 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 237 <value>0</value> 238 </enumeratedValue> 239 <enumeratedValue> 240 <name>inverted</name> 241 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 242 <value>1</value> 243 </enumeratedValue> 244 </enumeratedValues> 245 </field> 246 <field> 247 <name>NUMBITS</name> 248 <description>Number of Bits per character.</description> 249 <bitOffset>8</bitOffset> 250 <bitWidth>4</bitWidth> 251 <enumeratedValues> 252 <enumeratedValue> 253 <name>0</name> 254 <description>16 bits per character.</description> 255 <value>0</value> 256 </enumeratedValue> 257 </enumeratedValues> 258 </field> 259 <field> 260 <name>DATAWIDTH</name> 261 <description>SPI Data width.</description> 262 <bitOffset>12</bitOffset> 263 <bitWidth>2</bitWidth> 264 <enumeratedValues> 265 <enumeratedValue> 266 <name>mono</name> 267 <description>1 data pin.</description> 268 <value>0</value> 269 </enumeratedValue> 270 <enumeratedValue> 271 <name>dual</name> 272 <description>2 data pins.</description> 273 <value>1</value> 274 </enumeratedValue> 275 <enumeratedValue> 276 <name>quad</name> 277 <description>4 data pins.</description> 278 <value>2</value> 279 </enumeratedValue> 280 </enumeratedValues> 281 </field> 282 <field> 283 <name>3WIRE</name> 284 <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description> 285 <bitOffset>15</bitOffset> 286 <bitWidth>1</bitWidth> 287 <enumeratedValues> 288 <enumeratedValue> 289 <name>dis</name> 290 <description>Use four wire mode (Mono only).</description> 291 <value>0</value> 292 </enumeratedValue> 293 <enumeratedValue> 294 <name>en</name> 295 <description>Use three wire mode.</description> 296 <value>1</value> 297 </enumeratedValue> 298 </enumeratedValues> 299 </field> 300 <field> 301 <name>SSPOL</name> 302 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 303 <bitOffset>16</bitOffset> 304 <bitWidth>8</bitWidth> 305 <enumeratedValues> 306 <enumeratedValue> 307 <name>SS0_high</name> 308 <description>SS0 active high.</description> 309 <value>0x1</value> 310 </enumeratedValue> 311 <enumeratedValue> 312 <name>SS1_high</name> 313 <description>SS1 active high.</description> 314 <value>0x2</value> 315 </enumeratedValue> 316 <enumeratedValue> 317 <name>SS2_high</name> 318 <description>SS2 active high.</description> 319 <value>0x4</value> 320 </enumeratedValue> 321 </enumeratedValues> 322 </field> 323 </fields> 324 </register> 325 <register> 326 <name>SS_TIME</name> 327 <description>Register for controlling SPI peripheral/Slave Select Timing.</description> 328 <addressOffset>0x10</addressOffset> 329 <access>read-write</access> 330 <fields> 331 <field> 332 <name>PRE</name> 333 <description>Slave Select Pre delay 1.</description> 334 <bitOffset>0</bitOffset> 335 <bitWidth>8</bitWidth> 336 <enumeratedValues> 337 <enumeratedValue> 338 <name>256</name> 339 <description>256 system clocks between SS active and first serial clock edge.</description> 340 <value>0</value> 341 </enumeratedValue> 342 </enumeratedValues> 343 </field> 344 <field> 345 <name>POST</name> 346 <description>Slave Select Post delay 2.</description> 347 <bitOffset>8</bitOffset> 348 <bitWidth>8</bitWidth> 349 <enumeratedValues> 350 <enumeratedValue> 351 <name>256</name> 352 <description>256 system clocks between last serial clock edge and SS inactive.</description> 353 <value>0</value> 354 </enumeratedValue> 355 </enumeratedValues> 356 </field> 357 <field> 358 <name>INACT</name> 359 <description>Slave Select Inactive delay.</description> 360 <bitOffset>16</bitOffset> 361 <bitWidth>8</bitWidth> 362 <enumeratedValues> 363 <enumeratedValue> 364 <name>256</name> 365 <description>256 system clocks between transactions.</description> 366 <value>0</value> 367 </enumeratedValue> 368 </enumeratedValues> 369 </field> 370 </fields> 371 </register> 372 <register> 373 <name>CLK_CONFIG</name> 374 <description>Register for controlling SPI clock rate.</description> 375 <addressOffset>0x14</addressOffset> 376 <access>read-write</access> 377 <fields> 378 <field> 379 <name>LOW</name> 380 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 381 <bitOffset>0</bitOffset> 382 <bitWidth>8</bitWidth> 383 <enumeratedValues> 384 <enumeratedValue> 385 <name>dis</name> 386 <description>Duty cycle control of serial clock generation is disabled.</description> 387 <value>0</value> 388 </enumeratedValue> 389 </enumeratedValues> 390 </field> 391 <field> 392 <name>HIGH</name> 393 <description>High duty cycle control. In timer mode, reload[15:8].</description> 394 <bitOffset>8</bitOffset> 395 <bitWidth>8</bitWidth> 396 <enumeratedValues> 397 <enumeratedValue> 398 <name>dis</name> 399 <description>Duty cycle control of serial clock generation is disabled.</description> 400 <value>0</value> 401 </enumeratedValue> 402 </enumeratedValues> 403 </field> 404 <field> 405 <name>SCALE</name> 406 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 407 <bitOffset>16</bitOffset> 408 <bitWidth>4</bitWidth> 409 </field> 410 </fields> 411 </register> 412 <register> 413 <name>DMA</name> 414 <description>Register for controlling DMA.</description> 415 <addressOffset>0x1C</addressOffset> 416 <access>read-write</access> 417 <fields> 418 <field> 419 <name>TX_FIFO_LEVEL</name> 420 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 421 <bitOffset>0</bitOffset> 422 <bitWidth>5</bitWidth> 423 </field> 424 <field> 425 <name>TX_FIFO_EN</name> 426 <description>Transmit FIFO enabled for SPI transactions.</description> 427 <bitOffset>6</bitOffset> 428 <bitWidth>1</bitWidth> 429 <enumeratedValues> 430 <enumeratedValue> 431 <name>dis</name> 432 <description>Transmit FIFO is not enabled.</description> 433 <value>0</value> 434 </enumeratedValue> 435 <enumeratedValue> 436 <name>en</name> 437 <description>Transmit FIFO is enabled.</description> 438 <value>1</value> 439 </enumeratedValue> 440 </enumeratedValues> 441 </field> 442 <field> 443 <name>TX_FIFO_CLEAR</name> 444 <description>Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 445 <bitOffset>7</bitOffset> 446 <bitWidth>1</bitWidth> 447 <enumeratedValues> 448 <enumeratedValue> 449 <name>clear</name> 450 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 451 <value>1</value> 452 </enumeratedValue> 453 </enumeratedValues> 454 </field> 455 <field> 456 <name>TX_FIFO_CNT</name> 457 <description>Count of entries in TX FIFO.</description> 458 <bitOffset>8</bitOffset> 459 <bitWidth>6</bitWidth> 460 <access>read-only</access> 461 </field> 462 <field> 463 <name>TX_DMA_EN</name> 464 <description>TX DMA Enable.</description> 465 <bitOffset>15</bitOffset> 466 <bitWidth>1</bitWidth> 467 <enumeratedValues> 468 <enumeratedValue> 469 <name>dis</name> 470 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 471 <value>0</value> 472 </enumeratedValue> 473 <enumeratedValue> 474 <name>en</name> 475 <description>TX DMA requests are enabled.</description> 476 <value>1</value> 477 </enumeratedValue> 478 </enumeratedValues> 479 </field> 480 <field> 481 <name>RX_FIFO_LEVEL</name> 482 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 483 <bitOffset>16</bitOffset> 484 <bitWidth>5</bitWidth> 485 </field> 486 <field> 487 <name>RX_FIFO_EN</name> 488 <description>Receive FIFO enabled for SPI transactions.</description> 489 <bitOffset>22</bitOffset> 490 <bitWidth>1</bitWidth> 491 <enumeratedValues> 492 <enumeratedValue> 493 <name>dis</name> 494 <description>Receive FIFO is not enabled.</description> 495 <value>0</value> 496 </enumeratedValue> 497 <enumeratedValue> 498 <name>en</name> 499 <description>Receive FIFO is enabled.</description> 500 <value>1</value> 501 </enumeratedValue> 502 </enumeratedValues> 503 </field> 504 <field> 505 <name>RX_FIFO_CLEAR</name> 506 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 507 <bitOffset>23</bitOffset> 508 <bitWidth>1</bitWidth> 509 <enumeratedValues> 510 <enumeratedValue> 511 <name>clear</name> 512 <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description> 513 <value>1</value> 514 </enumeratedValue> 515 </enumeratedValues> 516 </field> 517 <field> 518 <name>RX_FIFO_CNT</name> 519 <description>Count of entries in RX FIFO.</description> 520 <bitOffset>24</bitOffset> 521 <bitWidth>6</bitWidth> 522 <access>read-only</access> 523 </field> 524 <field> 525 <name>RX_DMA_EN</name> 526 <description>RX DMA Enable.</description> 527 <bitOffset>31</bitOffset> 528 <bitWidth>1</bitWidth> 529 <enumeratedValues> 530 <enumeratedValue> 531 <name>dis</name> 532 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 533 <value>0</value> 534 </enumeratedValue> 535 <enumeratedValue> 536 <name>en</name> 537 <description>RX DMA requests are enabled.</description> 538 <value>1</value> 539 </enumeratedValue> 540 </enumeratedValues> 541 </field> 542 </fields> 543 </register> 544 <register> 545 <name>INT_FL</name> 546 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 547 <addressOffset>0x20</addressOffset> 548 <access>read-write</access> 549 <fields> 550 <field> 551 <name>TXTHRLD</name> 552 <description>TX FIFO Threshold Crossed.</description> 553 <bitOffset>0</bitOffset> 554 <bitWidth>1</bitWidth> 555 <enumeratedValues> 556 <enumeratedValue> 557 <name>clear</name> 558 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 559 <value>1</value> 560 </enumeratedValue> 561 </enumeratedValues> 562 </field> 563 <field> 564 <name>TXEMPTY</name> 565 <description>TX FIFO Empty.</description> 566 <bitOffset>1</bitOffset> 567 <bitWidth>1</bitWidth> 568 <enumeratedValues> 569 <enumeratedValue> 570 <name>clear</name> 571 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 572 <value>1</value> 573 </enumeratedValue> 574 </enumeratedValues> 575 </field> 576 <field> 577 <name>RXTHRLD</name> 578 <description>RX FIFO Threshold Crossed.</description> 579 <bitOffset>2</bitOffset> 580 <bitWidth>1</bitWidth> 581 <enumeratedValues> 582 <enumeratedValue> 583 <name>clear</name> 584 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 585 <value>1</value> 586 </enumeratedValue> 587 </enumeratedValues> 588 </field> 589 <field> 590 <name>RXFULL</name> 591 <description>RX FIFO FULL.</description> 592 <bitOffset>3</bitOffset> 593 <bitWidth>1</bitWidth> 594 <enumeratedValues> 595 <enumeratedValue> 596 <name>clear</name> 597 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 598 <value>1</value> 599 </enumeratedValue> 600 </enumeratedValues> 601 </field> 602 <field> 603 <name>SSA</name> 604 <description>Slave Select Asserted.</description> 605 <bitOffset>4</bitOffset> 606 <bitWidth>1</bitWidth> 607 <enumeratedValues> 608 <enumeratedValue> 609 <name>clear</name> 610 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 611 <value>1</value> 612 </enumeratedValue> 613 </enumeratedValues> 614 </field> 615 <field> 616 <name>SSD</name> 617 <description>Slave Select Deasserted.</description> 618 <bitOffset>5</bitOffset> 619 <bitWidth>1</bitWidth> 620 <enumeratedValues> 621 <enumeratedValue> 622 <name>clear</name> 623 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 624 <value>1</value> 625 </enumeratedValue> 626 </enumeratedValues> 627 </field> 628 <field> 629 <name>FAULT</name> 630 <description>Multi-Master Mode Fault.</description> 631 <bitOffset>8</bitOffset> 632 <bitWidth>1</bitWidth> 633 <enumeratedValues> 634 <enumeratedValue> 635 <name>clear</name> 636 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 637 <value>1</value> 638 </enumeratedValue> 639 </enumeratedValues> 640 </field> 641 <field> 642 <name>ABORT</name> 643 <description>Slave Abort Detected.</description> 644 <bitOffset>9</bitOffset> 645 <bitWidth>1</bitWidth> 646 <enumeratedValues> 647 <enumeratedValue> 648 <name>clear</name> 649 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 650 <value>1</value> 651 </enumeratedValue> 652 </enumeratedValues> 653 </field> 654 <field> 655 <name>MSTRDONE</name> 656 <description>Master Done, set when SPI Master has completed any transactions.</description> 657 <bitOffset>11</bitOffset> 658 <bitWidth>1</bitWidth> 659 <enumeratedValues> 660 <enumeratedValue> 661 <name>clear</name> 662 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 663 <value>1</value> 664 </enumeratedValue> 665 </enumeratedValues> 666 </field> 667 <field> 668 <name>TXOVR</name> 669 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 670 <bitOffset>12</bitOffset> 671 <bitWidth>1</bitWidth> 672 <enumeratedValues> 673 <enumeratedValue> 674 <name>clear</name> 675 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 676 <value>1</value> 677 </enumeratedValue> 678 </enumeratedValues> 679 </field> 680 <field> 681 <name>TXUNDR</name> 682 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 683 <bitOffset>13</bitOffset> 684 <bitWidth>1</bitWidth> 685 <enumeratedValues> 686 <enumeratedValue> 687 <name>clear</name> 688 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 689 <value>1</value> 690 </enumeratedValue> 691 </enumeratedValues> 692 </field> 693 <field> 694 <name>RXOVR</name> 695 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 696 <bitOffset>14</bitOffset> 697 <bitWidth>1</bitWidth> 698 <enumeratedValues> 699 <enumeratedValue> 700 <name>clear</name> 701 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 702 <value>1</value> 703 </enumeratedValue> 704 </enumeratedValues> 705 </field> 706 <field> 707 <name>RXUNDR</name> 708 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 709 <bitOffset>15</bitOffset> 710 <bitWidth>1</bitWidth> 711 <enumeratedValues> 712 <enumeratedValue> 713 <name>clear</name> 714 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 715 <value>1</value> 716 </enumeratedValue> 717 </enumeratedValues> 718 </field> 719 </fields> 720 </register> 721 <register> 722 <name>INT_EN</name> 723 <description>Register for enabling interrupts.</description> 724 <addressOffset>0x24</addressOffset> 725 <access>read-write</access> 726 <fields> 727 <field> 728 <name>TXTHRLD</name> 729 <description>TX FIFO Threshold interrupt enable.</description> 730 <bitOffset>0</bitOffset> 731 <bitWidth>1</bitWidth> 732 <enumeratedValues> 733 <enumeratedValue> 734 <name>dis</name> 735 <description>Interrupt is disabled.</description> 736 <value>0</value> 737 </enumeratedValue> 738 <enumeratedValue> 739 <name>en</name> 740 <description>Interrupt is enabled.</description> 741 <value>1</value> 742 </enumeratedValue> 743 </enumeratedValues> 744 </field> 745 <field> 746 <name>TXEMPTY</name> 747 <description>TX FIFO Empty interrupt enable.</description> 748 <bitOffset>1</bitOffset> 749 <bitWidth>1</bitWidth> 750 <enumeratedValues> 751 <enumeratedValue> 752 <name>dis</name> 753 <description>Interrupt is disabled.</description> 754 <value>0</value> 755 </enumeratedValue> 756 <enumeratedValue> 757 <name>en</name> 758 <description>Interrupt is enabled.</description> 759 <value>1</value> 760 </enumeratedValue> 761 </enumeratedValues> 762 </field> 763 <field> 764 <name>RXTHRLD</name> 765 <description>RX FIFO Threshold Crossed interrupt enable.</description> 766 <bitOffset>2</bitOffset> 767 <bitWidth>1</bitWidth> 768 <enumeratedValues> 769 <enumeratedValue> 770 <name>dis</name> 771 <description>Interrupt is disabled.</description> 772 <value>0</value> 773 </enumeratedValue> 774 <enumeratedValue> 775 <name>en</name> 776 <description>Interrupt is enabled.</description> 777 <value>1</value> 778 </enumeratedValue> 779 </enumeratedValues> 780 </field> 781 <field> 782 <name>RXFULL</name> 783 <description>RX FIFO FULL interrupt enable.</description> 784 <bitOffset>3</bitOffset> 785 <bitWidth>1</bitWidth> 786 <enumeratedValues> 787 <enumeratedValue> 788 <name>dis</name> 789 <description>Interrupt is disabled.</description> 790 <value>0</value> 791 </enumeratedValue> 792 <enumeratedValue> 793 <name>en</name> 794 <description>Interrupt is enabled.</description> 795 <value>1</value> 796 </enumeratedValue> 797 </enumeratedValues> 798 </field> 799 <field> 800 <name>SSA</name> 801 <description>Slave Select Asserted interrupt enable.</description> 802 <bitOffset>4</bitOffset> 803 <bitWidth>1</bitWidth> 804 <enumeratedValues> 805 <enumeratedValue> 806 <name>dis</name> 807 <description>Interrupt is disabled.</description> 808 <value>0</value> 809 </enumeratedValue> 810 <enumeratedValue> 811 <name>en</name> 812 <description>Interrupt is enabled.</description> 813 <value>1</value> 814 </enumeratedValue> 815 </enumeratedValues> 816 </field> 817 <field> 818 <name>SSD</name> 819 <description>Slave Select Deasserted interrupt enable.</description> 820 <bitOffset>5</bitOffset> 821 <bitWidth>1</bitWidth> 822 <enumeratedValues> 823 <enumeratedValue> 824 <name>dis</name> 825 <description>Interrupt is disabled.</description> 826 <value>0</value> 827 </enumeratedValue> 828 <enumeratedValue> 829 <name>en</name> 830 <description>Interrupt is enabled.</description> 831 <value>1</value> 832 </enumeratedValue> 833 </enumeratedValues> 834 </field> 835 <field> 836 <name>FAULT</name> 837 <description>Multi-Master Mode Fault interrupt enable.</description> 838 <bitOffset>8</bitOffset> 839 <bitWidth>1</bitWidth> 840 <enumeratedValues> 841 <enumeratedValue> 842 <name>dis</name> 843 <description>Interrupt is disabled.</description> 844 <value>0</value> 845 </enumeratedValue> 846 <enumeratedValue> 847 <name>en</name> 848 <description>Interrupt is enabled.</description> 849 <value>1</value> 850 </enumeratedValue> 851 </enumeratedValues> 852 </field> 853 <field> 854 <name>ABORT</name> 855 <description>Slave Abort Detected interrupt enable.</description> 856 <bitOffset>9</bitOffset> 857 <bitWidth>1</bitWidth> 858 <enumeratedValues> 859 <enumeratedValue> 860 <name>dis</name> 861 <description>Interrupt is disabled.</description> 862 <value>0</value> 863 </enumeratedValue> 864 <enumeratedValue> 865 <name>en</name> 866 <description>Interrupt is enabled.</description> 867 <value>1</value> 868 </enumeratedValue> 869 </enumeratedValues> 870 </field> 871 <field> 872 <name>MSTRDONE</name> 873 <description>Master Done interrupt enable.</description> 874 <bitOffset>11</bitOffset> 875 <bitWidth>1</bitWidth> 876 <enumeratedValues> 877 <enumeratedValue> 878 <name>dis</name> 879 <description>Interrupt is disabled.</description> 880 <value>0</value> 881 </enumeratedValue> 882 <enumeratedValue> 883 <name>en</name> 884 <description>Interrupt is enabled.</description> 885 <value>1</value> 886 </enumeratedValue> 887 </enumeratedValues> 888 </field> 889 <field> 890 <name>TXOVR</name> 891 <description>Transmit FIFO Overrun interrupt enable.</description> 892 <bitOffset>12</bitOffset> 893 <bitWidth>1</bitWidth> 894 <enumeratedValues> 895 <enumeratedValue> 896 <name>dis</name> 897 <description>Interrupt is disabled.</description> 898 <value>0</value> 899 </enumeratedValue> 900 <enumeratedValue> 901 <name>en</name> 902 <description>Interrupt is enabled.</description> 903 <value>1</value> 904 </enumeratedValue> 905 </enumeratedValues> 906 </field> 907 <field> 908 <name>TXUNDR</name> 909 <description>Transmit FIFO Underrun interrupt enable.</description> 910 <bitOffset>13</bitOffset> 911 <bitWidth>1</bitWidth> 912 <enumeratedValues> 913 <enumeratedValue> 914 <name>dis</name> 915 <description>Interrupt is disabled.</description> 916 <value>0</value> 917 </enumeratedValue> 918 <enumeratedValue> 919 <name>en</name> 920 <description>Interrupt is enabled.</description> 921 <value>1</value> 922 </enumeratedValue> 923 </enumeratedValues> 924 </field> 925 <field> 926 <name>RXOVR</name> 927 <description>Receive FIFO Overrun interrupt enable.</description> 928 <bitOffset>14</bitOffset> 929 <bitWidth>1</bitWidth> 930 <enumeratedValues> 931 <enumeratedValue> 932 <name>dis</name> 933 <description>Interrupt is disabled.</description> 934 <value>0</value> 935 </enumeratedValue> 936 <enumeratedValue> 937 <name>en</name> 938 <description>Interrupt is enabled.</description> 939 <value>1</value> 940 </enumeratedValue> 941 </enumeratedValues> 942 </field> 943 <field> 944 <name>RXUNDR</name> 945 <description>Receive FIFO Underrun interrupt enable.</description> 946 <bitOffset>15</bitOffset> 947 <bitWidth>1</bitWidth> 948 <enumeratedValues> 949 <enumeratedValue> 950 <name>dis</name> 951 <description>Interrupt is disabled.</description> 952 <value>0</value> 953 </enumeratedValue> 954 <enumeratedValue> 955 <name>en</name> 956 <description>Interrupt is enabled.</description> 957 <value>1</value> 958 </enumeratedValue> 959 </enumeratedValues> 960 </field> 961 </fields> 962 </register> 963 <register> 964 <name>WAKE_FL</name> 965 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 966 <addressOffset>0x28</addressOffset> 967 <access>read-write</access> 968 <fields> 969 <field> 970 <name>TXTHRLD</name> 971 <description>Wake on TX FIFO Threshold Crossed.</description> 972 <bitOffset>0</bitOffset> 973 <bitWidth>1</bitWidth> 974 <enumeratedValues> 975 <enumeratedValue> 976 <name>clear</name> 977 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 978 <value>1</value> 979 </enumeratedValue> 980 </enumeratedValues> 981 </field> 982 <field> 983 <name>TXEMPTY</name> 984 <description>Wake on TX FIFO Empty.</description> 985 <bitOffset>1</bitOffset> 986 <bitWidth>1</bitWidth> 987 <enumeratedValues> 988 <enumeratedValue> 989 <name>clear</name> 990 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 991 <value>1</value> 992 </enumeratedValue> 993 </enumeratedValues> 994 </field> 995 <field> 996 <name>RXTHRLD</name> 997 <description>Wake on RX FIFO Threshold Crossed.</description> 998 <bitOffset>2</bitOffset> 999 <bitWidth>1</bitWidth> 1000 <enumeratedValues> 1001 <enumeratedValue> 1002 <name>clear</name> 1003 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1004 <value>1</value> 1005 </enumeratedValue> 1006 </enumeratedValues> 1007 </field> 1008 <field> 1009 <name>RXFULL</name> 1010 <description>Wake on RX FIFO Full.</description> 1011 <bitOffset>3</bitOffset> 1012 <bitWidth>1</bitWidth> 1013 <enumeratedValues> 1014 <enumeratedValue> 1015 <name>clear</name> 1016 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1017 <value>1</value> 1018 </enumeratedValue> 1019 </enumeratedValues> 1020 </field> 1021 </fields> 1022 </register> 1023 <register> 1024 <name>WAKE_EN</name> 1025 <description>Register for wake up enable.</description> 1026 <addressOffset>0x2C</addressOffset> 1027 <access>read-write</access> 1028 <fields> 1029 <field> 1030 <name>TXTHRLD</name> 1031 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 1032 <bitOffset>0</bitOffset> 1033 <bitWidth>1</bitWidth> 1034 <enumeratedValues> 1035 <enumeratedValue> 1036 <name>dis</name> 1037 <description>Wakeup source disabled.</description> 1038 <value>0</value> 1039 </enumeratedValue> 1040 <enumeratedValue> 1041 <name>en</name> 1042 <description>Wakeup source enabled.</description> 1043 <value>1</value> 1044 </enumeratedValue> 1045 </enumeratedValues> 1046 </field> 1047 <field> 1048 <name>TXEMPTY</name> 1049 <description>Wake on TX FIFO Empty Enable.</description> 1050 <bitOffset>1</bitOffset> 1051 <bitWidth>1</bitWidth> 1052 <enumeratedValues> 1053 <enumeratedValue> 1054 <name>dis</name> 1055 <description>Wakeup source disabled.</description> 1056 <value>0</value> 1057 </enumeratedValue> 1058 <enumeratedValue> 1059 <name>en</name> 1060 <description>Wakeup source enabled.</description> 1061 <value>1</value> 1062 </enumeratedValue> 1063 </enumeratedValues> 1064 </field> 1065 <field> 1066 <name>RXTHRLD</name> 1067 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 1068 <bitOffset>2</bitOffset> 1069 <bitWidth>1</bitWidth> 1070 <enumeratedValues> 1071 <enumeratedValue> 1072 <name>dis</name> 1073 <description>Wakeup source disabled.</description> 1074 <value>0</value> 1075 </enumeratedValue> 1076 <enumeratedValue> 1077 <name>en</name> 1078 <description>Wakeup source enabled.</description> 1079 <value>1</value> 1080 </enumeratedValue> 1081 </enumeratedValues> 1082 </field> 1083 <field> 1084 <name>RXFULL</name> 1085 <description>Wake on RX FIFO Full Enable.</description> 1086 <bitOffset>3</bitOffset> 1087 <bitWidth>1</bitWidth> 1088 <enumeratedValues> 1089 <enumeratedValue> 1090 <name>dis</name> 1091 <description>Wakeup source disabled.</description> 1092 <value>0</value> 1093 </enumeratedValue> 1094 <enumeratedValue> 1095 <name>en</name> 1096 <description>Wakeup source enabled.</description> 1097 <value>1</value> 1098 </enumeratedValue> 1099 </enumeratedValues> 1100 </field> 1101 </fields> 1102 </register> 1103 <register> 1104 <name>STAT</name> 1105 <description>SPI Status register.</description> 1106 <addressOffset>0x30</addressOffset> 1107 <access>read-only</access> 1108 <fields> 1109 <field> 1110 <name>BUSY</name> 1111 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description> 1112 <bitOffset>0</bitOffset> 1113 <bitWidth>1</bitWidth> 1114 <enumeratedValues> 1115 <enumeratedValue> 1116 <name>inactive</name> 1117 <description>SPI not active.</description> 1118 <value>0</value> 1119 </enumeratedValue> 1120 <enumeratedValue> 1121 <name>active</name> 1122 <description>SPI active.</description> 1123 <value>1</value> 1124 </enumeratedValue> 1125 </enumeratedValues> 1126 </field> 1127 </fields> 1128 </register> 1129 </registers> 1130 </peripheral> 1131 <!-- SPI: Serial Peripheral Interface --> 1132</device>
