1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPI0</name> 5 <description>SPI peripheral.</description> 6 <baseAddress>0x40046000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>SPI0</name> 14 <value>16</value> 15 </interrupt> 16 <registers> 17 <register> 18 <name>FIFO32</name> 19 <description>Register for reading and writing the FIFO.</description> 20 <addressOffset>0x00</addressOffset> 21 <size>32</size> 22 <access>read-write</access> 23 <fields> 24 <field> 25 <name>DATA</name> 26 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <dim>2</dim> 34 <dimIncrement>2</dimIncrement> 35 <name>FIFO16[%s]</name> 36 <description>Register for reading and writing the FIFO.</description> 37 <addressOffset>0x00</addressOffset> 38 <size>16</size> 39 <access>read-write</access> 40 <fields> 41 <field> 42 <name>DATA</name> 43 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 44 <bitOffset>0</bitOffset> 45 <bitWidth>16</bitWidth> 46 </field> 47 </fields> 48 </register> 49 <register> 50 <dim>4</dim> 51 <dimIncrement>1</dimIncrement> 52 <name>FIFO8[%s]</name> 53 <description>Register for reading and writing the FIFO.</description> 54 <addressOffset>0x00</addressOffset> 55 <size>8</size> 56 <access>read-write</access> 57 <fields> 58 <field> 59 <name>DATA</name> 60 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 61 <bitOffset>0</bitOffset> 62 <bitWidth>8</bitWidth> 63 </field> 64 </fields> 65 </register> 66 <register> 67 <name>CTRL0</name> 68 <description>Register for controlling SPI peripheral.</description> 69 <addressOffset>0x04</addressOffset> 70 <access>read-write</access> 71 <fields> 72 <field> 73 <name>EN</name> 74 <description>SPI Enable.</description> 75 <bitOffset>0</bitOffset> 76 <bitWidth>1</bitWidth> 77 <enumeratedValues> 78 <enumeratedValue> 79 <name>dis</name> 80 <description>SPI is disabled.</description> 81 <value>0</value> 82 </enumeratedValue> 83 <enumeratedValue> 84 <name>en</name> 85 <description>SPI is enabled.</description> 86 <value>1</value> 87 </enumeratedValue> 88 </enumeratedValues> 89 </field> 90 <field> 91 <name>MST_MODE</name> 92 <description>Master Mode Enable.</description> 93 <bitOffset>1</bitOffset> 94 <bitWidth>1</bitWidth> 95 <enumeratedValues> 96 <enumeratedValue> 97 <name>dis</name> 98 <description>SPI is Slave mode.</description> 99 <value>0</value> 100 </enumeratedValue> 101 <enumeratedValue> 102 <name>en</name> 103 <description>SPI is Master mode.</description> 104 <value>1</value> 105 </enumeratedValue> 106 </enumeratedValues> 107 </field> 108 <field> 109 <name>SS_IO</name> 110 <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 111 <bitOffset>4</bitOffset> 112 <bitWidth>1</bitWidth> 113 <enumeratedValues> 114 <enumeratedValue> 115 <name>output</name> 116 <description>Slave select 0 is output.</description> 117 <value>0</value> 118 </enumeratedValue> 119 <enumeratedValue> 120 <name>input</name> 121 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 122 <value>1</value> 123 </enumeratedValue> 124 </enumeratedValues> 125 </field> 126 <field> 127 <name>START</name> 128 <description>Start Transmit.</description> 129 <bitOffset>5</bitOffset> 130 <bitWidth>1</bitWidth> 131 <enumeratedValues> 132 <enumeratedValue> 133 <name>start</name> 134 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description> 135 <value>1</value> 136 </enumeratedValue> 137 </enumeratedValues> 138 </field> 139 <field> 140 <name>SS_CTRL</name> 141 <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description> 142 <bitOffset>8</bitOffset> 143 <bitWidth>1</bitWidth> 144 <enumeratedValues> 145 <enumeratedValue> 146 <name>DEASSERT</name> 147 <description>SPI De-asserts Slave Select at the end of a transaction.</description> 148 <value>0</value> 149 </enumeratedValue> 150 <enumeratedValue> 151 <name>ASSERT</name> 152 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 153 <value>1</value> 154 </enumeratedValue> 155 </enumeratedValues> 156 </field> 157 <field> 158 <name>SS_ACTIVE</name> 159 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 160 <bitOffset>16</bitOffset> 161 <bitWidth>4</bitWidth> 162 <enumeratedValues> 163 <enumeratedValue> 164 <name>SS0</name> 165 <description>SS0 is selected.</description> 166 <value>0x1</value> 167 </enumeratedValue> 168 <enumeratedValue> 169 <name>SS1</name> 170 <description>SS1 is selected.</description> 171 <value>0x2</value> 172 </enumeratedValue> 173 <enumeratedValue> 174 <name>SS2</name> 175 <description>SS2 is selected.</description> 176 <value>0x4</value> 177 </enumeratedValue> 178 <enumeratedValue> 179 <name>SS3</name> 180 <description>SS3 is selected.</description> 181 <value>0x8</value> 182 </enumeratedValue> 183 </enumeratedValues> 184 </field> 185 </fields> 186 </register> 187 <register> 188 <name>CTRL1</name> 189 <description>Register for controlling SPI peripheral.</description> 190 <addressOffset>0x08</addressOffset> 191 <access>read-write</access> 192 <fields> 193 <field> 194 <name>TX_NUM_CHAR</name> 195 <description>Nubmer of Characters to transmit.</description> 196 <bitOffset>0</bitOffset> 197 <bitWidth>16</bitWidth> 198 </field> 199 <field> 200 <name>RX_NUM_CHAR</name> 201 <description>Nubmer of Characters to receive.</description> 202 <bitOffset>16</bitOffset> 203 <bitWidth>16</bitWidth> 204 </field> 205 </fields> 206 </register> 207 <register> 208 <name>CTRL2</name> 209 <description>Register for controlling SPI peripheral.</description> 210 <addressOffset>0x0C</addressOffset> 211 <access>read-write</access> 212 <fields> 213 <field> 214 <name>CLKPHA</name> 215 <description>Clock Phase.</description> 216 <bitOffset>0</bitOffset> 217 <bitWidth>1</bitWidth> 218 <enumeratedValues> 219 <enumeratedValue> 220 <name>Rising_Edge</name> 221 <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description> 222 <value>0</value> 223 </enumeratedValue> 224 <enumeratedValue> 225 <name>Falling_Edge</name> 226 <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description> 227 <value>1</value> 228 </enumeratedValue> 229 </enumeratedValues> 230 </field> 231 <field> 232 <name>CLKPOL</name> 233 <description>Clock Polarity.</description> 234 <bitOffset>1</bitOffset> 235 <bitWidth>1</bitWidth> 236 <enumeratedValues> 237 <enumeratedValue> 238 <name>Normal</name> 239 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 240 <value>0</value> 241 </enumeratedValue> 242 <enumeratedValue> 243 <name>Inverted</name> 244 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 245 <value>1</value> 246 </enumeratedValue> 247 </enumeratedValues> 248 </field> 249 <field> 250 <name>SCLK_FB_INV</name> 251 <description>SCLK_FB_INV.</description> 252 <bitOffset>4</bitOffset> 253 <bitWidth>1</bitWidth> 254 </field> 255 <field> 256 <name>NUMBITS</name> 257 <description>Number of Bits per character.</description> 258 <bitOffset>8</bitOffset> 259 <bitWidth>4</bitWidth> 260 <enumeratedValues> 261 <enumeratedValue> 262 <name>0</name> 263 <description>16 bits per character.</description> 264 <value>0</value> 265 </enumeratedValue> 266 </enumeratedValues> 267 </field> 268 <field> 269 <name>DATA_WIDTH</name> 270 <description>SPI Data width.</description> 271 <bitOffset>12</bitOffset> 272 <bitWidth>2</bitWidth> 273 <enumeratedValues> 274 <enumeratedValue> 275 <name>Mono</name> 276 <description>1 data pin.</description> 277 <value>0</value> 278 </enumeratedValue> 279 <enumeratedValue> 280 <name>Dual</name> 281 <description>2 data pins.</description> 282 <value>1</value> 283 </enumeratedValue> 284 <enumeratedValue> 285 <name>Quad</name> 286 <description>4 data pins.</description> 287 <value>2</value> 288 </enumeratedValue> 289 </enumeratedValues> 290 </field> 291 <field> 292 <name>THREE_WIRE</name> 293 <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description> 294 <bitOffset>15</bitOffset> 295 <bitWidth>1</bitWidth> 296 <enumeratedValues> 297 <enumeratedValue> 298 <name>dis</name> 299 <description>Use four wire mode (Mono only).</description> 300 <value>0</value> 301 </enumeratedValue> 302 <enumeratedValue> 303 <name>en</name> 304 <description>Use three wire mode.</description> 305 <value>1</value> 306 </enumeratedValue> 307 </enumeratedValues> 308 </field> 309 <field> 310 <name>SS_POL</name> 311 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 312 <bitOffset>16</bitOffset> 313 <bitWidth>8</bitWidth> 314 <enumeratedValues> 315 <enumeratedValue> 316 <name>SS0_high</name> 317 <description>SS0 active high.</description> 318 <value>0x1</value> 319 </enumeratedValue> 320 <enumeratedValue> 321 <name>SS1_high</name> 322 <description>SS1 active high.</description> 323 <value>0x2</value> 324 </enumeratedValue> 325 <enumeratedValue> 326 <name>SS2_high</name> 327 <description>SS2 active high.</description> 328 <value>0x4</value> 329 </enumeratedValue> 330 <enumeratedValue> 331 <name>SS3_high</name> 332 <description>SS3 active high.</description> 333 <value>0x8</value> 334 </enumeratedValue> 335 </enumeratedValues> 336 </field> 337 </fields> 338 </register> 339 <register> 340 <name>SSTIME</name> 341 <description>Register for controlling SPI peripheral/Slave Select Timing.</description> 342 <addressOffset>0x10</addressOffset> 343 <access>read-write</access> 344 <fields> 345 <field> 346 <name>PRE</name> 347 <description>Slave Select Pre delay 1.</description> 348 <bitOffset>0</bitOffset> 349 <bitWidth>8</bitWidth> 350 <enumeratedValues> 351 <enumeratedValue> 352 <name>256</name> 353 <description>256 system clocks between SS active and first serial clock edge.</description> 354 <value>0</value> 355 </enumeratedValue> 356 </enumeratedValues> 357 </field> 358 <field> 359 <name>POST</name> 360 <description>Slave Select Post delay 2.</description> 361 <bitOffset>8</bitOffset> 362 <bitWidth>8</bitWidth> 363 <enumeratedValues> 364 <enumeratedValue> 365 <name>256</name> 366 <description>256 system clocks between last serial clock edge and SS inactive.</description> 367 <value>0</value> 368 </enumeratedValue> 369 </enumeratedValues> 370 </field> 371 <field> 372 <name>INACT</name> 373 <description>Slave Select Inactive delay.</description> 374 <bitOffset>16</bitOffset> 375 <bitWidth>8</bitWidth> 376 <enumeratedValues> 377 <enumeratedValue> 378 <name>256</name> 379 <description>256 system clocks between transactions.</description> 380 <value>0</value> 381 </enumeratedValue> 382 </enumeratedValues> 383 </field> 384 </fields> 385 </register> 386 <register> 387 <name>CLKCTRL</name> 388 <description>Register for controlling SPI clock rate.</description> 389 <addressOffset>0x14</addressOffset> 390 <access>read-write</access> 391 <fields> 392 <field> 393 <name>LO</name> 394 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 395 <bitOffset>0</bitOffset> 396 <bitWidth>8</bitWidth> 397 <enumeratedValues> 398 <enumeratedValue> 399 <name>Dis</name> 400 <description>Duty cycle control of serial clock generation is disabled.</description> 401 <value>0</value> 402 </enumeratedValue> 403 </enumeratedValues> 404 </field> 405 <field> 406 <name>HI</name> 407 <description>High duty cycle control. In timer mode, reload[15:8].</description> 408 <bitOffset>8</bitOffset> 409 <bitWidth>8</bitWidth> 410 <enumeratedValues> 411 <enumeratedValue> 412 <name>Dis</name> 413 <description>Duty cycle control of serial clock generation is disabled.</description> 414 <value>0</value> 415 </enumeratedValue> 416 </enumeratedValues> 417 </field> 418 <field> 419 <name>CLKDIV</name> 420 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 421 <bitOffset>16</bitOffset> 422 <bitWidth>4</bitWidth> 423 </field> 424 <field> 425 <name>AFP_FCD</name> 426 <description>Automatic frequency prescalar.</description> 427 <bitOffset>24</bitOffset> 428 <bitWidth>3</bitWidth> 429 </field> 430 </fields> 431 </register> 432 <register> 433 <name>DMA</name> 434 <description>Register for controlling DMA.</description> 435 <addressOffset>0x1C</addressOffset> 436 <access>read-write</access> 437 <fields> 438 <field> 439 <name>TX_THD_VAL</name> 440 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 441 <bitOffset>0</bitOffset> 442 <bitWidth>5</bitWidth> 443 </field> 444 <field> 445 <name>TX_FIFO_EN</name> 446 <description>Transmit FIFO enabled for SPI transactions.</description> 447 <bitOffset>6</bitOffset> 448 <bitWidth>1</bitWidth> 449 <enumeratedValues> 450 <enumeratedValue> 451 <name>dis</name> 452 <description>Transmit FIFO is not enabled.</description> 453 <value>0</value> 454 </enumeratedValue> 455 <enumeratedValue> 456 <name>en</name> 457 <description>Transmit FIFO is enabled.</description> 458 <value>1</value> 459 </enumeratedValue> 460 </enumeratedValues> 461 </field> 462 <field> 463 <name>TX_FLUSH</name> 464 <description>Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 465 <bitOffset>7</bitOffset> 466 <bitWidth>1</bitWidth> 467 <enumeratedValues> 468 <enumeratedValue> 469 <name>CLEAR</name> 470 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 471 <value>1</value> 472 </enumeratedValue> 473 </enumeratedValues> 474 </field> 475 <field> 476 <name>TX_LVL</name> 477 <description>Count of entries in TX FIFO.</description> 478 <bitOffset>8</bitOffset> 479 <bitWidth>6</bitWidth> 480 <access>read-only</access> 481 </field> 482 <field> 483 <name>DMA_TX_EN</name> 484 <description>TX DMA Enable.</description> 485 <bitOffset>15</bitOffset> 486 <bitWidth>1</bitWidth> 487 <enumeratedValues> 488 <enumeratedValue> 489 <name>DIS</name> 490 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 491 <value>0</value> 492 </enumeratedValue> 493 <enumeratedValue> 494 <name>en</name> 495 <description>TX DMA requests are enabled.</description> 496 <value>1</value> 497 </enumeratedValue> 498 </enumeratedValues> 499 </field> 500 <field> 501 <name>RX_THD_VAL</name> 502 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 503 <bitOffset>16</bitOffset> 504 <bitWidth>5</bitWidth> 505 </field> 506 <field> 507 <name>RX_FIFO_EN</name> 508 <description>Receive FIFO enabled for SPI transactions.</description> 509 <bitOffset>22</bitOffset> 510 <bitWidth>1</bitWidth> 511 <enumeratedValues> 512 <enumeratedValue> 513 <name>DIS</name> 514 <description>Receive FIFO is not enabled.</description> 515 <value>0</value> 516 </enumeratedValue> 517 <enumeratedValue> 518 <name>en</name> 519 <description>Receive FIFO is enabled.</description> 520 <value>1</value> 521 </enumeratedValue> 522 </enumeratedValues> 523 </field> 524 <field> 525 <name>RX_FLUSH</name> 526 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 527 <bitOffset>23</bitOffset> 528 <bitWidth>1</bitWidth> 529 <enumeratedValues> 530 <enumeratedValue> 531 <name>CLEAR</name> 532 <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description> 533 <value>1</value> 534 </enumeratedValue> 535 </enumeratedValues> 536 </field> 537 <field> 538 <name>RX_LVL</name> 539 <description>Count of entries in RX FIFO.</description> 540 <bitOffset>24</bitOffset> 541 <bitWidth>6</bitWidth> 542 <access>read-only</access> 543 </field> 544 <field> 545 <name>DMA_RX_EN</name> 546 <description>RX DMA Enable.</description> 547 <bitOffset>31</bitOffset> 548 <bitWidth>1</bitWidth> 549 <enumeratedValues> 550 <enumeratedValue> 551 <name>dis</name> 552 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 553 <value>0</value> 554 </enumeratedValue> 555 <enumeratedValue> 556 <name>en</name> 557 <description>RX DMA requests are enabled.</description> 558 <value>1</value> 559 </enumeratedValue> 560 </enumeratedValues> 561 </field> 562 </fields> 563 </register> 564 <register> 565 <name>INTFL</name> 566 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 567 <addressOffset>0x20</addressOffset> 568 <access>read-write</access> 569 <fields> 570 <field> 571 <name>TX_THD</name> 572 <description>TX FIFO Threshold Crossed.</description> 573 <bitOffset>0</bitOffset> 574 <bitWidth>1</bitWidth> 575 <enumeratedValues> 576 <enumeratedValue> 577 <name>clear</name> 578 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 579 <value>1</value> 580 </enumeratedValue> 581 </enumeratedValues> 582 </field> 583 <field> 584 <name>TX_EM</name> 585 <description>TX FIFO Empty.</description> 586 <bitOffset>1</bitOffset> 587 <bitWidth>1</bitWidth> 588 <enumeratedValues> 589 <enumeratedValue> 590 <name>clear</name> 591 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 592 <value>1</value> 593 </enumeratedValue> 594 </enumeratedValues> 595 </field> 596 <field> 597 <name>RX_THD</name> 598 <description>RX FIFO Threshold Crossed.</description> 599 <bitOffset>2</bitOffset> 600 <bitWidth>1</bitWidth> 601 <enumeratedValues> 602 <enumeratedValue> 603 <name>clear</name> 604 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 605 <value>1</value> 606 </enumeratedValue> 607 </enumeratedValues> 608 </field> 609 <field> 610 <name>RX_FULL</name> 611 <description>RX FIFO FULL.</description> 612 <bitOffset>3</bitOffset> 613 <bitWidth>1</bitWidth> 614 <enumeratedValues> 615 <enumeratedValue> 616 <name>clear</name> 617 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 618 <value>1</value> 619 </enumeratedValue> 620 </enumeratedValues> 621 </field> 622 <field> 623 <name>SSA</name> 624 <description>Slave Select Asserted.</description> 625 <bitOffset>4</bitOffset> 626 <bitWidth>1</bitWidth> 627 <enumeratedValues> 628 <enumeratedValue> 629 <name>clear</name> 630 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 631 <value>1</value> 632 </enumeratedValue> 633 </enumeratedValues> 634 </field> 635 <field> 636 <name>SSD</name> 637 <description>Slave Select Deasserted.</description> 638 <bitOffset>5</bitOffset> 639 <bitWidth>1</bitWidth> 640 <enumeratedValues> 641 <enumeratedValue> 642 <name>clear</name> 643 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 644 <value>1</value> 645 </enumeratedValue> 646 </enumeratedValues> 647 </field> 648 <field> 649 <name>FAULT</name> 650 <description>Multi-Master Mode Fault.</description> 651 <bitOffset>8</bitOffset> 652 <bitWidth>1</bitWidth> 653 <enumeratedValues> 654 <enumeratedValue> 655 <name>clear</name> 656 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 657 <value>1</value> 658 </enumeratedValue> 659 </enumeratedValues> 660 </field> 661 <field> 662 <name>ABORT</name> 663 <description>Slave Abort Detected.</description> 664 <bitOffset>9</bitOffset> 665 <bitWidth>1</bitWidth> 666 <enumeratedValues> 667 <enumeratedValue> 668 <name>clear</name> 669 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 670 <value>1</value> 671 </enumeratedValue> 672 </enumeratedValues> 673 </field> 674 <field> 675 <name>MST_DONE</name> 676 <description>Master Done, set when SPI Master has completed any transactions.</description> 677 <bitOffset>11</bitOffset> 678 <bitWidth>1</bitWidth> 679 <enumeratedValues> 680 <enumeratedValue> 681 <name>clear</name> 682 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 683 <value>1</value> 684 </enumeratedValue> 685 </enumeratedValues> 686 </field> 687 <field> 688 <name>TX_OV</name> 689 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 690 <bitOffset>12</bitOffset> 691 <bitWidth>1</bitWidth> 692 <enumeratedValues> 693 <enumeratedValue> 694 <name>clear</name> 695 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 696 <value>1</value> 697 </enumeratedValue> 698 </enumeratedValues> 699 </field> 700 <field> 701 <name>TX_UN</name> 702 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 703 <bitOffset>13</bitOffset> 704 <bitWidth>1</bitWidth> 705 <enumeratedValues> 706 <enumeratedValue> 707 <name>clear</name> 708 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 709 <value>1</value> 710 </enumeratedValue> 711 </enumeratedValues> 712 </field> 713 <field> 714 <name>RX_OV</name> 715 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 716 <bitOffset>14</bitOffset> 717 <bitWidth>1</bitWidth> 718 <enumeratedValues> 719 <enumeratedValue> 720 <name>clear</name> 721 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 722 <value>1</value> 723 </enumeratedValue> 724 </enumeratedValues> 725 </field> 726 <field> 727 <name>RX_UN</name> 728 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 729 <bitOffset>15</bitOffset> 730 <bitWidth>1</bitWidth> 731 <enumeratedValues> 732 <enumeratedValue> 733 <name>clear</name> 734 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 735 <value>1</value> 736 </enumeratedValue> 737 </enumeratedValues> 738 </field> 739 </fields> 740 </register> 741 <register> 742 <name>INTEN</name> 743 <description>Register for enabling interrupts.</description> 744 <addressOffset>0x24</addressOffset> 745 <access>read-write</access> 746 <fields> 747 <field> 748 <name>TX_THD</name> 749 <description>TX FIFO Threshold interrupt enable.</description> 750 <bitOffset>0</bitOffset> 751 <bitWidth>1</bitWidth> 752 <enumeratedValues> 753 <enumeratedValue> 754 <name>dis</name> 755 <description>Interrupt is disabled.</description> 756 <value>0</value> 757 </enumeratedValue> 758 <enumeratedValue> 759 <name>en</name> 760 <description>Interrupt is enabled.</description> 761 <value>1</value> 762 </enumeratedValue> 763 </enumeratedValues> 764 </field> 765 <field> 766 <name>TX_EM</name> 767 <description>TX FIFO Empty interrupt enable.</description> 768 <bitOffset>1</bitOffset> 769 <bitWidth>1</bitWidth> 770 <enumeratedValues> 771 <enumeratedValue> 772 <name>dis</name> 773 <description>Interrupt is disabled.</description> 774 <value>0</value> 775 </enumeratedValue> 776 <enumeratedValue> 777 <name>en</name> 778 <description>Interrupt is enabled.</description> 779 <value>1</value> 780 </enumeratedValue> 781 </enumeratedValues> 782 </field> 783 <field> 784 <name>RX_THD</name> 785 <description>RX FIFO Threshold Crossed interrupt enable.</description> 786 <bitOffset>2</bitOffset> 787 <bitWidth>1</bitWidth> 788 <enumeratedValues> 789 <enumeratedValue> 790 <name>dis</name> 791 <description>Interrupt is disabled.</description> 792 <value>0</value> 793 </enumeratedValue> 794 <enumeratedValue> 795 <name>en</name> 796 <description>Interrupt is enabled.</description> 797 <value>1</value> 798 </enumeratedValue> 799 </enumeratedValues> 800 </field> 801 <field> 802 <name>RX_FULL</name> 803 <description>RX FIFO FULL interrupt enable.</description> 804 <bitOffset>3</bitOffset> 805 <bitWidth>1</bitWidth> 806 <enumeratedValues> 807 <enumeratedValue> 808 <name>dis</name> 809 <description>Interrupt is disabled.</description> 810 <value>0</value> 811 </enumeratedValue> 812 <enumeratedValue> 813 <name>en</name> 814 <description>Interrupt is enabled.</description> 815 <value>1</value> 816 </enumeratedValue> 817 </enumeratedValues> 818 </field> 819 <field> 820 <name>SSA</name> 821 <description>Slave Select Asserted interrupt enable.</description> 822 <bitOffset>4</bitOffset> 823 <bitWidth>1</bitWidth> 824 <enumeratedValues> 825 <enumeratedValue> 826 <name>dis</name> 827 <description>Interrupt is disabled.</description> 828 <value>0</value> 829 </enumeratedValue> 830 <enumeratedValue> 831 <name>en</name> 832 <description>Interrupt is enabled.</description> 833 <value>1</value> 834 </enumeratedValue> 835 </enumeratedValues> 836 </field> 837 <field> 838 <name>SSD</name> 839 <description>Slave Select Deasserted interrupt enable.</description> 840 <bitOffset>5</bitOffset> 841 <bitWidth>1</bitWidth> 842 <enumeratedValues> 843 <enumeratedValue> 844 <name>dis</name> 845 <description>Interrupt is disabled.</description> 846 <value>0</value> 847 </enumeratedValue> 848 <enumeratedValue> 849 <name>en</name> 850 <description>Interrupt is enabled.</description> 851 <value>1</value> 852 </enumeratedValue> 853 </enumeratedValues> 854 </field> 855 <field> 856 <name>FAULT</name> 857 <description>Multi-Master Mode Fault interrupt enable.</description> 858 <bitOffset>8</bitOffset> 859 <bitWidth>1</bitWidth> 860 <enumeratedValues> 861 <enumeratedValue> 862 <name>dis</name> 863 <description>Interrupt is disabled.</description> 864 <value>0</value> 865 </enumeratedValue> 866 <enumeratedValue> 867 <name>en</name> 868 <description>Interrupt is enabled.</description> 869 <value>1</value> 870 </enumeratedValue> 871 </enumeratedValues> 872 </field> 873 <field> 874 <name>ABORT</name> 875 <description>Slave Abort Detected interrupt enable.</description> 876 <bitOffset>9</bitOffset> 877 <bitWidth>1</bitWidth> 878 <enumeratedValues> 879 <enumeratedValue> 880 <name>dis</name> 881 <description>Interrupt is disabled.</description> 882 <value>0</value> 883 </enumeratedValue> 884 <enumeratedValue> 885 <name>en</name> 886 <description>Interrupt is enabled.</description> 887 <value>1</value> 888 </enumeratedValue> 889 </enumeratedValues> 890 </field> 891 <field> 892 <name>MST_DONE</name> 893 <description>Master Done interrupt enable.</description> 894 <bitOffset>11</bitOffset> 895 <bitWidth>1</bitWidth> 896 <enumeratedValues> 897 <enumeratedValue> 898 <name>dis</name> 899 <description>Interrupt is disabled.</description> 900 <value>0</value> 901 </enumeratedValue> 902 <enumeratedValue> 903 <name>en</name> 904 <description>Interrupt is enabled.</description> 905 <value>1</value> 906 </enumeratedValue> 907 </enumeratedValues> 908 </field> 909 <field> 910 <name>TX_OV</name> 911 <description>Transmit FIFO Overrun interrupt enable.</description> 912 <bitOffset>12</bitOffset> 913 <bitWidth>1</bitWidth> 914 <enumeratedValues> 915 <enumeratedValue> 916 <name>dis</name> 917 <description>Interrupt is disabled.</description> 918 <value>0</value> 919 </enumeratedValue> 920 <enumeratedValue> 921 <name>en</name> 922 <description>Interrupt is enabled.</description> 923 <value>1</value> 924 </enumeratedValue> 925 </enumeratedValues> 926 </field> 927 <field> 928 <name>TX_UN</name> 929 <description>Transmit FIFO Underrun interrupt enable.</description> 930 <bitOffset>13</bitOffset> 931 <bitWidth>1</bitWidth> 932 <enumeratedValues> 933 <enumeratedValue> 934 <name>dis</name> 935 <description>Interrupt is disabled.</description> 936 <value>0</value> 937 </enumeratedValue> 938 <enumeratedValue> 939 <name>en</name> 940 <description>Interrupt is enabled.</description> 941 <value>1</value> 942 </enumeratedValue> 943 </enumeratedValues> 944 </field> 945 <field> 946 <name>RX_OV</name> 947 <description>Receive FIFO Overrun interrupt enable.</description> 948 <bitOffset>14</bitOffset> 949 <bitWidth>1</bitWidth> 950 <enumeratedValues> 951 <enumeratedValue> 952 <name>dis</name> 953 <description>Interrupt is disabled.</description> 954 <value>0</value> 955 </enumeratedValue> 956 <enumeratedValue> 957 <name>en</name> 958 <description>Interrupt is enabled.</description> 959 <value>1</value> 960 </enumeratedValue> 961 </enumeratedValues> 962 </field> 963 <field> 964 <name>RX_UN</name> 965 <description>Receive FIFO Underrun interrupt enable.</description> 966 <bitOffset>15</bitOffset> 967 <bitWidth>1</bitWidth> 968 <enumeratedValues> 969 <enumeratedValue> 970 <name>dis</name> 971 <description>Interrupt is disabled.</description> 972 <value>0</value> 973 </enumeratedValue> 974 <enumeratedValue> 975 <name>en</name> 976 <description>Interrupt is enabled.</description> 977 <value>1</value> 978 </enumeratedValue> 979 </enumeratedValues> 980 </field> 981 </fields> 982 </register> 983 <register> 984 <name>WKFL</name> 985 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 986 <addressOffset>0x28</addressOffset> 987 <access>read-write</access> 988 <fields> 989 <field> 990 <name>TX_THD</name> 991 <description>Wake on TX FIFO Threshold Crossed.</description> 992 <bitOffset>0</bitOffset> 993 <bitWidth>1</bitWidth> 994 <enumeratedValues> 995 <enumeratedValue> 996 <name>clear</name> 997 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 998 <value>1</value> 999 </enumeratedValue> 1000 </enumeratedValues> 1001 </field> 1002 <field> 1003 <name>TX_EM</name> 1004 <description>Wake on TX FIFO Empty.</description> 1005 <bitOffset>1</bitOffset> 1006 <bitWidth>1</bitWidth> 1007 <enumeratedValues> 1008 <enumeratedValue> 1009 <name>clear</name> 1010 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1011 <value>1</value> 1012 </enumeratedValue> 1013 </enumeratedValues> 1014 </field> 1015 <field> 1016 <name>RX_THD</name> 1017 <description>Wake on RX FIFO Threshold Crossed.</description> 1018 <bitOffset>2</bitOffset> 1019 <bitWidth>1</bitWidth> 1020 <enumeratedValues> 1021 <enumeratedValue> 1022 <name>clear</name> 1023 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1024 <value>1</value> 1025 </enumeratedValue> 1026 </enumeratedValues> 1027 </field> 1028 <field> 1029 <name>RX_FULL</name> 1030 <description>Wake on RX FIFO Full.</description> 1031 <bitOffset>3</bitOffset> 1032 <bitWidth>1</bitWidth> 1033 <enumeratedValues> 1034 <enumeratedValue> 1035 <name>clear</name> 1036 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1037 <value>1</value> 1038 </enumeratedValue> 1039 </enumeratedValues> 1040 </field> 1041 </fields> 1042 </register> 1043 <register> 1044 <name>WKEN</name> 1045 <description>Register for wake up enable.</description> 1046 <addressOffset>0x2C</addressOffset> 1047 <access>read-write</access> 1048 <fields> 1049 <field> 1050 <name>TX_THD</name> 1051 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 1052 <bitOffset>0</bitOffset> 1053 <bitWidth>1</bitWidth> 1054 <enumeratedValues> 1055 <enumeratedValue> 1056 <name>dis</name> 1057 <description>Wakeup source disabled.</description> 1058 <value>0</value> 1059 </enumeratedValue> 1060 <enumeratedValue> 1061 <name>en</name> 1062 <description>Wakeup source enabled.</description> 1063 <value>1</value> 1064 </enumeratedValue> 1065 </enumeratedValues> 1066 </field> 1067 <field> 1068 <name>TX_EM</name> 1069 <description>Wake on TX FIFO Empty Enable.</description> 1070 <bitOffset>1</bitOffset> 1071 <bitWidth>1</bitWidth> 1072 <enumeratedValues> 1073 <enumeratedValue> 1074 <name>dis</name> 1075 <description>Wakeup source disabled.</description> 1076 <value>0</value> 1077 </enumeratedValue> 1078 <enumeratedValue> 1079 <name>en</name> 1080 <description>Wakeup source enabled.</description> 1081 <value>1</value> 1082 </enumeratedValue> 1083 </enumeratedValues> 1084 </field> 1085 <field> 1086 <name>RX_THD</name> 1087 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 1088 <bitOffset>2</bitOffset> 1089 <bitWidth>1</bitWidth> 1090 <enumeratedValues> 1091 <enumeratedValue> 1092 <name>dis</name> 1093 <description>Wakeup source disabled.</description> 1094 <value>0</value> 1095 </enumeratedValue> 1096 <enumeratedValue> 1097 <name>en</name> 1098 <description>Wakeup source enabled.</description> 1099 <value>1</value> 1100 </enumeratedValue> 1101 </enumeratedValues> 1102 </field> 1103 <field> 1104 <name>RX_FULL</name> 1105 <description>Wake on RX FIFO Full Enable.</description> 1106 <bitOffset>3</bitOffset> 1107 <bitWidth>1</bitWidth> 1108 <enumeratedValues> 1109 <enumeratedValue> 1110 <name>dis</name> 1111 <description>Wakeup source disabled.</description> 1112 <value>0</value> 1113 </enumeratedValue> 1114 <enumeratedValue> 1115 <name>en</name> 1116 <description>Wakeup source enabled.</description> 1117 <value>1</value> 1118 </enumeratedValue> 1119 </enumeratedValues> 1120 </field> 1121 </fields> 1122 </register> 1123 <register> 1124 <name>STAT</name> 1125 <description>SPI Status register.</description> 1126 <addressOffset>0x30</addressOffset> 1127 <access>read-only</access> 1128 <fields> 1129 <field> 1130 <name>BUSY</name> 1131 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description> 1132 <bitOffset>0</bitOffset> 1133 <bitWidth>1</bitWidth> 1134 <enumeratedValues> 1135 <enumeratedValue> 1136 <name>not</name> 1137 <description>SPI not active.</description> 1138 <value>0</value> 1139 </enumeratedValue> 1140 <enumeratedValue> 1141 <name>active</name> 1142 <description>SPI active.</description> 1143 <value>1</value> 1144 </enumeratedValue> 1145 </enumeratedValues> 1146 </field> 1147 </fields> 1148 </register> 1149 </registers> 1150 </peripheral> 1151 <!-- SPI: Serial Peripheral Interface --> 1152</device>
