1 /** 2 * @file smon_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SMON_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _SMON_REVA_REGS_H_ 27 #define _SMON_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup smon_reva 65 * @defgroup smon_reva_registers SMON_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the SMON_REVA Peripheral Module. 67 * @details The Security Monitor block used to monitor system threat conditions. 68 */ 69 70 /** 71 * @ingroup smon_reva_registers 72 * Structure type to access the SMON_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t extscn; /**< <tt>\b 0x00:</tt> SMON_REVA EXTSCN Register */ 76 __IO uint32_t intscn; /**< <tt>\b 0x04:</tt> SMON_REVA INTSCN Register */ 77 __IO uint32_t secalm; /**< <tt>\b 0x08:</tt> SMON_REVA SECALM Register */ 78 __I uint32_t secdiag; /**< <tt>\b 0x0C:</tt> SMON_REVA SECDIAG Register */ 79 __I uint32_t dlrtc; /**< <tt>\b 0x10:</tt> SMON_REVA DLRTC Register */ 80 __R uint32_t rsv_0x14_0x23[4]; 81 __IO uint32_t meucfg; /**< <tt>\b 0x24:</tt> SMON_REVA MEUCFG Register */ 82 __R uint32_t rsv_0x28_0x33[3]; 83 __I uint32_t secst; /**< <tt>\b 0x34:</tt> SMON_REVA SECST Register */ 84 __IO uint32_t sdbe; /**< <tt>\b 0x38:</tt> SMON_REVA SDBE Register */ 85 } mxc_smon_reva_regs_t; 86 87 /* Register offsets for module SMON_REVA */ 88 /** 89 * @ingroup smon_reva_registers 90 * @defgroup SMON_REVA_Register_Offsets Register Offsets 91 * @brief SMON_REVA Peripheral Register Offsets from the SMON_REVA Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_SMON_REVA_EXTSCN ((uint32_t)0x00000000UL) /**< Offset from SMON_REVA Base Address: <tt> 0x0000</tt> */ 95 #define MXC_R_SMON_REVA_INTSCN ((uint32_t)0x00000004UL) /**< Offset from SMON_REVA Base Address: <tt> 0x0004</tt> */ 96 #define MXC_R_SMON_REVA_SECALM ((uint32_t)0x00000008UL) /**< Offset from SMON_REVA Base Address: <tt> 0x0008</tt> */ 97 #define MXC_R_SMON_REVA_SECDIAG ((uint32_t)0x0000000CUL) /**< Offset from SMON_REVA Base Address: <tt> 0x000C</tt> */ 98 #define MXC_R_SMON_REVA_DLRTC ((uint32_t)0x00000010UL) /**< Offset from SMON_REVA Base Address: <tt> 0x0010</tt> */ 99 #define MXC_R_SMON_REVA_MEUCFG ((uint32_t)0x00000024UL) /**< Offset from SMON_REVA Base Address: <tt> 0x0024</tt> */ 100 #define MXC_R_SMON_REVA_SECST ((uint32_t)0x00000034UL) /**< Offset from SMON_REVA Base Address: <tt> 0x0034</tt> */ 101 #define MXC_R_SMON_REVA_SDBE ((uint32_t)0x00000038UL) /**< Offset from SMON_REVA Base Address: <tt> 0x0038</tt> */ 102 /**@} end of group smon_reva_registers */ 103 104 /** 105 * @ingroup smon_reva_registers 106 * @defgroup SMON_REVA_EXTSCN SMON_REVA_EXTSCN 107 * @brief External Sensor Control Register. 108 * @{ 109 */ 110 #define MXC_F_SMON_REVA_EXTSCN_EXTS_EN0_POS 0 /**< EXTSCN_EXTS_EN0 Position */ 111 #define MXC_F_SMON_REVA_EXTSCN_EXTS_EN0 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_EXTSCN_EXTS_EN0_POS)) /**< EXTSCN_EXTS_EN0 Mask */ 112 113 #define MXC_F_SMON_REVA_EXTSCN_EXTS_EN1_POS 1 /**< EXTSCN_EXTS_EN1 Position */ 114 #define MXC_F_SMON_REVA_EXTSCN_EXTS_EN1 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_EXTSCN_EXTS_EN1_POS)) /**< EXTSCN_EXTS_EN1 Mask */ 115 116 #define MXC_F_SMON_REVA_EXTSCN_EXTS_EN2_POS 2 /**< EXTSCN_EXTS_EN2 Position */ 117 #define MXC_F_SMON_REVA_EXTSCN_EXTS_EN2 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_EXTSCN_EXTS_EN2_POS)) /**< EXTSCN_EXTS_EN2 Mask */ 118 119 #define MXC_F_SMON_REVA_EXTSCN_EXTS_EN3_POS 3 /**< EXTSCN_EXTS_EN3 Position */ 120 #define MXC_F_SMON_REVA_EXTSCN_EXTS_EN3 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_EXTSCN_EXTS_EN3_POS)) /**< EXTSCN_EXTS_EN3 Mask */ 121 122 #define MXC_F_SMON_REVA_EXTSCN_EXTS_EN4_POS 4 /**< EXTSCN_EXTS_EN4 Position */ 123 #define MXC_F_SMON_REVA_EXTSCN_EXTS_EN4 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_EXTSCN_EXTS_EN4_POS)) /**< EXTSCN_EXTS_EN4 Mask */ 124 125 #define MXC_F_SMON_REVA_EXTSCN_EXTS_EN5_POS 5 /**< EXTSCN_EXTS_EN5 Position */ 126 #define MXC_F_SMON_REVA_EXTSCN_EXTS_EN5 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_EXTSCN_EXTS_EN5_POS)) /**< EXTSCN_EXTS_EN5 Mask */ 127 128 #define MXC_F_SMON_REVA_EXTSCN_EXTCNT_POS 16 /**< EXTSCN_EXTCNT Position */ 129 #define MXC_F_SMON_REVA_EXTSCN_EXTCNT ((uint32_t)(0x1FUL << MXC_F_SMON_REVA_EXTSCN_EXTCNT_POS)) /**< EXTSCN_EXTCNT Mask */ 130 131 #define MXC_F_SMON_REVA_EXTSCN_EXTFRQ_POS 21 /**< EXTSCN_EXTFRQ Position */ 132 #define MXC_F_SMON_REVA_EXTSCN_EXTFRQ ((uint32_t)(0x7UL << MXC_F_SMON_REVA_EXTSCN_EXTFRQ_POS)) /**< EXTSCN_EXTFRQ Mask */ 133 #define MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ2000HZ ((uint32_t)0x0UL) /**< EXTSCN_EXTFRQ_FREQ2000HZ Value */ 134 #define MXC_S_SMON_REVA_EXTSCN_EXTFRQ_FREQ2000HZ (MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ2000HZ << MXC_F_SMON_REVA_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ2000HZ Setting */ 135 #define MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ1000HZ ((uint32_t)0x1UL) /**< EXTSCN_EXTFRQ_FREQ1000HZ Value */ 136 #define MXC_S_SMON_REVA_EXTSCN_EXTFRQ_FREQ1000HZ (MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ1000HZ << MXC_F_SMON_REVA_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ1000HZ Setting */ 137 #define MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ500HZ ((uint32_t)0x2UL) /**< EXTSCN_EXTFRQ_FREQ500HZ Value */ 138 #define MXC_S_SMON_REVA_EXTSCN_EXTFRQ_FREQ500HZ (MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ500HZ << MXC_F_SMON_REVA_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ500HZ Setting */ 139 #define MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ250HZ ((uint32_t)0x3UL) /**< EXTSCN_EXTFRQ_FREQ250HZ Value */ 140 #define MXC_S_SMON_REVA_EXTSCN_EXTFRQ_FREQ250HZ (MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ250HZ << MXC_F_SMON_REVA_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ250HZ Setting */ 141 #define MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ125HZ ((uint32_t)0x4UL) /**< EXTSCN_EXTFRQ_FREQ125HZ Value */ 142 #define MXC_S_SMON_REVA_EXTSCN_EXTFRQ_FREQ125HZ (MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ125HZ << MXC_F_SMON_REVA_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ125HZ Setting */ 143 #define MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ63HZ ((uint32_t)0x5UL) /**< EXTSCN_EXTFRQ_FREQ63HZ Value */ 144 #define MXC_S_SMON_REVA_EXTSCN_EXTFRQ_FREQ63HZ (MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ63HZ << MXC_F_SMON_REVA_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ63HZ Setting */ 145 #define MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ31HZ ((uint32_t)0x6UL) /**< EXTSCN_EXTFRQ_FREQ31HZ Value */ 146 #define MXC_S_SMON_REVA_EXTSCN_EXTFRQ_FREQ31HZ (MXC_V_SMON_REVA_EXTSCN_EXTFRQ_FREQ31HZ << MXC_F_SMON_REVA_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ31HZ Setting */ 147 #define MXC_V_SMON_REVA_EXTSCN_EXTFRQ_RFU ((uint32_t)0x7UL) /**< EXTSCN_EXTFRQ_RFU Value */ 148 #define MXC_S_SMON_REVA_EXTSCN_EXTFRQ_RFU (MXC_V_SMON_REVA_EXTSCN_EXTFRQ_RFU << MXC_F_SMON_REVA_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_RFU Setting */ 149 150 #define MXC_F_SMON_REVA_EXTSCN_DIVCLK_POS 24 /**< EXTSCN_DIVCLK Position */ 151 #define MXC_F_SMON_REVA_EXTSCN_DIVCLK ((uint32_t)(0x7UL << MXC_F_SMON_REVA_EXTSCN_DIVCLK_POS)) /**< EXTSCN_DIVCLK Mask */ 152 #define MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV1 ((uint32_t)0x0UL) /**< EXTSCN_DIVCLK_DIV1 Value */ 153 #define MXC_S_SMON_REVA_EXTSCN_DIVCLK_DIV1 (MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV1 << MXC_F_SMON_REVA_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV1 Setting */ 154 #define MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV2 ((uint32_t)0x1UL) /**< EXTSCN_DIVCLK_DIV2 Value */ 155 #define MXC_S_SMON_REVA_EXTSCN_DIVCLK_DIV2 (MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV2 << MXC_F_SMON_REVA_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV2 Setting */ 156 #define MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV4 ((uint32_t)0x2UL) /**< EXTSCN_DIVCLK_DIV4 Value */ 157 #define MXC_S_SMON_REVA_EXTSCN_DIVCLK_DIV4 (MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV4 << MXC_F_SMON_REVA_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV4 Setting */ 158 #define MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV8 ((uint32_t)0x3UL) /**< EXTSCN_DIVCLK_DIV8 Value */ 159 #define MXC_S_SMON_REVA_EXTSCN_DIVCLK_DIV8 (MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV8 << MXC_F_SMON_REVA_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV8 Setting */ 160 #define MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV16 ((uint32_t)0x4UL) /**< EXTSCN_DIVCLK_DIV16 Value */ 161 #define MXC_S_SMON_REVA_EXTSCN_DIVCLK_DIV16 (MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV16 << MXC_F_SMON_REVA_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV16 Setting */ 162 #define MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV32 ((uint32_t)0x5UL) /**< EXTSCN_DIVCLK_DIV32 Value */ 163 #define MXC_S_SMON_REVA_EXTSCN_DIVCLK_DIV32 (MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV32 << MXC_F_SMON_REVA_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV32 Setting */ 164 #define MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV64 ((uint32_t)0x6UL) /**< EXTSCN_DIVCLK_DIV64 Value */ 165 #define MXC_S_SMON_REVA_EXTSCN_DIVCLK_DIV64 (MXC_V_SMON_REVA_EXTSCN_DIVCLK_DIV64 << MXC_F_SMON_REVA_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV64 Setting */ 166 167 #define MXC_F_SMON_REVA_EXTSCN_BUSY_POS 30 /**< EXTSCN_BUSY Position */ 168 #define MXC_F_SMON_REVA_EXTSCN_BUSY ((uint32_t)(0x1UL << MXC_F_SMON_REVA_EXTSCN_BUSY_POS)) /**< EXTSCN_BUSY Mask */ 169 170 #define MXC_F_SMON_REVA_EXTSCN_LOCK_POS 31 /**< EXTSCN_LOCK Position */ 171 #define MXC_F_SMON_REVA_EXTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_REVA_EXTSCN_LOCK_POS)) /**< EXTSCN_LOCK Mask */ 172 173 /**@} end of group SMON_REVA_EXTSCN_Register */ 174 175 /** 176 * @ingroup smon_reva_registers 177 * @defgroup SMON_REVA_INTSCN SMON_REVA_INTSCN 178 * @brief Internal Sensor Control Register. 179 * @{ 180 */ 181 #define MXC_F_SMON_REVA_INTSCN_SHIELD_EN_POS 0 /**< INTSCN_SHIELD_EN Position */ 182 #define MXC_F_SMON_REVA_INTSCN_SHIELD_EN ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_SHIELD_EN_POS)) /**< INTSCN_SHIELD_EN Mask */ 183 184 #define MXC_F_SMON_REVA_INTSCN_TEMP_EN_POS 1 /**< INTSCN_TEMP_EN Position */ 185 #define MXC_F_SMON_REVA_INTSCN_TEMP_EN ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_TEMP_EN_POS)) /**< INTSCN_TEMP_EN Mask */ 186 187 #define MXC_F_SMON_REVA_INTSCN_VBAT_EN_POS 2 /**< INTSCN_VBAT_EN Position */ 188 #define MXC_F_SMON_REVA_INTSCN_VBAT_EN ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_VBAT_EN_POS)) /**< INTSCN_VBAT_EN Mask */ 189 190 #define MXC_F_SMON_REVA_INTSCN_DFD_EN_POS 3 /**< INTSCN_DFD_EN Position */ 191 #define MXC_F_SMON_REVA_INTSCN_DFD_EN ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_DFD_EN_POS)) /**< INTSCN_DFD_EN Mask */ 192 193 #define MXC_F_SMON_REVA_INTSCN_DFD_NMI_POS 4 /**< INTSCN_DFD_NMI Position */ 194 #define MXC_F_SMON_REVA_INTSCN_DFD_NMI ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_DFD_NMI_POS)) /**< INTSCN_DFD_NMI Mask */ 195 196 #define MXC_F_SMON_REVA_INTSCN_DFD_STDBY_POS 8 /**< INTSCN_DFD_STDBY Position */ 197 #define MXC_F_SMON_REVA_INTSCN_DFD_STDBY ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_DFD_STDBY_POS)) /**< INTSCN_DFD_STDBY Mask */ 198 199 #define MXC_F_SMON_REVA_INTSCN_PUF_TRIM_ERASE_POS 10 /**< INTSCN_PUF_TRIM_ERASE Position */ 200 #define MXC_F_SMON_REVA_INTSCN_PUF_TRIM_ERASE ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_PUF_TRIM_ERASE_POS)) /**< INTSCN_PUF_TRIM_ERASE Mask */ 201 202 #define MXC_F_SMON_REVA_INTSCN_LOTEMP_SEL_POS 16 /**< INTSCN_LOTEMP_SEL Position */ 203 #define MXC_F_SMON_REVA_INTSCN_LOTEMP_SEL ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_LOTEMP_SEL_POS)) /**< INTSCN_LOTEMP_SEL Mask */ 204 205 #define MXC_F_SMON_REVA_INTSCN_VCORELOEN_POS 18 /**< INTSCN_VCORELOEN Position */ 206 #define MXC_F_SMON_REVA_INTSCN_VCORELOEN ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_VCORELOEN_POS)) /**< INTSCN_VCORELOEN Mask */ 207 208 #define MXC_F_SMON_REVA_INTSCN_VCOREHIEN_POS 19 /**< INTSCN_VCOREHIEN Position */ 209 #define MXC_F_SMON_REVA_INTSCN_VCOREHIEN ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_VCOREHIEN_POS)) /**< INTSCN_VCOREHIEN Mask */ 210 211 #define MXC_F_SMON_REVA_INTSCN_VDDLOEN_POS 20 /**< INTSCN_VDDLOEN Position */ 212 #define MXC_F_SMON_REVA_INTSCN_VDDLOEN ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_VDDLOEN_POS)) /**< INTSCN_VDDLOEN Mask */ 213 214 #define MXC_F_SMON_REVA_INTSCN_VDDHIEN_POS 21 /**< INTSCN_VDDHIEN Position */ 215 #define MXC_F_SMON_REVA_INTSCN_VDDHIEN ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_VDDHIEN_POS)) /**< INTSCN_VDDHIEN Mask */ 216 217 #define MXC_F_SMON_REVA_INTSCN_VGLEN_POS 22 /**< INTSCN_VGLEN Position */ 218 #define MXC_F_SMON_REVA_INTSCN_VGLEN ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_VGLEN_POS)) /**< INTSCN_VGLEN Mask */ 219 220 #define MXC_F_SMON_REVA_INTSCN_LOCK_POS 31 /**< INTSCN_LOCK Position */ 221 #define MXC_F_SMON_REVA_INTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_REVA_INTSCN_LOCK_POS)) /**< INTSCN_LOCK Mask */ 222 223 /**@} end of group SMON_REVA_INTSCN_Register */ 224 225 /** 226 * @ingroup smon_reva_registers 227 * @defgroup SMON_REVA_SECALM SMON_REVA_SECALM 228 * @brief Security Alarm Register. 229 * @{ 230 */ 231 #define MXC_F_SMON_REVA_SECALM_DRS_POS 0 /**< SECALM_DRS Position */ 232 #define MXC_F_SMON_REVA_SECALM_DRS ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_DRS_POS)) /**< SECALM_DRS Mask */ 233 234 #define MXC_F_SMON_REVA_SECALM_KEYWIPE_POS 1 /**< SECALM_KEYWIPE Position */ 235 #define MXC_F_SMON_REVA_SECALM_KEYWIPE ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_KEYWIPE_POS)) /**< SECALM_KEYWIPE Mask */ 236 237 #define MXC_F_SMON_REVA_SECALM_SHIELDF_POS 2 /**< SECALM_SHIELDF Position */ 238 #define MXC_F_SMON_REVA_SECALM_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_SHIELDF_POS)) /**< SECALM_SHIELDF Mask */ 239 240 #define MXC_F_SMON_REVA_SECALM_LOTEMP_POS 3 /**< SECALM_LOTEMP Position */ 241 #define MXC_F_SMON_REVA_SECALM_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_LOTEMP_POS)) /**< SECALM_LOTEMP Mask */ 242 243 #define MXC_F_SMON_REVA_SECALM_HITEMP_POS 4 /**< SECALM_HITEMP Position */ 244 #define MXC_F_SMON_REVA_SECALM_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_HITEMP_POS)) /**< SECALM_HITEMP Mask */ 245 246 #define MXC_F_SMON_REVA_SECALM_BATLO_POS 5 /**< SECALM_BATLO Position */ 247 #define MXC_F_SMON_REVA_SECALM_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_BATLO_POS)) /**< SECALM_BATLO Mask */ 248 249 #define MXC_F_SMON_REVA_SECALM_BATHI_POS 6 /**< SECALM_BATHI Position */ 250 #define MXC_F_SMON_REVA_SECALM_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_BATHI_POS)) /**< SECALM_BATHI Mask */ 251 252 #define MXC_F_SMON_REVA_SECALM_EXTF_POS 7 /**< SECALM_EXTF Position */ 253 #define MXC_F_SMON_REVA_SECALM_EXTF ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_EXTF_POS)) /**< SECALM_EXTF Mask */ 254 255 #define MXC_F_SMON_REVA_SECALM_VDDLO_POS 8 /**< SECALM_VDDLO Position */ 256 #define MXC_F_SMON_REVA_SECALM_VDDLO ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_VDDLO_POS)) /**< SECALM_VDDLO Mask */ 257 258 #define MXC_F_SMON_REVA_SECALM_VCORELO_POS 9 /**< SECALM_VCORELO Position */ 259 #define MXC_F_SMON_REVA_SECALM_VCORELO ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_VCORELO_POS)) /**< SECALM_VCORELO Mask */ 260 261 #define MXC_F_SMON_REVA_SECALM_VCOREHI_POS 10 /**< SECALM_VCOREHI Position */ 262 #define MXC_F_SMON_REVA_SECALM_VCOREHI ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_VCOREHI_POS)) /**< SECALM_VCOREHI Mask */ 263 264 #define MXC_F_SMON_REVA_SECALM_VDDHI_POS 11 /**< SECALM_VDDHI Position */ 265 #define MXC_F_SMON_REVA_SECALM_VDDHI ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_VDDHI_POS)) /**< SECALM_VDDHI Mask */ 266 267 #define MXC_F_SMON_REVA_SECALM_VGL_POS 12 /**< SECALM_VGL Position */ 268 #define MXC_F_SMON_REVA_SECALM_VGL ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_VGL_POS)) /**< SECALM_VGL Mask */ 269 270 #define MXC_F_SMON_REVA_SECALM_EXTSTAT0_POS 16 /**< SECALM_EXTSTAT0 Position */ 271 #define MXC_F_SMON_REVA_SECALM_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_EXTSTAT0_POS)) /**< SECALM_EXTSTAT0 Mask */ 272 273 #define MXC_F_SMON_REVA_SECALM_EXTSTAT1_POS 17 /**< SECALM_EXTSTAT1 Position */ 274 #define MXC_F_SMON_REVA_SECALM_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_EXTSTAT1_POS)) /**< SECALM_EXTSTAT1 Mask */ 275 276 #define MXC_F_SMON_REVA_SECALM_EXTSTAT2_POS 18 /**< SECALM_EXTSTAT2 Position */ 277 #define MXC_F_SMON_REVA_SECALM_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_EXTSTAT2_POS)) /**< SECALM_EXTSTAT2 Mask */ 278 279 #define MXC_F_SMON_REVA_SECALM_EXTSTAT3_POS 19 /**< SECALM_EXTSTAT3 Position */ 280 #define MXC_F_SMON_REVA_SECALM_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_EXTSTAT3_POS)) /**< SECALM_EXTSTAT3 Mask */ 281 282 #define MXC_F_SMON_REVA_SECALM_EXTSTAT4_POS 20 /**< SECALM_EXTSTAT4 Position */ 283 #define MXC_F_SMON_REVA_SECALM_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_EXTSTAT4_POS)) /**< SECALM_EXTSTAT4 Mask */ 284 285 #define MXC_F_SMON_REVA_SECALM_EXTSTAT5_POS 21 /**< SECALM_EXTSTAT5 Position */ 286 #define MXC_F_SMON_REVA_SECALM_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_EXTSTAT5_POS)) /**< SECALM_EXTSTAT5 Mask */ 287 288 #define MXC_F_SMON_REVA_SECALM_EXTSWARN0_POS 24 /**< SECALM_EXTSWARN0 Position */ 289 #define MXC_F_SMON_REVA_SECALM_EXTSWARN0 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_EXTSWARN0_POS)) /**< SECALM_EXTSWARN0 Mask */ 290 291 #define MXC_F_SMON_REVA_SECALM_EXTSWARN1_POS 25 /**< SECALM_EXTSWARN1 Position */ 292 #define MXC_F_SMON_REVA_SECALM_EXTSWARN1 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_EXTSWARN1_POS)) /**< SECALM_EXTSWARN1 Mask */ 293 294 #define MXC_F_SMON_REVA_SECALM_EXTSWARN2_POS 26 /**< SECALM_EXTSWARN2 Position */ 295 #define MXC_F_SMON_REVA_SECALM_EXTSWARN2 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_EXTSWARN2_POS)) /**< SECALM_EXTSWARN2 Mask */ 296 297 #define MXC_F_SMON_REVA_SECALM_EXTSWARN3_POS 27 /**< SECALM_EXTSWARN3 Position */ 298 #define MXC_F_SMON_REVA_SECALM_EXTSWARN3 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_EXTSWARN3_POS)) /**< SECALM_EXTSWARN3 Mask */ 299 300 #define MXC_F_SMON_REVA_SECALM_EXTSWARN4_POS 28 /**< SECALM_EXTSWARN4 Position */ 301 #define MXC_F_SMON_REVA_SECALM_EXTSWARN4 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_EXTSWARN4_POS)) /**< SECALM_EXTSWARN4 Mask */ 302 303 #define MXC_F_SMON_REVA_SECALM_EXTSWARN5_POS 29 /**< SECALM_EXTSWARN5 Position */ 304 #define MXC_F_SMON_REVA_SECALM_EXTSWARN5 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECALM_EXTSWARN5_POS)) /**< SECALM_EXTSWARN5 Mask */ 305 306 /**@} end of group SMON_REVA_SECALM_Register */ 307 308 /** 309 * @ingroup smon_reva_registers 310 * @defgroup SMON_REVA_SECDIAG SMON_REVA_SECDIAG 311 * @brief Security Diagnostic Register. 312 * @{ 313 */ 314 #define MXC_F_SMON_REVA_SECDIAG_BORF_POS 0 /**< SECDIAG_BORF Position */ 315 #define MXC_F_SMON_REVA_SECDIAG_BORF ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_BORF_POS)) /**< SECDIAG_BORF Mask */ 316 317 #define MXC_F_SMON_REVA_SECDIAG_SHIELDF_POS 2 /**< SECDIAG_SHIELDF Position */ 318 #define MXC_F_SMON_REVA_SECDIAG_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_SHIELDF_POS)) /**< SECDIAG_SHIELDF Mask */ 319 320 #define MXC_F_SMON_REVA_SECDIAG_LOTEMP_POS 3 /**< SECDIAG_LOTEMP Position */ 321 #define MXC_F_SMON_REVA_SECDIAG_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_LOTEMP_POS)) /**< SECDIAG_LOTEMP Mask */ 322 323 #define MXC_F_SMON_REVA_SECDIAG_HITEMP_POS 4 /**< SECDIAG_HITEMP Position */ 324 #define MXC_F_SMON_REVA_SECDIAG_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_HITEMP_POS)) /**< SECDIAG_HITEMP Mask */ 325 326 #define MXC_F_SMON_REVA_SECDIAG_BATLO_POS 5 /**< SECDIAG_BATLO Position */ 327 #define MXC_F_SMON_REVA_SECDIAG_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_BATLO_POS)) /**< SECDIAG_BATLO Mask */ 328 329 #define MXC_F_SMON_REVA_SECDIAG_BATHI_POS 6 /**< SECDIAG_BATHI Position */ 330 #define MXC_F_SMON_REVA_SECDIAG_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_BATHI_POS)) /**< SECDIAG_BATHI Mask */ 331 332 #define MXC_F_SMON_REVA_SECDIAG_DYNF_POS 7 /**< SECDIAG_DYNF Position */ 333 #define MXC_F_SMON_REVA_SECDIAG_DYNF ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_DYNF_POS)) /**< SECDIAG_DYNF Mask */ 334 335 #define MXC_F_SMON_REVA_SECDIAG_AESKT_POS 8 /**< SECDIAG_AESKT Position */ 336 #define MXC_F_SMON_REVA_SECDIAG_AESKT ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_AESKT_POS)) /**< SECDIAG_AESKT Mask */ 337 338 #define MXC_F_SMON_REVA_SECDIAG_EXTSTAT0_POS 16 /**< SECDIAG_EXTSTAT0 Position */ 339 #define MXC_F_SMON_REVA_SECDIAG_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_EXTSTAT0_POS)) /**< SECDIAG_EXTSTAT0 Mask */ 340 341 #define MXC_F_SMON_REVA_SECDIAG_EXTSTAT1_POS 17 /**< SECDIAG_EXTSTAT1 Position */ 342 #define MXC_F_SMON_REVA_SECDIAG_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_EXTSTAT1_POS)) /**< SECDIAG_EXTSTAT1 Mask */ 343 344 #define MXC_F_SMON_REVA_SECDIAG_EXTSTAT2_POS 18 /**< SECDIAG_EXTSTAT2 Position */ 345 #define MXC_F_SMON_REVA_SECDIAG_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_EXTSTAT2_POS)) /**< SECDIAG_EXTSTAT2 Mask */ 346 347 #define MXC_F_SMON_REVA_SECDIAG_EXTSTAT3_POS 19 /**< SECDIAG_EXTSTAT3 Position */ 348 #define MXC_F_SMON_REVA_SECDIAG_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_EXTSTAT3_POS)) /**< SECDIAG_EXTSTAT3 Mask */ 349 350 #define MXC_F_SMON_REVA_SECDIAG_EXTSTAT4_POS 20 /**< SECDIAG_EXTSTAT4 Position */ 351 #define MXC_F_SMON_REVA_SECDIAG_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_EXTSTAT4_POS)) /**< SECDIAG_EXTSTAT4 Mask */ 352 353 #define MXC_F_SMON_REVA_SECDIAG_EXTSTAT5_POS 21 /**< SECDIAG_EXTSTAT5 Position */ 354 #define MXC_F_SMON_REVA_SECDIAG_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECDIAG_EXTSTAT5_POS)) /**< SECDIAG_EXTSTAT5 Mask */ 355 356 /**@} end of group SMON_REVA_SECDIAG_Register */ 357 358 /** 359 * @ingroup smon_reva_registers 360 * @defgroup SMON_REVA_DLRTC SMON_REVA_DLRTC 361 * @brief DRS Log RTC Value. This register contains the 32 bit value in the RTC second 362 * register when the last DRS event occurred. 363 * @{ 364 */ 365 #define MXC_F_SMON_REVA_DLRTC_DLRTC_POS 0 /**< DLRTC_DLRTC Position */ 366 #define MXC_F_SMON_REVA_DLRTC_DLRTC ((uint32_t)(0xFFFFFFFFUL << MXC_F_SMON_REVA_DLRTC_DLRTC_POS)) /**< DLRTC_DLRTC Mask */ 367 368 /**@} end of group SMON_REVA_DLRTC_Register */ 369 370 /** 371 * @ingroup smon_reva_registers 372 * @defgroup SMON_REVA_MEUCFG SMON_REVA_MEUCFG 373 * @brief MEU Configuration 374 * @{ 375 */ 376 #define MXC_F_SMON_REVA_MEUCFG_MEUCFG_POS 0 /**< MEUCFG_MEUCFG Position */ 377 #define MXC_F_SMON_REVA_MEUCFG_MEUCFG ((uint32_t)(0x7FUL << MXC_F_SMON_REVA_MEUCFG_MEUCFG_POS)) /**< MEUCFG_MEUCFG Mask */ 378 379 /**@} end of group SMON_REVA_MEUCFG_Register */ 380 381 /** 382 * @ingroup smon_reva_registers 383 * @defgroup SMON_REVA_SECST SMON_REVA_SECST 384 * @brief Security Monitor Status Register. 385 * @{ 386 */ 387 #define MXC_F_SMON_REVA_SECST_EXTSRS_POS 0 /**< SECST_EXTSRS Position */ 388 #define MXC_F_SMON_REVA_SECST_EXTSRS ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECST_EXTSRS_POS)) /**< SECST_EXTSRS Mask */ 389 390 #define MXC_F_SMON_REVA_SECST_INTSRS_POS 1 /**< SECST_INTSRS Position */ 391 #define MXC_F_SMON_REVA_SECST_INTSRS ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECST_INTSRS_POS)) /**< SECST_INTSRS Mask */ 392 393 #define MXC_F_SMON_REVA_SECST_SECALRS_POS 2 /**< SECST_SECALRS Position */ 394 #define MXC_F_SMON_REVA_SECST_SECALRS ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SECST_SECALRS_POS)) /**< SECST_SECALRS Mask */ 395 396 /**@} end of group SMON_REVA_SECST_Register */ 397 398 /** 399 * @ingroup smon_reva_registers 400 * @defgroup SMON_REVA_SDBE SMON_REVA_SDBE 401 * @brief Security Monitor Self Destruct Byte. 402 * @{ 403 */ 404 #define MXC_F_SMON_REVA_SDBE_DBYTE_POS 0 /**< SDBE_DBYTE Position */ 405 #define MXC_F_SMON_REVA_SDBE_DBYTE ((uint32_t)(0xFFUL << MXC_F_SMON_REVA_SDBE_DBYTE_POS)) /**< SDBE_DBYTE Mask */ 406 407 #define MXC_F_SMON_REVA_SDBE_SBDEN_POS 31 /**< SDBE_SBDEN Position */ 408 #define MXC_F_SMON_REVA_SDBE_SBDEN ((uint32_t)(0x1UL << MXC_F_SMON_REVA_SDBE_SBDEN_POS)) /**< SDBE_SBDEN Mask */ 409 410 /**@} end of group SMON_REVA_SDBE_Register */ 411 412 #ifdef __cplusplus 413 } 414 #endif 415 416 #endif /* _SMON_REVA_REGS_H_ */ 417
