1 /****************************************************************************** 2 * 3 * Copyright (C) 2024 Analog Devices, Inc. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ******************************************************************************/ 18 19 /** 20 * @file sfcc_reva_regs.h 21 * @brief Registers, Bit Masks and Bit Positions for the SFCC_REVA Peripheral Module. 22 */ 23 24 #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SFCC_SFCC_REVA_REGS_H_ 25 #define LIBRARIES_PERIPHDRIVERS_SOURCE_SFCC_SFCC_REVA_REGS_H_ 26 27 /* **** Includes **** */ 28 #include <stdint.h> 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #if defined (__SFCCARM__) 35 #pragma system_include 36 #endif 37 38 #if defined (__CC_ARM) 39 #pragma anon_unions 40 #endif 41 /// @cond 42 /* 43 If types are not defined elsewhere (CMSIS) define them here 44 */ 45 #ifndef __IO 46 #define __IO volatile 47 #endif 48 #ifndef __I 49 #define __I volatile const 50 #endif 51 #ifndef __O 52 #define __O volatile 53 #endif 54 #ifndef __R 55 #define __R volatile const 56 #endif 57 /// @endcond 58 59 /* **** Definitions **** */ 60 61 /** 62 * @ingroup sfcc_reva 63 * @defgroup sfcc_reva_registers SFCC_REVA_Registers 64 * @brief Registers, Bit Masks and Bit Positions for the SFCC_REVA Peripheral Module. 65 * @details Instruction Cache Controller Registers 66 */ 67 68 /** 69 * @ingroup sfcc_reva_registers 70 * Structure type to access the SFCC_REVA Registers. 71 */ 72 typedef struct { 73 __I uint32_t info; /**< <tt>\b 0x0000:</tt> SFCC_REVA INFO Register */ 74 __I uint32_t sz; /**< <tt>\b 0x0004:</tt> SFCC_REVA SZ Register */ 75 __R uint32_t rsv_0x8_0xff[62]; 76 __IO uint32_t ctrl; /**< <tt>\b 0x0100:</tt> SFCC_REVA CTRL Register */ 77 __R uint32_t rsv_0x104_0x6ff[383]; 78 __IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> SFCC_REVA INVALIDATE Register */ 79 } mxc_sfcc_reva_regs_t; 80 81 /* Register offsets for module SFCC_REVA */ 82 /** 83 * @ingroup sfcc_reva_registers 84 * @defgroup SFCC_REVA_Register_Offsets Register Offsets 85 * @brief SFCC_REVA Peripheral Register Offsets from the SFCC_REVA Base Peripheral Address. 86 * @{ 87 */ 88 #define MXC_R_SFCC_REVA_INFO ((uint32_t)0x00000000UL) /**< Offset from SFCC_REVA Base Address: <tt> 0x0000</tt> */ 89 #define MXC_R_SFCC_REVA_SZ ((uint32_t)0x00000004UL) /**< Offset from SFCC_REVA Base Address: <tt> 0x0004</tt> */ 90 #define MXC_R_SFCC_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from SFCC_REVA Base Address: <tt> 0x0100</tt> */ 91 #define MXC_R_SFCC_REVA_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from SFCC_REVA Base Address: <tt> 0x0700</tt> */ 92 /**@} end of group sfcc_reva_registers */ 93 94 /** 95 * @ingroup sfcc_reva_registers 96 * @defgroup SFCC_REVA_INFO SFCC_REVA_INFO 97 * @brief Cache ID Register. 98 * @{ 99 */ 100 #define MXC_F_SFCC_REVA_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ 101 #define MXC_F_SFCC_REVA_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_SFCC_REVA_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ 102 103 #define MXC_F_SFCC_REVA_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ 104 #define MXC_F_SFCC_REVA_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_SFCC_REVA_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ 105 106 #define MXC_F_SFCC_REVA_INFO_ID_POS 10 /**< INFO_ID Position */ 107 #define MXC_F_SFCC_REVA_INFO_ID ((uint32_t)(0x3FUL << MXC_F_SFCC_REVA_INFO_ID_POS)) /**< INFO_ID Mask */ 108 109 /**@} end of group SFCC_REVA_INFO_Register */ 110 111 /** 112 * @ingroup sfcc_reva_registers 113 * @defgroup SFCC_REVA_SZ SFCC_REVA_SZ 114 * @brief Memory Configuration Register. 115 * @{ 116 */ 117 #define MXC_F_SFCC_REVA_SZ_CCH_POS 0 /**< SZ_CCH Position */ 118 #define MXC_F_SFCC_REVA_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_SFCC_REVA_SZ_CCH_POS)) /**< SZ_CCH Mask */ 119 120 #define MXC_F_SFCC_REVA_SZ_MEM_POS 16 /**< SZ_MEM Position */ 121 #define MXC_F_SFCC_REVA_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_SFCC_REVA_SZ_MEM_POS)) /**< SZ_MEM Mask */ 122 123 /**@} end of group SFCC_REVA_SZ_Register */ 124 125 /** 126 * @ingroup sfcc_reva_registers 127 * @defgroup SFCC_REVA_CTRL SFCC_REVA_CTRL 128 * @brief Cache Control and Status Register. 129 * @{ 130 */ 131 #define MXC_F_SFCC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ 132 #define MXC_F_SFCC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_SFCC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ 133 134 #define MXC_F_SFCC_REVA_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ 135 #define MXC_F_SFCC_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_SFCC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 136 137 /**@} end of group SFCC_REVA_CTRL_Register */ 138 139 /** 140 * @ingroup sfcc_reva_registers 141 * @defgroup SFCC_REVA_INVALIDATE SFCC_REVA_INVALIDATE 142 * @brief Invalidate All Registers. 143 * @{ 144 */ 145 #define MXC_F_SFCC_REVA_INVALIDATE_INVALID_POS 0 /**< INVALIDATE_INVALID Position */ 146 #define MXC_F_SFCC_REVA_INVALIDATE_INVALID ((uint32_t)(0xFFFFFFFFUL << MXC_F_SFCC_REVA_INVALIDATE_INVALID_POS)) /**< INVALIDATE_INVALID Mask */ 147 148 /**@} end of group SFCC_REVA_INVALIDATE_Register */ 149 150 #ifdef __cplusplus 151 } 152 #endif 153 154 #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SFCC_SFCC_REVA_REGS_H_ 155 156
