1 /** 2 * @file sema_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SEMA_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _SEMA_REVA_REGS_H_ 27 #define _SEMA_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup sema_reva 65 * @defgroup sema_reva_registers SEMA_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the SEMA_REVA Peripheral Module. 67 * @details The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. 68 The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software 69 architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be 70 71 modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. 72 */ 73 74 /** 75 * @ingroup sema_reva_registers 76 * Structure type to access the SEMA_REVA Registers. 77 */ 78 typedef struct { 79 __IO uint32_t semaphores[8]; /**< <tt>\b 0x00:</tt> SEMA SEMAPHORES Register */ 80 __R uint32_t rsv_0x20_0x3f[8]; 81 __IO uint32_t irq0; /**< <tt>\b 0x40:</tt> SEMA IRQ0 Register */ 82 __IO uint32_t mail0; /**< <tt>\b 0x44:</tt> SEMA MAIL0 Register */ 83 __IO uint32_t irq1; /**< <tt>\b 0x48:</tt> SEMA IRQ1 Register */ 84 __IO uint32_t mail1; /**< <tt>\b 0x4C:</tt> SEMA MAIL1 Register */ 85 __R uint32_t rsv_0x50_0xff[44]; 86 __IO uint32_t status; /**< <tt>\b 0x100:</tt> SEMA STATUS Register */ 87 } mxc_sema_reva_regs_t; 88 89 /* Register offsets for module SEMA_REVA */ 90 /** 91 * @ingroup sema_reva_registers 92 * @defgroup SEMA_REVA_Register_Offsets Register Offsets 93 * @brief SEMA_REVA Peripheral Register Offsets from the SEMA_REVA Base Peripheral Address. 94 * @{ 95 */ 96 #define MXC_R_SEMA_REVA_SEMAPHORES ((uint32_t)0x00000000UL) /**< Offset from SEMA Base Address: <tt> 0x0000</tt> */ 97 #define MXC_R_SEMA_REVA_IRQ0 ((uint32_t)0x00000040UL) /**< Offset from SEMA Base Address: <tt> 0x0040</tt> */ 98 #define MXC_R_SEMA_REVA_MAIL0 ((uint32_t)0x00000044UL) /**< Offset from SEMA Base Address: <tt> 0x0044</tt> */ 99 #define MXC_R_SEMA_REVA_IRQ1 ((uint32_t)0x00000048UL) /**< Offset from SEMA Base Address: <tt> 0x0048</tt> */ 100 #define MXC_R_SEMA_REVA_MAIL1 ((uint32_t)0x0000004CUL) /**< Offset from SEMA Base Address: <tt> 0x004C</tt> */ 101 #define MXC_R_SEMA_REVA_STATUS ((uint32_t)0x00000100UL) /**< Offset from SEMA Base Address: <tt> 0x0100</tt> */ 102 /**@} end of group sema_registers */ 103 104 /** 105 * @ingroup sema_reva_registers 106 * @defgroup SEMA_REVA_SEMAPHORES SEMA_REVA_SEMAPHORES 107 * @brief Read to test and set, returns prior value. Write 0 to clear semaphore. 108 * @{ 109 */ 110 #define MXC_F_SEMA_REVA_SEMAPHORES_SEMA_POS 0 /**< SEMAPHORES_SEMA Position */ 111 #define MXC_F_SEMA_REVA_SEMAPHORES_SEMA ((uint32_t)(0x1UL << MXC_F_SEMA_REVA_SEMAPHORES_SEMA_POS)) /**< SEMAPHORES_SEMA Mask */ 112 113 /**@} end of group SEMA_REVA_SEMAPHORES_Register */ 114 115 /** 116 * @ingroup sema_registers 117 * @defgroup SEMA_REVA_IRQ0 SEMA_REVA_IRQ0 118 * @brief Semaphore IRQ0 register. 119 * @{ 120 */ 121 #define MXC_F_SEMA_REVA_IRQ0_EN_POS 0 /**< IRQ0_EN Position */ 122 #define MXC_F_SEMA_REVA_IRQ0_EN ((uint32_t)(0x1UL << MXC_F_SEMA_REVA_IRQ0_EN_POS)) /**< IRQ0_EN Mask */ 123 124 #define MXC_F_SEMA_REVA_IRQ0_CM4_IRQ_POS 16 /**< IRQ0_CM4_IRQ Position */ 125 #define MXC_F_SEMA_REVA_IRQ0_CM4_IRQ ((uint32_t)(0x1UL << MXC_F_SEMA_REVA_IRQ0_CM4_IRQ_POS)) /**< IRQ0_CM4_IRQ Mask */ 126 127 /**@} end of group SEMA_REVA_IRQ0_Register */ 128 129 /** 130 * @ingroup sema_registers 131 * @defgroup SEMA_REVA_MAIL0 SEMA_REVA_MAIL0 132 * @brief Semaphore Mailbox 0 register. 133 * @{ 134 */ 135 #define MXC_F_SEMA_REVA_MAIL0_DATA_POS 0 /**< MAIL0_DATA Position */ 136 #define MXC_F_SEMA_REVA_MAIL0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SEMA_REVA_MAIL0_DATA_POS)) /**< MAIL0_DATA Mask */ 137 138 /**@} end of group SEMA_REVA_MAIL0_Register */ 139 140 /** 141 * @ingroup sema_registers 142 * @defgroup SEMA_REVA_IRQ1 SEMA_REVA_IRQ1 143 * @brief Semaphore IRQ1 register. 144 * @{ 145 */ 146 #define MXC_F_SEMA_REVA_IRQ1_EN_POS 0 /**< IRQ1_EN Position */ 147 #define MXC_F_SEMA_REVA_IRQ1_EN ((uint32_t)(0x1UL << MXC_F_SEMA_REVA_IRQ1_EN_POS)) /**< IRQ1_EN Mask */ 148 149 #define MXC_F_SEMA_REVA_IRQ1_RV32_IRQ_POS 16 /**< IRQ1_RV32_IRQ Position */ 150 #define MXC_F_SEMA_REVA_IRQ1_RV32_IRQ ((uint32_t)(0x1UL << MXC_F_SEMA_REVA_IRQ1_RV32_IRQ_POS)) /**< IRQ1_RV32_IRQ Mask */ 151 152 /**@} end of group SEMA_REVA_IRQ1_Register */ 153 154 /** 155 * @ingroup sema_registers 156 * @defgroup SEMA_REVA_MAIL1 SEMA_REVA_MAIL1 157 * @brief Semaphore Mailbox 1 register. 158 * @{ 159 */ 160 #define MXC_F_SEMA_REVA_MAIL1_DATA_POS 0 /**< MAIL1_DATA Position */ 161 #define MXC_F_SEMA_REVA_MAIL1_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SEMA_REVA_MAIL1_DATA_POS)) /**< MAIL1_DATA Mask */ 162 163 /**@} end of group SEMA_REVA_MAIL1_Register */ 164 165 /** 166 * @ingroup sema_registers 167 * @defgroup SEMA_REVA_STATUS SEMA_REVA_STATUS 168 * @brief Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken. 169 * @{ 170 */ 171 #define MXC_F_SEMA_REVA_STATUS_STATUS_POS 0 /**< STATUS_STATUS Position */ 172 #define MXC_F_SEMA_REVA_STATUS_STATUS ((uint32_t)(0xFFUL << MXC_F_SEMA_REVA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ 173 174 /**@} end of group SEMA_REVA_STATUS_Register */ 175 176 #ifdef __cplusplus 177 } 178 #endif 179 180 #endif /* _SEMA_REVA_REGS_H_ */ 181
