1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SDHC</name> 5 <description>SDHC/SDIO Controller</description> 6 <baseAddress>0x400B6000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>SDHC</name> 14 <value>66</value> 15 </interrupt> 16 <registers> 17 <register> 18 <name>SDMA</name> 19 <description>SDMA System Address / Argument 2.</description> 20 <addressOffset>0x00</addressOffset> 21 <size>32</size> 22 <fields> 23 <field> 24 <name>ADDR</name> 25 <description>SDMA System Address / Argument 2 of Auto CMD23.</description> 26 <bitOffset>0</bitOffset> 27 <bitWidth>32</bitWidth> 28 </field> 29 </fields> 30 </register> 31 <register> 32 <name>BLK_SIZE</name> 33 <description>Block Size.</description> 34 <addressOffset>0x04</addressOffset> 35 <size>16</size> 36 <fields> 37 <field> 38 <name>TRANS</name> 39 <description>Transfer Block Size.</description> 40 <bitOffset>0</bitOffset> 41 <bitWidth>12</bitWidth> 42 </field> 43 <field> 44 <name>HOST_BUFF</name> 45 <description>Host SDMA Buffer Boundary.</description> 46 <bitOffset>12</bitOffset> 47 <bitWidth>3</bitWidth> 48 </field> 49 </fields> 50 </register> 51 <register> 52 <name>BLK_CNT</name> 53 <description>Block Count.</description> 54 <addressOffset>0x06</addressOffset> 55 <size>16</size> 56 <fields> 57 <field> 58 <name>COUNT</name> 59 <description>Blocks Count For Current Transfer.</description> 60 <bitOffset>0</bitOffset> 61 <bitWidth>16</bitWidth> 62 </field> 63 </fields> 64 </register> 65 <register> 66 <name>ARG_1</name> 67 <description>Argument 1.</description> 68 <addressOffset>0x08</addressOffset> 69 <size>32</size> 70 <fields> 71 <field> 72 <name>CMD</name> 73 <description>Command Argument 1.</description> 74 <bitOffset>0</bitOffset> 75 <bitWidth>32</bitWidth> 76 </field> 77 </fields> 78 </register> 79 <register> 80 <name>TRANS</name> 81 <description>Transfer Mode.</description> 82 <addressOffset>0x0C</addressOffset> 83 <size>16</size> 84 <fields> 85 <field> 86 <name>DMA_EN</name> 87 <description>DMA Enable.</description> 88 <bitOffset>0</bitOffset> 89 <bitWidth>1</bitWidth> 90 <enumeratedValues> 91 <name>enable</name> 92 <enumeratedValue> 93 <name>dma_transfer</name> 94 <value>1</value> 95 </enumeratedValue> 96 <enumeratedValue> 97 <name>non_dma_transfer</name> 98 <value>0</value> 99 </enumeratedValue> 100 </enumeratedValues> 101 </field> 102 <field> 103 <name>BLK_CNT_EN</name> 104 <description>Block Count Enable.</description> 105 <bitOffset>1</bitOffset> 106 <bitWidth>1</bitWidth> 107 <enumeratedValues> 108 <name>count</name> 109 <enumeratedValue> 110 <name>enable</name> 111 <value>1</value> 112 </enumeratedValue> 113 <enumeratedValue> 114 <name>disable</name> 115 <value>0</value> 116 </enumeratedValue> 117 </enumeratedValues> 118 </field> 119 <field> 120 <name>AUTO_CMD_EN</name> 121 <description>Auto CMD Enable.</description> 122 <bitOffset>2</bitOffset> 123 <bitWidth>2</bitWidth> 124 <enumeratedValues> 125 <name>CMD</name> 126 <enumeratedValue> 127 <name>disable</name> 128 <value>0</value> 129 </enumeratedValue> 130 <enumeratedValue> 131 <name>cmd12</name> 132 <value>1</value> 133 </enumeratedValue> 134 <enumeratedValue> 135 <name>cmd23</name> 136 <value>2</value> 137 </enumeratedValue> 138 </enumeratedValues> 139 </field> 140 <field> 141 <name>READ_WRITE</name> 142 <description>Data Transfer Direction Select.</description> 143 <bitOffset>4</bitOffset> 144 <bitWidth>1</bitWidth> 145 <enumeratedValues> 146 <name>read</name> 147 <enumeratedValue> 148 <name>read</name> 149 <value>1</value> 150 </enumeratedValue> 151 <enumeratedValue> 152 <name>write</name> 153 <value>0</value> 154 </enumeratedValue> 155 </enumeratedValues> 156 </field> 157 <field> 158 <name>MULTI</name> 159 <description>Multi / Single Block Select.</description> 160 <bitOffset>5</bitOffset> 161 <bitWidth>1</bitWidth> 162 <enumeratedValues> 163 <name>multi</name> 164 <enumeratedValue> 165 <name>enable</name> 166 <value>1</value> 167 </enumeratedValue> 168 <enumeratedValue> 169 <name>disable</name> 170 <value>0</value> 171 </enumeratedValue> 172 </enumeratedValues> 173 </field> 174 </fields> 175 </register> 176 <register> 177 <name>CMD</name> 178 <description>Command.</description> 179 <addressOffset>0x0E</addressOffset> 180 <size>16</size> 181 <fields> 182 <field> 183 <name>RESP_TYPE</name> 184 <description>Response Type Select.</description> 185 <bitOffset>0</bitOffset> 186 <bitWidth>2</bitWidth> 187 </field> 188 <field> 189 <name>CRC_CHK_EN</name> 190 <description>Command CRC Check Enable.</description> 191 <bitOffset>3</bitOffset> 192 <bitWidth>1</bitWidth> 193 </field> 194 <field> 195 <name>IDX_CHK_EN</name> 196 <description>Command Index Check Enable.</description> 197 <bitOffset>4</bitOffset> 198 <bitWidth>1</bitWidth> 199 </field> 200 <field> 201 <name>DATA_PRES_SEL</name> 202 <description>Data Present Select.</description> 203 <bitOffset>5</bitOffset> 204 <bitWidth>1</bitWidth> 205 </field> 206 <field> 207 <name>TYPE</name> 208 <description>Command Type.</description> 209 <bitOffset>6</bitOffset> 210 <bitWidth>2</bitWidth> 211 </field> 212 <field> 213 <name>IDX</name> 214 <description>Command Index.</description> 215 <bitOffset>8</bitOffset> 216 <bitWidth>6</bitWidth> 217 </field> 218 </fields> 219 </register> 220 <register> 221 <dim>4</dim> 222 <dimIncrement>4</dimIncrement> 223 <name>RESP[%s]</name> 224 <description>Response 0 Register 0-15.</description> 225 <addressOffset>0x010</addressOffset> 226 <size>32</size> 227 <fields> 228 <field> 229 <name>CMD_RESP</name> 230 <description>Command Response.</description> 231 <bitOffset>0</bitOffset> 232 <bitWidth>32</bitWidth> 233 </field> 234 </fields> 235 </register> 236 <register> 237 <name>BUFFER</name> 238 <description>Buffer Data Port.</description> 239 <addressOffset>0x20</addressOffset> 240 <size>32</size> 241 <fields> 242 <field> 243 <name>DATA</name> 244 <description>Buffer Data.</description> 245 <bitOffset>0</bitOffset> 246 <bitWidth>32</bitWidth> 247 </field> 248 </fields> 249 </register> 250 <register> 251 <name>PRESENT</name> 252 <description>Present State.</description> 253 <addressOffset>0x024</addressOffset> 254 <size>32</size> 255 <access>read-only</access> 256 <fields> 257 <field> 258 <name>CMD</name> 259 <description>Command Inhibit (CMD).</description> 260 <bitOffset>0</bitOffset> 261 <bitWidth>1</bitWidth> 262 <access>read-only</access> 263 </field> 264 <field> 265 <name>DAT</name> 266 <description>Command Inhibit (DAT).</description> 267 <bitOffset>1</bitOffset> 268 <bitWidth>1</bitWidth> 269 <access>read-only</access> 270 </field> 271 <field> 272 <name>DAT_LINE_ACTIVE</name> 273 <description>DAT Line Active.</description> 274 <bitOffset>2</bitOffset> 275 <bitWidth>1</bitWidth> 276 <access>read-only</access> 277 </field> 278 <field> 279 <name>RETUNING</name> 280 <description>Re-Tuning Request.</description> 281 <bitOffset>3</bitOffset> 282 <bitWidth>1</bitWidth> 283 <access>read-only</access> 284 </field> 285 <field> 286 <name>WRITE_TRANSFER</name> 287 <description>Write Transfer Active.</description> 288 <bitOffset>8</bitOffset> 289 <bitWidth>1</bitWidth> 290 <access>read-only</access> 291 </field> 292 <field> 293 <name>READ_TRANSFER</name> 294 <description>Read Transfer Active.</description> 295 <bitOffset>9</bitOffset> 296 <bitWidth>1</bitWidth> 297 <access>read-only</access> 298 </field> 299 <field> 300 <name>BUFFER_WRITE</name> 301 <description>Buffer Write Enable.</description> 302 <bitOffset>10</bitOffset> 303 <bitWidth>1</bitWidth> 304 <access>read-only</access> 305 </field> 306 <field> 307 <name>BUFFER_READ</name> 308 <description>Buffer Read Enable.</description> 309 <bitOffset>11</bitOffset> 310 <bitWidth>1</bitWidth> 311 <access>read-only</access> 312 </field> 313 <field> 314 <name>CARD_INSERTED</name> 315 <description>Card Inserted.</description> 316 <bitOffset>16</bitOffset> 317 <bitWidth>1</bitWidth> 318 <access>read-only</access> 319 </field> 320 <field> 321 <name>CARD_STATE</name> 322 <description>Card State Stable.</description> 323 <bitOffset>17</bitOffset> 324 <bitWidth>1</bitWidth> 325 <access>read-only</access> 326 </field> 327 <field> 328 <name>CARD_DETECT</name> 329 <description>Card Detect Pin Level.</description> 330 <bitOffset>18</bitOffset> 331 <bitWidth>1</bitWidth> 332 <access>read-only</access> 333 </field> 334 <field> 335 <name>WP</name> 336 <description>Write Protect Switch Pin Level.</description> 337 <bitOffset>19</bitOffset> 338 <bitWidth>1</bitWidth> 339 <access>read-only</access> 340 </field> 341 <field> 342 <name>DAT_SIGNAL_LEVEL</name> 343 <description>DAT[3:0] Line Signal Level.</description> 344 <bitOffset>20</bitOffset> 345 <bitWidth>4</bitWidth> 346 </field> 347 <field> 348 <name>CMD_SIGNAL_LEVEL</name> 349 <description>CMD Line Signal Level.</description> 350 <bitOffset>24</bitOffset> 351 <bitWidth>1</bitWidth> 352 </field> 353 </fields> 354 </register> 355 <register> 356 <name>HOST_CN_1</name> 357 <description>Host Control 1.</description> 358 <addressOffset>0x028</addressOffset> 359 <size>8</size> 360 <fields> 361 <field> 362 <name>LED_CN</name> 363 <description>LED Control.</description> 364 <bitOffset>0</bitOffset> 365 <bitWidth>1</bitWidth> 366 </field> 367 <field> 368 <name>DATA_TRANSFER_WIDTH</name> 369 <description>Data Transfer Width.</description> 370 <bitOffset>1</bitOffset> 371 <bitWidth>1</bitWidth> 372 </field> 373 <field> 374 <name>HS_EN</name> 375 <description>High Speed Enable.</description> 376 <bitOffset>2</bitOffset> 377 <bitWidth>1</bitWidth> 378 </field> 379 <field> 380 <name>DMA_SELECT</name> 381 <description>DMA Select.</description> 382 <bitOffset>3</bitOffset> 383 <bitWidth>2</bitWidth> 384 </field> 385 <field> 386 <name>EXT_DATA_TRANSFER_WIDTH</name> 387 <description>Extended Data Transfer Width.</description> 388 <bitOffset>5</bitOffset> 389 <bitWidth>1</bitWidth> 390 </field> 391 <field> 392 <name>CARD_DETECT_TEST</name> 393 <description>Card Detect Test Level.</description> 394 <bitOffset>6</bitOffset> 395 <bitWidth>1</bitWidth> 396 </field> 397 <field> 398 <name>CARD_DETECT_SIGNAL</name> 399 <description>Card Detect Signal Selection.</description> 400 <bitOffset>7</bitOffset> 401 <bitWidth>1</bitWidth> 402 </field> 403 </fields> 404 </register> 405 <register> 406 <name>PWR</name> 407 <description>Power Control.</description> 408 <addressOffset>0x029</addressOffset> 409 <size>8</size> 410 <fields> 411 <field> 412 <name>BUS_POWER</name> 413 <description>SD Bus Power.</description> 414 <bitOffset>0</bitOffset> 415 <bitWidth>1</bitWidth> 416 </field> 417 <field> 418 <name>BUS_VOLT_SEL</name> 419 <description>SD Bus Voltage Select.</description> 420 <bitOffset>1</bitOffset> 421 <bitWidth>3</bitWidth> 422 </field> 423 </fields> 424 </register> 425 <register> 426 <name>BLK_GAP</name> 427 <description>Block Gap Control.</description> 428 <addressOffset>0x02A</addressOffset> 429 <size>8</size> 430 <fields> 431 <field> 432 <name>STOP</name> 433 <description>Stop At Block Gap Request.</description> 434 <bitOffset>0</bitOffset> 435 <bitWidth>1</bitWidth> 436 </field> 437 <field> 438 <name>CONT</name> 439 <description>Continue Request.</description> 440 <bitOffset>1</bitOffset> 441 <bitWidth>1</bitWidth> 442 </field> 443 <field> 444 <name>READ_WAIT</name> 445 <description>Read Wait Control.</description> 446 <bitOffset>2</bitOffset> 447 <bitWidth>1</bitWidth> 448 </field> 449 <field> 450 <name>INTR</name> 451 <description>Interrupt At Block Gap.</description> 452 <bitOffset>3</bitOffset> 453 <bitWidth>1</bitWidth> 454 </field> 455 </fields> 456 </register> 457 <register> 458 <name>WAKEUP</name> 459 <description>Wakeup Control.</description> 460 <addressOffset>0x02B</addressOffset> 461 <size>8</size> 462 <fields> 463 <field> 464 <name>CARD_INT</name> 465 <description>Wakeup Event Enable On Card Interrupt.</description> 466 <bitOffset>0</bitOffset> 467 <bitWidth>1</bitWidth> 468 </field> 469 <field> 470 <name>CARD_INS</name> 471 <description>Wakeup Event Enable On SD Card Insertion.</description> 472 <bitOffset>1</bitOffset> 473 <bitWidth>1</bitWidth> 474 </field> 475 <field> 476 <name>CARD_REM</name> 477 <description>Wakeup Event Enable On SD Card Removal.</description> 478 <bitOffset>2</bitOffset> 479 <bitWidth>1</bitWidth> 480 </field> 481 </fields> 482 </register> 483 <register> 484 <name>CLK_CN</name> 485 <description>Clock Control.</description> 486 <addressOffset>0x02C</addressOffset> 487 <size>16</size> 488 <fields> 489 <field> 490 <name>INTERNAL_CLK_EN</name> 491 <description>Internal Clock Enable.</description> 492 <bitOffset>0</bitOffset> 493 <bitWidth>1</bitWidth> 494 </field> 495 <field> 496 <name>INTERNAL_CLK_STABLE</name> 497 <description>Internal Clock Stable.</description> 498 <bitOffset>1</bitOffset> 499 <bitWidth>1</bitWidth> 500 <access>read-only</access> 501 </field> 502 <field> 503 <name>SD_CLK_EN</name> 504 <description>SD Clock Enable.</description> 505 <bitOffset>2</bitOffset> 506 <bitWidth>1</bitWidth> 507 </field> 508 <field> 509 <name>CLK_GEN_SEL</name> 510 <description>Clock Generator Select.</description> 511 <bitOffset>5</bitOffset> 512 <bitWidth>1</bitWidth> 513 <access>read-only</access> 514 </field> 515 <field> 516 <name>UPPER_SDCLK_FREQ_SEL</name> 517 <description>Upper Bits of SDCLK Frequency Select.</description> 518 <bitOffset>6</bitOffset> 519 <bitWidth>2</bitWidth> 520 </field> 521 <field> 522 <name>SDCLK_FREQ_SEL</name> 523 <description>SDCLK Frequency Select.</description> 524 <bitOffset>8</bitOffset> 525 <bitWidth>8</bitWidth> 526 </field> 527 </fields> 528 </register> 529 <register> 530 <name>TO</name> 531 <description>Timeout Control.</description> 532 <addressOffset>0x02E</addressOffset> 533 <size>8</size> 534 <fields> 535 <field> 536 <name>DATA_COUNT_VALUE</name> 537 <description>Data Timeout Counter Value.</description> 538 <bitOffset>0</bitOffset> 539 <bitWidth>3</bitWidth> 540 </field> 541 </fields> 542 </register> 543 <register> 544 <name>SW_RESET</name> 545 <description>Software Reset.</description> 546 <addressOffset>0x02F</addressOffset> 547 <size>8</size> 548 <fields> 549 <field> 550 <name>RESET_ALL</name> 551 <description>Software Reset For All.</description> 552 <bitOffset>0</bitOffset> 553 <bitWidth>1</bitWidth> 554 </field> 555 <field> 556 <name>RESET_CMD</name> 557 <description>Software Reset For CMD Line.</description> 558 <bitOffset>1</bitOffset> 559 <bitWidth>1</bitWidth> 560 </field> 561 <field> 562 <name>RESET_DAT</name> 563 <description>Software Reset For DAT Line.</description> 564 <bitOffset>2</bitOffset> 565 <bitWidth>1</bitWidth> 566 </field> 567 </fields> 568 </register> 569 <register> 570 <name>INT_STAT</name> 571 <description>Normal Interrupt Status.</description> 572 <addressOffset>0x030</addressOffset> 573 <size>16</size> 574 <fields> 575 <field> 576 <name>CMD_COMP</name> 577 <description>Command Complete.</description> 578 <bitOffset>0</bitOffset> 579 <bitWidth>1</bitWidth> 580 </field> 581 <field> 582 <name>TRANS_COMP</name> 583 <description>Transfer Complete.</description> 584 <bitOffset>1</bitOffset> 585 <bitWidth>1</bitWidth> 586 </field> 587 <field> 588 <name>BLK_GAP_EVENT</name> 589 <description>Block Gap Event.</description> 590 <bitOffset>2</bitOffset> 591 <bitWidth>1</bitWidth> 592 </field> 593 <field> 594 <name>DMA</name> 595 <description>DMA Interrupt.</description> 596 <bitOffset>3</bitOffset> 597 <bitWidth>1</bitWidth> 598 </field> 599 <field> 600 <name>BUFF_WR_READY</name> 601 <description>Buffer Write Ready.</description> 602 <bitOffset>4</bitOffset> 603 <bitWidth>1</bitWidth> 604 </field> 605 <field> 606 <name>BUFF_RD_READY</name> 607 <description>Buffer Read Ready.</description> 608 <bitOffset>5</bitOffset> 609 <bitWidth>1</bitWidth> 610 </field> 611 <field> 612 <name>CARD_INSERTION</name> 613 <description>Card Insertion.</description> 614 <bitOffset>6</bitOffset> 615 <bitWidth>1</bitWidth> 616 </field> 617 <field> 618 <name>CARD_REMOVAL</name> 619 <description>Card Removal.</description> 620 <bitOffset>7</bitOffset> 621 <bitWidth>1</bitWidth> 622 </field> 623 <field> 624 <name>CARD_INTR</name> 625 <description>Card Interrupt.</description> 626 <bitOffset>8</bitOffset> 627 <bitWidth>1</bitWidth> 628 </field> 629 <field> 630 <name>RETUNING</name> 631 <description>Re-Tuning Event.</description> 632 <bitOffset>12</bitOffset> 633 <bitWidth>1</bitWidth> 634 </field> 635 <field> 636 <name>ERR_INTR</name> 637 <description>Error Interrupt.</description> 638 <bitOffset>15</bitOffset> 639 <bitWidth>1</bitWidth> 640 </field> 641 </fields> 642 </register> 643 <register> 644 <name>ER_INT_STAT</name> 645 <description>Error Interrupt Status.</description> 646 <addressOffset>0x032</addressOffset> 647 <size>16</size> 648 <fields> 649 <field> 650 <name>CMD_TO</name> 651 <description>Command Timeout Error.</description> 652 <bitOffset>0</bitOffset> 653 <bitWidth>1</bitWidth> 654 </field> 655 <field> 656 <name>CMD_CRC</name> 657 <description>Command CRC Error.</description> 658 <bitOffset>1</bitOffset> 659 <bitWidth>1</bitWidth> 660 </field> 661 <field> 662 <name>CMD_END_BIT</name> 663 <description>Command End Bit Error.</description> 664 <bitOffset>2</bitOffset> 665 <bitWidth>1</bitWidth> 666 </field> 667 <field> 668 <name>CMD_IDX</name> 669 <description>Command Index Error.</description> 670 <bitOffset>3</bitOffset> 671 <bitWidth>1</bitWidth> 672 </field> 673 <field> 674 <name>DATA_TO</name> 675 <description>Data Timeout Error.</description> 676 <bitOffset>4</bitOffset> 677 <bitWidth>1</bitWidth> 678 </field> 679 <field> 680 <name>DATA_CRC</name> 681 <description>Data CRC Error.</description> 682 <bitOffset>5</bitOffset> 683 <bitWidth>1</bitWidth> 684 </field> 685 <field> 686 <name>DATA_END_BIT</name> 687 <description>Data End Bit Error.</description> 688 <bitOffset>6</bitOffset> 689 <bitWidth>1</bitWidth> 690 </field> 691 <field> 692 <name>CURRENT_LIMIT</name> 693 <description>Current Limit Error.</description> 694 <bitOffset>7</bitOffset> 695 <bitWidth>1</bitWidth> 696 </field> 697 <field> 698 <name>AUTO_CMD_12</name> 699 <description>Auto CMD Error.</description> 700 <bitOffset>8</bitOffset> 701 <bitWidth>1</bitWidth> 702 </field> 703 <field> 704 <name>ADMA</name> 705 <description>ADMA Error.</description> 706 <bitOffset>9</bitOffset> 707 <bitWidth>1</bitWidth> 708 </field> 709 <field> 710 <name>DMA</name> 711 <description>DMA Error.</description> 712 <bitOffset>12</bitOffset> 713 <bitWidth>1</bitWidth> 714 </field> 715 </fields> 716 </register> 717 <register> 718 <name>INT_EN</name> 719 <description>Normal Interrupt Status Enable.</description> 720 <addressOffset>0x034</addressOffset> 721 <size>16</size> 722 <fields> 723 <field> 724 <name>CMD_COMP</name> 725 <description>Command Complete Status Enable.</description> 726 <bitOffset>0</bitOffset> 727 <bitWidth>1</bitWidth> 728 </field> 729 <field> 730 <name>TRANS_COMP</name> 731 <description>Transfer Complete Status Enable.</description> 732 <bitOffset>1</bitOffset> 733 <bitWidth>1</bitWidth> 734 </field> 735 <field> 736 <name>BLK_GAP</name> 737 <description>Block Gap Event Status Enable.</description> 738 <bitOffset>2</bitOffset> 739 <bitWidth>1</bitWidth> 740 </field> 741 <field> 742 <name>DMA</name> 743 <description>DMA Interrupt Status Enable.</description> 744 <bitOffset>3</bitOffset> 745 <bitWidth>1</bitWidth> 746 </field> 747 <field> 748 <name>BUFFER_WR</name> 749 <description>Buffer Write Ready Status Enable.</description> 750 <bitOffset>4</bitOffset> 751 <bitWidth>1</bitWidth> 752 </field> 753 <field> 754 <name>BUFFER_RD</name> 755 <description>Buffer Read Ready Status Enable.</description> 756 <bitOffset>5</bitOffset> 757 <bitWidth>1</bitWidth> 758 </field> 759 <field> 760 <name>CARD_INSERT</name> 761 <description>Card Insertion Status Enable.</description> 762 <bitOffset>6</bitOffset> 763 <bitWidth>1</bitWidth> 764 </field> 765 <field> 766 <name>CARD_REMOVAL</name> 767 <description>Card Removal Status Enable.</description> 768 <bitOffset>7</bitOffset> 769 <bitWidth>1</bitWidth> 770 </field> 771 <field> 772 <name>CARD_INT</name> 773 <description>Card Interrupt Status Enable.</description> 774 <bitOffset>8</bitOffset> 775 <bitWidth>1</bitWidth> 776 </field> 777 <field> 778 <name>RETUNING</name> 779 <description>Re-Tuning Event Status Enable.</description> 780 <bitOffset>12</bitOffset> 781 <bitWidth>1</bitWidth> 782 </field> 783 </fields> 784 </register> 785 <register> 786 <name>ER_INT_EN</name> 787 <description>Error Interrupt Status Enable.</description> 788 <addressOffset>0x36</addressOffset> 789 <size>16</size> 790 <fields> 791 <field> 792 <name>CMD_TO</name> 793 <description>Command Timeout Error Status Enable.</description> 794 <bitOffset>0</bitOffset> 795 <bitWidth>1</bitWidth> 796 </field> 797 <field> 798 <name>CMD_CRC</name> 799 <description>Command CRC Error Status Enable.</description> 800 <bitOffset>1</bitOffset> 801 <bitWidth>1</bitWidth> 802 </field> 803 <field> 804 <name>CMD_END_BIT</name> 805 <description>Command End Bit Error Status Enable.</description> 806 <bitOffset>2</bitOffset> 807 <bitWidth>1</bitWidth> 808 </field> 809 <field> 810 <name>CMD_IDX</name> 811 <description>Command Index Error Status Enable.</description> 812 <bitOffset>3</bitOffset> 813 <bitWidth>1</bitWidth> 814 </field> 815 <field> 816 <name>DATA_TO</name> 817 <description>Data Timeout Error Status Enable.</description> 818 <bitOffset>4</bitOffset> 819 <bitWidth>1</bitWidth> 820 </field> 821 <field> 822 <name>DATA_CRC</name> 823 <description>Data CRC Error Status Enable.</description> 824 <bitOffset>5</bitOffset> 825 <bitWidth>1</bitWidth> 826 </field> 827 <field> 828 <name>DATA_END_BIT</name> 829 <description>Data End Bit Error Status Enable.</description> 830 <bitOffset>6</bitOffset> 831 <bitWidth>1</bitWidth> 832 </field> 833 <field> 834 <name>AUTO_CMD</name> 835 <description>Auto CMD Error Status Enable.</description> 836 <bitOffset>8</bitOffset> 837 <bitWidth>1</bitWidth> 838 </field> 839 <field> 840 <name>ADMA</name> 841 <description>ADMA Error Status Enable.</description> 842 <bitOffset>9</bitOffset> 843 <bitWidth>1</bitWidth> 844 </field> 845 <field> 846 <name>TUNING</name> 847 <description>Tuning Error Status Enable.</description> 848 <bitOffset>10</bitOffset> 849 <bitWidth>1</bitWidth> 850 </field> 851 <field> 852 <name>VENDOR</name> 853 <description>Vendor Specific Error Status Enable.</description> 854 <bitOffset>12</bitOffset> 855 <bitWidth>1</bitWidth> 856 </field> 857 </fields> 858 </register> 859 <register> 860 <name>INT_SIGNAL</name> 861 <description>Normal Interrupt Signal Enable.</description> 862 <addressOffset>0x038</addressOffset> 863 <size>16</size> 864 <fields> 865 <field> 866 <name>CMD_COMP</name> 867 <description>Command Complete Signal Enable.</description> 868 <bitOffset>0</bitOffset> 869 <bitWidth>1</bitWidth> 870 </field> 871 <field> 872 <name>TRANS_COMP</name> 873 <description>Transfer Complete Signal Enable.</description> 874 <bitOffset>1</bitOffset> 875 <bitWidth>1</bitWidth> 876 </field> 877 <field> 878 <name>BLK_GAP</name> 879 <description>Block Gap Event Signal Enable.</description> 880 <bitOffset>2</bitOffset> 881 <bitWidth>1</bitWidth> 882 </field> 883 <field> 884 <name>DMA</name> 885 <description>DMA Interrupt Signal Enable.</description> 886 <bitOffset>3</bitOffset> 887 <bitWidth>1</bitWidth> 888 </field> 889 <field> 890 <name>BUFFER_WR</name> 891 <description>Buffer Write Ready Signal Enable.</description> 892 <bitOffset>4</bitOffset> 893 <bitWidth>1</bitWidth> 894 </field> 895 <field> 896 <name>BUFFER_RD</name> 897 <description>Buffer Read Ready Signal Enable.</description> 898 <bitOffset>5</bitOffset> 899 <bitWidth>1</bitWidth> 900 </field> 901 <field> 902 <name>CARD_INSERT</name> 903 <description>Card Insertion Signal Enable.</description> 904 <bitOffset>6</bitOffset> 905 <bitWidth>1</bitWidth> 906 </field> 907 <field> 908 <name>CARD_REMOVAL</name> 909 <description>Card Removal Signal Enable.</description> 910 <bitOffset>7</bitOffset> 911 <bitWidth>1</bitWidth> 912 </field> 913 <field> 914 <name>CARD_INT</name> 915 <description>Card Interrupt Signal Enable.</description> 916 <bitOffset>8</bitOffset> 917 <bitWidth>1</bitWidth> 918 </field> 919 <field> 920 <name>RETUNING</name> 921 <description>Re-Tuning Event Signal Enable.</description> 922 <bitOffset>12</bitOffset> 923 <bitWidth>1</bitWidth> 924 </field> 925 </fields> 926 </register> 927 <register> 928 <name>ER_INT_SIGNAL</name> 929 <description>Error Interrupt Signal Enable.</description> 930 <addressOffset>0x03A</addressOffset> 931 <size>16</size> 932 <fields> 933 <field> 934 <name>CMD_TO</name> 935 <description>Command Timeout Error Signal Enable.</description> 936 <bitOffset>0</bitOffset> 937 <bitWidth>1</bitWidth> 938 </field> 939 <field> 940 <name>CMD_CRC</name> 941 <description>Command CRC Error Signal Enable.</description> 942 <bitOffset>1</bitOffset> 943 <bitWidth>1</bitWidth> 944 </field> 945 <field> 946 <name>CMD_END_BIT</name> 947 <description>Command End Bit Error Signal Enable.</description> 948 <bitOffset>2</bitOffset> 949 <bitWidth>1</bitWidth> 950 </field> 951 <field> 952 <name>CMD_IDX</name> 953 <description>Command Index Error Signal Enable.</description> 954 <bitOffset>3</bitOffset> 955 <bitWidth>1</bitWidth> 956 </field> 957 <field> 958 <name>DATA_TO</name> 959 <description>Data Timeout Error Signal Enable.</description> 960 <bitOffset>4</bitOffset> 961 <bitWidth>1</bitWidth> 962 </field> 963 <field> 964 <name>DATA_CRC</name> 965 <description>Data CRC Error Signal Enable.</description> 966 <bitOffset>5</bitOffset> 967 <bitWidth>1</bitWidth> 968 </field> 969 <field> 970 <name>DATA_END_BIT</name> 971 <description>Data End Bit Error Signal Enable.</description> 972 <bitOffset>6</bitOffset> 973 <bitWidth>1</bitWidth> 974 </field> 975 <field> 976 <name>CURR_LIM</name> 977 <description>Current Limit Error Signal Enable.</description> 978 <bitOffset>7</bitOffset> 979 <bitWidth>1</bitWidth> 980 </field> 981 <field> 982 <name>AUTO_CMD</name> 983 <description>Auto CMD Error Signal Enable.</description> 984 <bitOffset>8</bitOffset> 985 <bitWidth>1</bitWidth> 986 </field> 987 <field> 988 <name>ADMA</name> 989 <description>ADMA Error Signal Enable.</description> 990 <bitOffset>9</bitOffset> 991 <bitWidth>1</bitWidth> 992 </field> 993 <field> 994 <name>TUNING</name> 995 <description>Tuning Error Signal Enable.</description> 996 <bitOffset>10</bitOffset> 997 <bitWidth>1</bitWidth> 998 </field> 999 <field> 1000 <name>TAR_RESP</name> 1001 <description>Target Response Error Signal Enable.</description> 1002 <bitOffset>12</bitOffset> 1003 <bitWidth>1</bitWidth> 1004 </field> 1005 </fields> 1006 </register> 1007 <register> 1008 <name>AUTO_CMD_ER</name> 1009 <description>Auto CMD Error Status.</description> 1010 <addressOffset>0x03C</addressOffset> 1011 <size>16</size> 1012 <fields> 1013 <field> 1014 <name>NOT_EXCUTED</name> 1015 <description>Auto CMD12 Not Executed.</description> 1016 <bitOffset>0</bitOffset> 1017 <bitWidth>1</bitWidth> 1018 </field> 1019 <field> 1020 <name>TO</name> 1021 <description>Auto CMD Timeout Error.</description> 1022 <bitOffset>1</bitOffset> 1023 <bitWidth>1</bitWidth> 1024 </field> 1025 <field> 1026 <name>CRC</name> 1027 <description>Auto CMD CRC Error.</description> 1028 <bitOffset>2</bitOffset> 1029 <bitWidth>1</bitWidth> 1030 </field> 1031 <field> 1032 <name>END_BIT</name> 1033 <description>Auto CMD End Bit Error.</description> 1034 <bitOffset>3</bitOffset> 1035 <bitWidth>1</bitWidth> 1036 </field> 1037 <field> 1038 <name>INDEX</name> 1039 <description>Auto CMD Index Error.</description> 1040 <bitOffset>4</bitOffset> 1041 <bitWidth>1</bitWidth> 1042 </field> 1043 <field> 1044 <name>NOT_ISSUED</name> 1045 <description>Command Not Issued By Auto CMD12 Error.</description> 1046 <bitOffset>7</bitOffset> 1047 <bitWidth>1</bitWidth> 1048 </field> 1049 </fields> 1050 </register> 1051 <register> 1052 <name>HOST_CN_2</name> 1053 <description>Host Control 2.</description> 1054 <addressOffset>0x03E</addressOffset> 1055 <size>16</size> 1056 <fields> 1057 <field> 1058 <name>UHS</name> 1059 <description>UHS Mode Select.</description> 1060 <bitOffset>0</bitOffset> 1061 <bitWidth>2</bitWidth> 1062 </field> 1063 <field> 1064 <name>SIGNAL_V1_8</name> 1065 <description>1.8V Signaling Enable.</description> 1066 <bitOffset>3</bitOffset> 1067 <bitWidth>1</bitWidth> 1068 </field> 1069 <field> 1070 <name>DRIVER_STRENGTH</name> 1071 <description>Driver Strength Select.</description> 1072 <bitOffset>4</bitOffset> 1073 <bitWidth>2</bitWidth> 1074 </field> 1075 <field> 1076 <name>EXCUTE</name> 1077 <description>Execute Tuning.</description> 1078 <bitOffset>6</bitOffset> 1079 <bitWidth>1</bitWidth> 1080 </field> 1081 <field> 1082 <name>SAMPLING_CLK</name> 1083 <description>Sampling Clock Select.</description> 1084 <bitOffset>7</bitOffset> 1085 <bitWidth>1</bitWidth> 1086 </field> 1087 <field> 1088 <name>ASYNCH_INT</name> 1089 <description>Asynchronous Interrupt Enable.</description> 1090 <bitOffset>14</bitOffset> 1091 <bitWidth>1</bitWidth> 1092 </field> 1093 <field> 1094 <name>PRESET_VAL_EN</name> 1095 <description>Preset Value Enable.</description> 1096 <bitOffset>15</bitOffset> 1097 <bitWidth>1</bitWidth> 1098 </field> 1099 </fields> 1100 </register> 1101 <register> 1102 <name>CFG_0</name> 1103 <description>Capabilities 0-31.</description> 1104 <addressOffset>0x040</addressOffset> 1105 <size>32</size> 1106 <access>read-only</access> 1107 <fields> 1108 <field> 1109 <name>CLK_FREQ</name> 1110 <description>Timeout Clock Frequency.</description> 1111 <bitOffset>0</bitOffset> 1112 <bitWidth>6</bitWidth> 1113 <access>read-only</access> 1114 </field> 1115 <field> 1116 <name>TO_CLK_UNIT</name> 1117 <description>Timeout Clock Unit.</description> 1118 <bitOffset>7</bitOffset> 1119 <bitWidth>1</bitWidth> 1120 <access>read-only</access> 1121 </field> 1122 <field> 1123 <name>TO_CLK_FREQ</name> 1124 <description>Base Clock Frequency For SD Clock.</description> 1125 <bitOffset>8</bitOffset> 1126 <bitWidth>8</bitWidth> 1127 <access>read-only</access> 1128 </field> 1129 <field> 1130 <name>MAX_BLK_LEN</name> 1131 <description>Max Block Length.</description> 1132 <bitOffset>16</bitOffset> 1133 <bitWidth>2</bitWidth> 1134 <access>read-only</access> 1135 </field> 1136 <field> 1137 <name>BIT_8</name> 1138 <description>8-bit Support for Embedded Device.</description> 1139 <bitOffset>18</bitOffset> 1140 <bitWidth>1</bitWidth> 1141 <access>read-only</access> 1142 </field> 1143 <field> 1144 <name>ADMA2</name> 1145 <description>ADMA2 Support.</description> 1146 <bitOffset>19</bitOffset> 1147 <bitWidth>1</bitWidth> 1148 <access>read-only</access> 1149 </field> 1150 <field> 1151 <name>HS</name> 1152 <description>High Speed Support.</description> 1153 <bitOffset>21</bitOffset> 1154 <bitWidth>1</bitWidth> 1155 <access>read-only</access> 1156 </field> 1157 <field> 1158 <name>SDMA</name> 1159 <description>SDMA Support.</description> 1160 <bitOffset>22</bitOffset> 1161 <bitWidth>1</bitWidth> 1162 <access>read-only</access> 1163 </field> 1164 <field> 1165 <name>SUSPEND</name> 1166 <description>Suspend/Resume Support.</description> 1167 <bitOffset>23</bitOffset> 1168 <bitWidth>1</bitWidth> 1169 <access>read-only</access> 1170 </field> 1171 <field> 1172 <name>V3_3</name> 1173 <description>Voltage Support 3.3V.</description> 1174 <bitOffset>24</bitOffset> 1175 <bitWidth>1</bitWidth> 1176 <access>read-only</access> 1177 </field> 1178 <field> 1179 <name>V3_0</name> 1180 <description>Voltage Support 3.0V.</description> 1181 <bitOffset>25</bitOffset> 1182 <bitWidth>1</bitWidth> 1183 <access>read-only</access> 1184 </field> 1185 <field> 1186 <name>V1_8</name> 1187 <description>Voltage Support 1.8V.</description> 1188 <bitOffset>26</bitOffset> 1189 <bitWidth>1</bitWidth> 1190 <access>read-only</access> 1191 </field> 1192 <field> 1193 <name>BIT_64_SYS_BUS</name> 1194 <description>64-bit System Bus Support.</description> 1195 <bitOffset>28</bitOffset> 1196 <bitWidth>1</bitWidth> 1197 <access>read-only</access> 1198 </field> 1199 <field> 1200 <name>ASYNC_INT</name> 1201 <description>Asynchronous Interrupt Support.</description> 1202 <bitOffset>29</bitOffset> 1203 <bitWidth>1</bitWidth> 1204 <access>read-only</access> 1205 </field> 1206 <field> 1207 <name>SLOT_TYPE</name> 1208 <description>Slot Type.</description> 1209 <bitOffset>30</bitOffset> 1210 <bitWidth>2</bitWidth> 1211 <access>read-only</access> 1212 </field> 1213 </fields> 1214 </register> 1215 <register> 1216 <name>CFG_1</name> 1217 <description>Capabilities 32-63.</description> 1218 <addressOffset>0x044</addressOffset> 1219 <size>32</size> 1220 <access>read-only</access> 1221 <fields> 1222 <field> 1223 <name>SDR50</name> 1224 <description>SDR50 Support.</description> 1225 <bitOffset>0</bitOffset> 1226 <bitWidth>1</bitWidth> 1227 <access>read-only</access> 1228 </field> 1229 <field> 1230 <name>SDR104</name> 1231 <description>SDR104 Support.</description> 1232 <bitOffset>1</bitOffset> 1233 <bitWidth>0</bitWidth> 1234 <access>read-only</access> 1235 </field> 1236 <field> 1237 <name>DDR50</name> 1238 <description>DDR50 Support.</description> 1239 <bitOffset>2</bitOffset> 1240 <bitWidth>1</bitWidth> 1241 <access>read-only</access> 1242 </field> 1243 <field> 1244 <name>DRIVER_A</name> 1245 <description>Driver Type A Support.</description> 1246 <bitOffset>4</bitOffset> 1247 <bitWidth>1</bitWidth> 1248 <access>read-only</access> 1249 </field> 1250 <field> 1251 <name>DRIVER_C</name> 1252 <description>Driver Type C Support.</description> 1253 <bitOffset>5</bitOffset> 1254 <bitWidth>1</bitWidth> 1255 <access>read-only</access> 1256 </field> 1257 <field> 1258 <name>DRIVER_D</name> 1259 <description>Driver Type D Support.</description> 1260 <bitOffset>6</bitOffset> 1261 <bitWidth>1</bitWidth> 1262 <access>read-only</access> 1263 </field> 1264 <field> 1265 <name>TIMER_CNT_TUNING</name> 1266 <description>Timer Count for Re-Tuning.</description> 1267 <bitOffset>8</bitOffset> 1268 <bitWidth>4</bitWidth> 1269 <access>read-only</access> 1270 </field> 1271 <field> 1272 <name>TUNING_SDR50</name> 1273 <description>Use Tuning for SDR50.</description> 1274 <bitOffset>13</bitOffset> 1275 <bitWidth>1</bitWidth> 1276 <access>read-only</access> 1277 </field> 1278 <field> 1279 <name>RETUNING</name> 1280 <description>Re-Tuning Modes.</description> 1281 <bitOffset>14</bitOffset> 1282 <bitWidth>2</bitWidth> 1283 <access>read-only</access> 1284 </field> 1285 <field> 1286 <name>CLK_MULTI</name> 1287 <description>Clock Multiplier.</description> 1288 <bitOffset>16</bitOffset> 1289 <bitWidth>8</bitWidth> 1290 <access>read-only</access> 1291 </field> 1292 </fields> 1293 </register> 1294 <register> 1295 <name>MAX_CURR_CFG</name> 1296 <description>Maximum Current Capabilities.</description> 1297 <addressOffset>0x048</addressOffset> 1298 <size>32</size> 1299 <access>read-only</access> 1300 <fields> 1301 <field> 1302 <name>V3_3</name> 1303 <description>Maximum Current for 3.3V.</description> 1304 <bitOffset>0</bitOffset> 1305 <bitWidth>8</bitWidth> 1306 <access>read-only</access> 1307 </field> 1308 <field> 1309 <name>V3_0</name> 1310 <description>Maximum Current for 3.0V.</description> 1311 <bitOffset>8</bitOffset> 1312 <bitWidth>8</bitWidth> 1313 <access>read-only</access> 1314 </field> 1315 <field> 1316 <name>V1_8</name> 1317 <description>Maximum Current for 1.8V.</description> 1318 <bitOffset>16</bitOffset> 1319 <bitWidth>8</bitWidth> 1320 <access>read-only</access> 1321 </field> 1322 </fields> 1323 </register> 1324 <register> 1325 <name>FORCE_CMD</name> 1326 <description>Force Event for Auto CMD Error Status.</description> 1327 <addressOffset>0x050</addressOffset> 1328 <size>16</size> 1329 <access>write-only</access> 1330 <fields> 1331 <field> 1332 <name>NOT_EXCU</name> 1333 <description>Force Event for Auto CMD12 Not Executed.</description> 1334 <bitOffset>0</bitOffset> 1335 <bitWidth>1</bitWidth> 1336 <access>write-only</access> 1337 </field> 1338 <field> 1339 <name>TO</name> 1340 <description>Force Event for Auto CMD Timeout Error.</description> 1341 <bitOffset>1</bitOffset> 1342 <bitWidth>1</bitWidth> 1343 <access>write-only</access> 1344 </field> 1345 <field> 1346 <name>CRC</name> 1347 <description>Force Event for Auto CMD CRC Error.</description> 1348 <bitOffset>2</bitOffset> 1349 <bitWidth>1</bitWidth> 1350 <access>write-only</access> 1351 </field> 1352 <field> 1353 <name>END_BIT</name> 1354 <description>Force Event for Auto CMD End Bit Error.</description> 1355 <bitOffset>3</bitOffset> 1356 <bitWidth>1</bitWidth> 1357 <access>write-only</access> 1358 </field> 1359 <field> 1360 <name>INDEX</name> 1361 <description>Force Event for Auto CMD Index Error.</description> 1362 <bitOffset>4</bitOffset> 1363 <bitWidth>1</bitWidth> 1364 <access>write-only</access> 1365 </field> 1366 <field> 1367 <name>NOT_ISSUED</name> 1368 <description>Force Event for Command Not Issued By Auto CMD12 Error.</description> 1369 <bitOffset>7</bitOffset> 1370 <bitWidth>1</bitWidth> 1371 <access>write-only</access> 1372 </field> 1373 </fields> 1374 </register> 1375 <register> 1376 <name>FORCE_EVENT_INT_STAT</name> 1377 <description>Force Event for Error Interrupt Status.</description> 1378 <addressOffset>0x052</addressOffset> 1379 <size>16</size> 1380 <fields> 1381 <field> 1382 <name>CMD_TO</name> 1383 <description>Force Event for Command Timeout Error.</description> 1384 <bitOffset>0</bitOffset> 1385 <bitWidth>1</bitWidth> 1386 <access>read-only</access> 1387 </field> 1388 <field> 1389 <name>CMD_CRC</name> 1390 <description>Force Event for Command CRC Error.</description> 1391 <bitOffset>1</bitOffset> 1392 <bitWidth>1</bitWidth> 1393 <access>read-only</access> 1394 </field> 1395 <field> 1396 <name>CMD_END_BIT</name> 1397 <description>Force Event for Command End Bit Error.</description> 1398 <bitOffset>2</bitOffset> 1399 <bitWidth>1</bitWidth> 1400 <access>read-only</access> 1401 </field> 1402 <field> 1403 <name>CMD_INDEX</name> 1404 <description>Force Event for Command Index Error.</description> 1405 <bitOffset>3</bitOffset> 1406 <bitWidth>1</bitWidth> 1407 <access>read-only</access> 1408 </field> 1409 <field> 1410 <name>DATA_TO</name> 1411 <description>Force Event for Data Timeout Error.</description> 1412 <bitOffset>4</bitOffset> 1413 <bitWidth>1</bitWidth> 1414 <access>read-only</access> 1415 </field> 1416 <field> 1417 <name>DATA_CRC</name> 1418 <description>Force Event for Data CRC Error.</description> 1419 <bitOffset>5</bitOffset> 1420 <bitWidth>1</bitWidth> 1421 <access>read-only</access> 1422 </field> 1423 <field> 1424 <name>DATA_END_BIT</name> 1425 <description>Force Event for Data End Bit Error.</description> 1426 <bitOffset>6</bitOffset> 1427 <bitWidth>1</bitWidth> 1428 <access>read-only</access> 1429 </field> 1430 <field> 1431 <name>CURR_LIMIT</name> 1432 <description>Force Event for Current Limit Error.</description> 1433 <bitOffset>7</bitOffset> 1434 <bitWidth>1</bitWidth> 1435 <access>read-only</access> 1436 </field> 1437 <field> 1438 <name>AUTO_CMD</name> 1439 <description>Force Event for Auto CMD Error.</description> 1440 <bitOffset>8</bitOffset> 1441 <bitWidth>1</bitWidth> 1442 <access>read-only</access> 1443 </field> 1444 <field> 1445 <name>ADMA</name> 1446 <description>Force Event for ADMA Error.</description> 1447 <bitOffset>9</bitOffset> 1448 <bitWidth>1</bitWidth> 1449 </field> 1450 <field> 1451 <name>VENDOR</name> 1452 <description>Force Event for Vendor Specific Error Status.</description> 1453 <bitOffset>12</bitOffset> 1454 <bitWidth>3</bitWidth> 1455 <access>write-only</access> 1456 </field> 1457 </fields> 1458 </register> 1459 <register> 1460 <name>ADMA_ER</name> 1461 <description>ADMA Error Status.</description> 1462 <addressOffset>0x054</addressOffset> 1463 <size>8</size> 1464 <fields> 1465 <field> 1466 <name>STATE</name> 1467 <description>ADMA Error State.</description> 1468 <bitOffset>0</bitOffset> 1469 <bitWidth>2</bitWidth> 1470 </field> 1471 <field> 1472 <name>LEN_MISMATCH</name> 1473 <description>ADMA Length Mismatch Error.</description> 1474 <bitOffset>2</bitOffset> 1475 <bitWidth>1</bitWidth> 1476 </field> 1477 </fields> 1478 </register> 1479 <register> 1480 <name>ADMA_ADDR_0</name> 1481 <description>ADMA System Address 0-31.</description> 1482 <addressOffset>0x058</addressOffset> 1483 <size>32</size> 1484 <fields> 1485 <field> 1486 <name>ADDR</name> 1487 <description>ADMA System Address Part 1 (part 2 is ADMA_ADDR_1).</description> 1488 <bitOffset>0</bitOffset> 1489 <bitWidth>32</bitWidth> 1490 </field> 1491 </fields> 1492 </register> 1493 <register> 1494 <name>ADMA_ADDR_1</name> 1495 <description>ADMA System Address 32-63.</description> 1496 <addressOffset>0x05C</addressOffset> 1497 <size>32</size> 1498 <fields> 1499 <field> 1500 <name>ADDR</name> 1501 <description>ADMA System Address Part 1 (part 2 is ADMA_ADDR_1).</description> 1502 <bitOffset>0</bitOffset> 1503 <bitWidth>32</bitWidth> 1504 </field> 1505 </fields> 1506 </register> 1507 <register> 1508 <name>PRESET_0</name> 1509 <description>Preset Value for Initialization.</description> 1510 <addressOffset>0x060</addressOffset> 1511 <size>16</size> 1512 <access>read-only</access> 1513 <fields> 1514 <field> 1515 <name>SDCLK_FREQ</name> 1516 <description>SDCLK Frequency Select Value.</description> 1517 <bitOffset>0</bitOffset> 1518 <bitWidth>10</bitWidth> 1519 <access>read-only</access> 1520 </field> 1521 <field> 1522 <name>CLK_GEN</name> 1523 <description>Clock Generator Select Value.</description> 1524 <bitOffset>10</bitOffset> 1525 <bitWidth>1</bitWidth> 1526 <access>read-only</access> 1527 </field> 1528 <field> 1529 <name>DRIVER_STRENGTH</name> 1530 <description>Driver Strength Select Value.</description> 1531 <bitOffset>14</bitOffset> 1532 <bitWidth>2</bitWidth> 1533 <access>read-only</access> 1534 </field> 1535 </fields> 1536 </register> 1537 <register> 1538 <name>PRESET_1</name> 1539 <description>Preset Value for Default Speed.</description> 1540 <addressOffset>0x062</addressOffset> 1541 <size>16</size> 1542 <access>read-only</access> 1543 <fields> 1544 <field> 1545 <name>SDCLK_FREQ</name> 1546 <description>SDCLK Frequency Select Value.</description> 1547 <bitOffset>0</bitOffset> 1548 <bitWidth>10</bitWidth> 1549 <access>read-only</access> 1550 </field> 1551 <field> 1552 <name>CLK_GEN</name> 1553 <description>Clock Generator Select Value.</description> 1554 <bitOffset>10</bitOffset> 1555 <bitWidth>1</bitWidth> 1556 <access>read-only</access> 1557 </field> 1558 <field> 1559 <name>DRIVER_STRENGTH</name> 1560 <description>Driver Strength Select Value.</description> 1561 <bitOffset>14</bitOffset> 1562 <bitWidth>2</bitWidth> 1563 <access>read-only</access> 1564 </field> 1565 </fields> 1566 </register> 1567 <register> 1568 <name>PRESET_2</name> 1569 <description>Preset Value for High Speed.</description> 1570 <addressOffset>0x064</addressOffset> 1571 <size>16</size> 1572 <access>read-only</access> 1573 <fields> 1574 <field> 1575 <name>SDCLK_FREQ</name> 1576 <description>SDCLK Frequency Select Value.</description> 1577 <bitOffset>0</bitOffset> 1578 <bitWidth>10</bitWidth> 1579 <access>read-only</access> 1580 </field> 1581 <field> 1582 <name>CLK_GEN</name> 1583 <description>Clock Generator Select Value.</description> 1584 <bitOffset>10</bitOffset> 1585 <bitWidth>1</bitWidth> 1586 <access>read-only</access> 1587 </field> 1588 <field> 1589 <name>DRIVER_STRENGTH</name> 1590 <description>Driver Strength Select Value.</description> 1591 <bitOffset>14</bitOffset> 1592 <bitWidth>2</bitWidth> 1593 <access>read-only</access> 1594 </field> 1595 </fields> 1596 </register> 1597 <register> 1598 <name>PRESET_3</name> 1599 <description>Preset Value for SDR12.</description> 1600 <addressOffset>0x066</addressOffset> 1601 <size>16</size> 1602 <access>read-only</access> 1603 <fields> 1604 <field> 1605 <name>SDCLK_FREQ</name> 1606 <description>SDCLK Frequency Select Value.</description> 1607 <bitOffset>0</bitOffset> 1608 <bitWidth>10</bitWidth> 1609 <access>read-only</access> 1610 </field> 1611 <field> 1612 <name>CLK_GEN</name> 1613 <description>Clock Generator Select Value.</description> 1614 <bitOffset>10</bitOffset> 1615 <bitWidth>1</bitWidth> 1616 <access>read-only</access> 1617 </field> 1618 <field> 1619 <name>DRIVER_STRENGTH</name> 1620 <description>Driver Strength Select Value.</description> 1621 <bitOffset>14</bitOffset> 1622 <bitWidth>2</bitWidth> 1623 <access>read-only</access> 1624 </field> 1625 </fields> 1626 </register> 1627 <register> 1628 <name>PRESET_4</name> 1629 <description>Preset Value for SDR25.</description> 1630 <addressOffset>0x068</addressOffset> 1631 <size>16</size> 1632 <access>read-only</access> 1633 <fields> 1634 <field> 1635 <name>SDCLK_FREQ</name> 1636 <description>SDCLK Frequency Select Value.</description> 1637 <bitOffset>0</bitOffset> 1638 <bitWidth>10</bitWidth> 1639 <access>read-only</access> 1640 </field> 1641 <field> 1642 <name>CLK_GEN</name> 1643 <description>Clock Generator Select Value.</description> 1644 <bitOffset>10</bitOffset> 1645 <bitWidth>1</bitWidth> 1646 <access>read-only</access> 1647 </field> 1648 <field> 1649 <name>DRIVER_STRENGTH</name> 1650 <description>Driver Strength Select Value.</description> 1651 <bitOffset>14</bitOffset> 1652 <bitWidth>2</bitWidth> 1653 <access>read-only</access> 1654 </field> 1655 </fields> 1656 </register> 1657 <register> 1658 <name>PRESET_5</name> 1659 <description>Preset Value for SDR50.</description> 1660 <addressOffset>0x06A</addressOffset> 1661 <size>16</size> 1662 <access>read-only</access> 1663 <fields> 1664 <field> 1665 <name>SDCLK_FREQ</name> 1666 <description>SDCLK Frequency Select Value.</description> 1667 <bitOffset>0</bitOffset> 1668 <bitWidth>10</bitWidth> 1669 <access>read-only</access> 1670 </field> 1671 <field> 1672 <name>CLK_GEN</name> 1673 <description>Clock Generator Select Value.</description> 1674 <bitOffset>10</bitOffset> 1675 <bitWidth>1</bitWidth> 1676 <access>read-only</access> 1677 </field> 1678 <field> 1679 <name>DRIVER_STRENGTH</name> 1680 <description>Driver Strength Select Value.</description> 1681 <bitOffset>14</bitOffset> 1682 <bitWidth>2</bitWidth> 1683 <access>read-only</access> 1684 </field> 1685 </fields> 1686 </register> 1687 <register> 1688 <name>PRESET_6</name> 1689 <description>Preset Value for SDR104.</description> 1690 <addressOffset>0x06C</addressOffset> 1691 <size>16</size> 1692 <access>read-only</access> 1693 <fields> 1694 <field> 1695 <name>SDCLK_FREQ</name> 1696 <description>SDCLK Frequency Select Value.</description> 1697 <bitOffset>0</bitOffset> 1698 <bitWidth>10</bitWidth> 1699 <access>read-only</access> 1700 </field> 1701 <field> 1702 <name>CLK_GEN</name> 1703 <description>Clock Generator Select Value.</description> 1704 <bitOffset>10</bitOffset> 1705 <bitWidth>1</bitWidth> 1706 <access>read-only</access> 1707 </field> 1708 <field> 1709 <name>DRIVER_STRENGTH</name> 1710 <description>Driver Strength Select Value.</description> 1711 <bitOffset>14</bitOffset> 1712 <bitWidth>2</bitWidth> 1713 <access>read-only</access> 1714 </field> 1715 </fields> 1716 </register> 1717 <register> 1718 <name>PRESET_7</name> 1719 <description>Preset Value for DDR50.</description> 1720 <addressOffset>0x06E</addressOffset> 1721 <size>16</size> 1722 <access>read-only</access> 1723 <fields> 1724 <field> 1725 <name>SDCLK_FREQ</name> 1726 <description>SDCLK Frequency Select Value.</description> 1727 <bitOffset>0</bitOffset> 1728 <bitWidth>10</bitWidth> 1729 <access>read-only</access> 1730 </field> 1731 <field> 1732 <name>CLK_GEN</name> 1733 <description>Clock Generator Select Value.</description> 1734 <bitOffset>10</bitOffset> 1735 <bitWidth>1</bitWidth> 1736 <access>read-only</access> 1737 </field> 1738 <field> 1739 <name>DRIVER_STRENGTH</name> 1740 <description>Driver Strength Select Value.</description> 1741 <bitOffset>14</bitOffset> 1742 <bitWidth>2</bitWidth> 1743 <access>read-only</access> 1744 </field> 1745 </fields> 1746 </register> 1747 <register> 1748 <name>SLOT_INT</name> 1749 <description>Slot Interrupt Status.</description> 1750 <addressOffset>0x0FC</addressOffset> 1751 <size>16</size> 1752 <access>read-only</access> 1753 <fields> 1754 <field> 1755 <name>INT_SIGNALS</name> 1756 <description>Interrupt Signal For Each Slot.</description> 1757 <bitOffset>0</bitOffset> 1758 <bitWidth>1</bitWidth> 1759 <access>read-only</access> 1760 </field> 1761 </fields> 1762 </register> 1763 <register> 1764 <name>HOST_CN_VER</name> 1765 <description>Host Controller Version.</description> 1766 <addressOffset>0x0FE</addressOffset> 1767 <size>16</size> 1768 <fields> 1769 <field> 1770 <name>SPEC_VER</name> 1771 <description>Specification Version Number.</description> 1772 <bitOffset>0</bitOffset> 1773 <bitWidth>8</bitWidth> 1774 </field> 1775 <field> 1776 <name>VEND_VER</name> 1777 <description>Vendor Version Number.</description> 1778 <bitOffset>8</bitOffset> 1779 <bitWidth>8</bitWidth> 1780 </field> 1781 </fields> 1782 </register> 1783 </registers> 1784 </peripheral> 1785 <!-- SDHC: SD Card Controller --> 1786</device>
