1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SCN</name> 5 <description>Smart Card Interface.</description> 6 <groupName>SCN</groupName> 7 <baseAddress>0x4002C000</baseAddress> 8 <addressBlock> 9 <offset>0x00</offset> 10 <size>0x1000</size> 11 <usage>registers</usage> 12 </addressBlock> 13 <interrupt> 14 <name>SC0</name> 15 <description>SC0 IRQ</description> 16 <value>11</value> 17 </interrupt> 18 <registers> 19 <register> 20 <name>CR</name> 21 <description>Control Register.</description> 22 <addressOffset>0x00</addressOffset> 23 <fields> 24 <field> 25 <name>CONV</name> 26 <description>Convention Select Bit.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>1</bitWidth> 29 </field> 30 <field> 31 <name>CREP</name> 32 <description>Character Repeat Enable Bit.</description> 33 <bitOffset>1</bitOffset> 34 <bitWidth>1</bitWidth> 35 </field> 36 <field> 37 <name>WTEN</name> 38 <description>Wait Time Counter Enable Bit.</description> 39 <bitOffset>2</bitOffset> 40 <bitWidth>1</bitWidth> 41 </field> 42 <field> 43 <name>UART</name> 44 <description>Smart Card Mode Bit.</description> 45 <bitOffset>3</bitOffset> 46 <bitWidth>1</bitWidth> 47 </field> 48 <field> 49 <name>CCEN</name> 50 <description>Clock Counter Enable Bit.</description> 51 <bitOffset>4</bitOffset> 52 <bitWidth>1</bitWidth> 53 </field> 54 <field> 55 <name>RXFLUSH</name> 56 <description>Receive FIFO Flush.</description> 57 <bitOffset>5</bitOffset> 58 <bitWidth>1</bitWidth> 59 </field> 60 <field> 61 <name>TXFLUSH</name> 62 <description>Transmit FIFO Flush.</description> 63 <bitOffset>6</bitOffset> 64 <bitWidth>1</bitWidth> 65 </field> 66 <field> 67 <name>RXTHD</name> 68 <description>Receive FIFO Depth.</description> 69 <bitOffset>8</bitOffset> 70 <bitWidth>4</bitWidth> 71 </field> 72 <field> 73 <name>TXTHD</name> 74 <description>Transmit FIFO Depth.</description> 75 <bitOffset>12</bitOffset> 76 <bitWidth>4</bitWidth> 77 </field> 78 </fields> 79 </register> 80 <register> 81 <name>SR</name> 82 <description>Status Register.</description> 83 <addressOffset>0x04</addressOffset> 84 <fields> 85 <field> 86 <name>PAR</name> 87 <description>Parity Error Detector Flag.</description> 88 <bitOffset>0</bitOffset> 89 <bitWidth>1</bitWidth> 90 </field> 91 <field> 92 <name>WTOV</name> 93 <description>Waiting Time Counter Overflow.</description> 94 <bitOffset>1</bitOffset> 95 <bitWidth>1</bitWidth> 96 </field> 97 <field> 98 <name>CCOV</name> 99 <description>Clock Counter Overflow Flag.</description> 100 <bitOffset>2</bitOffset> 101 <bitWidth>1</bitWidth> 102 </field> 103 <field> 104 <name>TXCF</name> 105 <description>Transmit Complete Flag.</description> 106 <bitOffset>3</bitOffset> 107 <bitWidth>1</bitWidth> 108 </field> 109 <field> 110 <name>RXEMPTY</name> 111 <description>Receive FIFO Empty Flag.</description> 112 <bitOffset>4</bitOffset> 113 <bitWidth>1</bitWidth> 114 </field> 115 <field> 116 <name>RXFULL</name> 117 <description>Receive FIFO Full Flag.</description> 118 <bitOffset>5</bitOffset> 119 <bitWidth>1</bitWidth> 120 </field> 121 <field> 122 <name>TXEMPTY</name> 123 <description>Transmit FIFO Empty Flag.</description> 124 <bitOffset>6</bitOffset> 125 <bitWidth>1</bitWidth> 126 </field> 127 <field> 128 <name>TXFULL</name> 129 <description>Transmit FIFO Full Flag.</description> 130 <bitOffset>7</bitOffset> 131 <bitWidth>1</bitWidth> 132 </field> 133 <field> 134 <name>RXELT</name> 135 <description>Number of Bytes in the Receive FIFO.</description> 136 <bitOffset>8</bitOffset> 137 <bitWidth>4</bitWidth> 138 </field> 139 <field> 140 <name>TXELT</name> 141 <description>Number of Bytes in the Transmit FIFO.</description> 142 <bitOffset>12</bitOffset> 143 <bitWidth>4</bitWidth> 144 </field> 145 </fields> 146 </register> 147 <register> 148 <name>PN</name> 149 <description>Pin Register,</description> 150 <addressOffset>0x08</addressOffset> 151 <fields> 152 <field> 153 <name>CRDRST</name> 154 <description>Smart Card Reset Pin Control.</description> 155 <bitOffset>0</bitOffset> 156 <bitWidth>1</bitWidth> 157 </field> 158 <field> 159 <name>CRDCLK</name> 160 <description>Smart Card Clock Piin Control.</description> 161 <bitOffset>1</bitOffset> 162 <bitWidth>1</bitWidth> 163 </field> 164 <field> 165 <name>CRDIO</name> 166 <description>Smart Card IO Pin Control.</description> 167 <bitOffset>2</bitOffset> 168 <bitWidth>1</bitWidth> 169 </field> 170 <field> 171 <name>CRDC4</name> 172 <description>Smart Card SCn_C4 Pin Control.</description> 173 <bitOffset>3</bitOffset> 174 <bitWidth>1</bitWidth> 175 </field> 176 <field> 177 <name>CRDC8</name> 178 <description>Smart Card SCn_C8 Pin Control.</description> 179 <bitOffset>4</bitOffset> 180 <bitWidth>1</bitWidth> 181 </field> 182 <field> 183 <name>CLKSEL</name> 184 <description>Smart Card Clock Select.</description> 185 <bitOffset>5</bitOffset> 186 <bitWidth>1</bitWidth> 187 </field> 188 </fields> 189 </register> 190 <register> 191 <name>ETUR</name> 192 <description>ETU Register.</description> 193 <addressOffset>0x0C</addressOffset> 194 <fields> 195 <field> 196 <name>ETU</name> 197 <description>Elemental Time Unit Value.</description> 198 <bitOffset>0</bitOffset> 199 <bitWidth>15</bitWidth> 200 </field> 201 <field> 202 <name>COMP</name> 203 <description>Compensation Mode Enable Bit.</description> 204 <bitOffset>15</bitOffset> 205 <bitWidth>1</bitWidth> 206 </field> 207 <field> 208 <name>HALF</name> 209 <description>Half ETU Count Selection Bit.</description> 210 <bitOffset>16</bitOffset> 211 <bitWidth>1</bitWidth> 212 </field> 213 </fields> 214 </register> 215 <register> 216 <name>GTR</name> 217 <description>Guard Time Register.</description> 218 <addressOffset>0x10</addressOffset> 219 <fields> 220 <field> 221 <name>GT</name> 222 <description>Guard Time.</description> 223 <bitOffset>0</bitOffset> 224 <bitWidth>16</bitWidth> 225 </field> 226 </fields> 227 </register> 228 <register> 229 <name>WT0R</name> 230 <description>Waiting Time 0 Register.</description> 231 <addressOffset>0x14</addressOffset> 232 <fields> 233 <field> 234 <name>WT</name> 235 <description>Wait Time.</description> 236 <bitOffset>0</bitOffset> 237 <bitWidth>32</bitWidth> 238 </field> 239 </fields> 240 </register> 241 <register> 242 <name>WT1R</name> 243 <description>Waiting Time 1 Register.</description> 244 <addressOffset>0x18</addressOffset> 245 <fields> 246 <field> 247 <name>WT</name> 248 <description>Wait Time.</description> 249 <bitOffset>0</bitOffset> 250 <bitWidth>8</bitWidth> 251 </field> 252 </fields> 253 </register> 254 <register> 255 <name>IER</name> 256 <description>Interrupt Enable Register.</description> 257 <addressOffset>0x1C</addressOffset> 258 <fields> 259 <field> 260 <name>PARIE</name> 261 <description>Parity Error Interrupt Enable.</description> 262 <bitOffset>0</bitOffset> 263 <bitWidth>1</bitWidth> 264 </field> 265 <field> 266 <name>WTIE</name> 267 <description>Waiting Time Overflow Interrupt Enable.</description> 268 <bitOffset>1</bitOffset> 269 <bitWidth>1</bitWidth> 270 </field> 271 <field> 272 <name>CTIE</name> 273 <description>Clock Counter Overflow Interrupt Enable.</description> 274 <bitOffset>2</bitOffset> 275 <bitWidth>1</bitWidth> 276 </field> 277 <field> 278 <name>TCIE</name> 279 <description>Character Transmission Completion Interrupt Enable.</description> 280 <bitOffset>3</bitOffset> 281 <bitWidth>1</bitWidth> 282 </field> 283 <field> 284 <name>RXEIE</name> 285 <description>Receive FIFO Empty Interrupt Enable.</description> 286 <bitOffset>4</bitOffset> 287 <bitWidth>1</bitWidth> 288 </field> 289 <field> 290 <name>RXTIE</name> 291 <description>Receive FIFO Threshold Reached Interrupt Enable.</description> 292 <bitOffset>5</bitOffset> 293 <bitWidth>1</bitWidth> 294 </field> 295 <field> 296 <name>RXFIE</name> 297 <description>Receive FIFO Full Interrupt Enable.</description> 298 <bitOffset>6</bitOffset> 299 <bitWidth>1</bitWidth> 300 </field> 301 <field> 302 <name>TXEIE</name> 303 <description>Transmit FIFO Empty Interrupt Enable.</description> 304 <bitOffset>7</bitOffset> 305 <bitWidth>1</bitWidth> 306 </field> 307 <field> 308 <name>TXTIE</name> 309 <description>Transmit FIFO Threshold Reached Interrupt Enable.</description> 310 <bitOffset>8</bitOffset> 311 <bitWidth>1</bitWidth> 312 </field> 313 </fields> 314 </register> 315 <register> 316 <name>ISR</name> 317 <description>Interrupt Status Register.</description> 318 <addressOffset>0x20</addressOffset> 319 <fields> 320 <field> 321 <name>PARIS</name> 322 <description>Parity Error Interrupt Status Flag.</description> 323 <bitOffset>0</bitOffset> 324 <bitWidth>1</bitWidth> 325 </field> 326 <field> 327 <name>WTIS</name> 328 <description>Waiting Time Overflow Interrupt Status Flag.</description> 329 <bitOffset>1</bitOffset> 330 <bitWidth>1</bitWidth> 331 </field> 332 <field> 333 <name>CTIS</name> 334 <description>Clock Counter Overflow Interrupt Status Flag.</description> 335 <bitOffset>2</bitOffset> 336 <bitWidth>1</bitWidth> 337 </field> 338 <field> 339 <name>TCIS</name> 340 <description>Character Transmission Completion Interrupt Status Flag.</description> 341 <bitOffset>3</bitOffset> 342 <bitWidth>1</bitWidth> 343 </field> 344 <field> 345 <name>RXEIS</name> 346 <description>Receive FIFO Empty Interrupt Status Flag.</description> 347 <bitOffset>4</bitOffset> 348 <bitWidth>1</bitWidth> 349 </field> 350 <field> 351 <name>RXTIS</name> 352 <description>Receive FIFO Threshold Reached Interrupt Status Flag.</description> 353 <bitOffset>5</bitOffset> 354 <bitWidth>1</bitWidth> 355 </field> 356 <field> 357 <name>RXFIS</name> 358 <description>Receive FIFO Full Interrupt Status Flag.</description> 359 <bitOffset>6</bitOffset> 360 <bitWidth>1</bitWidth> 361 </field> 362 <field> 363 <name>TXEIS</name> 364 <description>Transmit FIFO Empty Interrupt Status Flag.</description> 365 <bitOffset>7</bitOffset> 366 <bitWidth>1</bitWidth> 367 </field> 368 <field> 369 <name>TXTIS</name> 370 <description>Transmit FIFO Threshold Reached Interrupt Status Flag.</description> 371 <bitOffset>8</bitOffset> 372 <bitWidth>1</bitWidth> 373 </field> 374 </fields> 375 </register> 376 <register> 377 <name>TXR</name> 378 <description>Transmit Register.</description> 379 <addressOffset>0x24</addressOffset> 380 <fields> 381 <field> 382 <name>DATA</name> 383 <description>Transmit Data.</description> 384 <bitOffset>0</bitOffset> 385 <bitWidth>8</bitWidth> 386 </field> 387 </fields> 388 </register> 389 <register> 390 <name>RXR</name> 391 <description>Receive Register.</description> 392 <addressOffset>0x28</addressOffset> 393 <fields> 394 <field> 395 <name>DATA</name> 396 <description>Receive Data.</description> 397 <bitOffset>0</bitOffset> 398 <bitWidth>8</bitWidth> 399 </field> 400 <field> 401 <name>PARER</name> 402 <description>Parity Error Detect Bit.</description> 403 <bitOffset>8</bitOffset> 404 <bitWidth>1</bitWidth> 405 </field> 406 </fields> 407 </register> 408 <register> 409 <name>CCR</name> 410 <description>Clock Counter Register,</description> 411 <addressOffset>0x2C</addressOffset> 412 <fields> 413 <field> 414 <name>CCYC</name> 415 <description>Number of Clock Cycles to Count.</description> 416 <bitOffset>0</bitOffset> 417 <bitWidth>24</bitWidth> 418 </field> 419 <field> 420 <name>MAN</name> 421 <description>Manual Mode.</description> 422 <bitOffset>31</bitOffset> 423 <bitWidth>1</bitWidth> 424 </field> 425 </fields> 426 </register> 427 </registers> 428 </peripheral> 429 <!--SC: Smart Card Interface--> 430</device>
