1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SCN</name> 5 <description>Smart Card Interface.</description> 6 <groupName>SCN</groupName> 7 <baseAddress>0x4002C000</baseAddress> 8 <addressBlock> 9 <offset>0x00</offset> 10 <size>0x1000</size> 11 <usage>registers</usage> 12 </addressBlock> 13 <interrupt> 14 <name>SC0</name> 15 <description>SC0 IRQ</description> 16 <value>11</value> 17 </interrupt> 18 <registers> 19 <register> 20 <name>CR</name> 21 <description>Control Register.</description> 22 <addressOffset>0x00</addressOffset> 23 <fields> 24 <field> 25 <name>CONV</name> 26 <description>Convention Select Bit.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>1</bitWidth> 29 </field> 30 <field> 31 <name>CREP</name> 32 <description>Character Repeat Enable Bit.</description> 33 <bitOffset>1</bitOffset> 34 <bitWidth>1</bitWidth> 35 </field> 36 <field> 37 <name>WTEN</name> 38 <description>Wait Time Counter Enable Bit.</description> 39 <bitOffset>2</bitOffset> 40 <bitWidth>1</bitWidth> 41 </field> 42 <field> 43 <name>UART</name> 44 <description>Smart Card Mode Bit.</description> 45 <bitOffset>3</bitOffset> 46 <bitWidth>1</bitWidth> 47 </field> 48 <field> 49 <name>CCEN</name> 50 <description>Clock Counter Enable Bit.</description> 51 <bitOffset>4</bitOffset> 52 <bitWidth>1</bitWidth> 53 </field> 54 <field> 55 <name>RXFLUSH</name> 56 <description>Receive FIFO Flush.</description> 57 <bitOffset>5</bitOffset> 58 <bitWidth>1</bitWidth> 59 </field> 60 <field> 61 <name>TXFLUSH</name> 62 <description>Transmit FIFO Flush.</description> 63 <bitOffset>6</bitOffset> 64 <bitWidth>1</bitWidth> 65 </field> 66 <field> 67 <name>RXTHD</name> 68 <description>Receive FIFO Depth.</description> 69 <bitOffset>8</bitOffset> 70 <bitWidth>4</bitWidth> 71 </field> 72 <field> 73 <name>TXTHD</name> 74 <description>Transmit FIFO Depth.</description> 75 <bitOffset>12</bitOffset> 76 <bitWidth>4</bitWidth> 77 </field> 78 <field> 79 <name>DUAL_MODE</name> 80 <description>Dual Internal AFE and Bypass Mode.</description> 81 <bitOffset>23</bitOffset> 82 <bitWidth>1</bitWidth> 83 </field> 84 </fields> 85 </register> 86 <register> 87 <name>SR</name> 88 <description>Status Register.</description> 89 <addressOffset>0x04</addressOffset> 90 <fields> 91 <field> 92 <name>PAR</name> 93 <description>Parity Error Detector Flag.</description> 94 <bitOffset>0</bitOffset> 95 <bitWidth>1</bitWidth> 96 </field> 97 <field> 98 <name>WTOV</name> 99 <description>Waiting Time Counter Overflow.</description> 100 <bitOffset>1</bitOffset> 101 <bitWidth>1</bitWidth> 102 </field> 103 <field> 104 <name>CCOV</name> 105 <description>Clock Counter Overflow Flag.</description> 106 <bitOffset>2</bitOffset> 107 <bitWidth>1</bitWidth> 108 </field> 109 <field> 110 <name>TXCF</name> 111 <description>Transmit Complete Flag.</description> 112 <bitOffset>3</bitOffset> 113 <bitWidth>1</bitWidth> 114 </field> 115 <field> 116 <name>RXEMPTY</name> 117 <description>Receive FIFO Empty Flag.</description> 118 <bitOffset>4</bitOffset> 119 <bitWidth>1</bitWidth> 120 </field> 121 <field> 122 <name>RXFULL</name> 123 <description>Receive FIFO Full Flag.</description> 124 <bitOffset>5</bitOffset> 125 <bitWidth>1</bitWidth> 126 </field> 127 <field> 128 <name>TXEMPTY</name> 129 <description>Transmit FIFO Empty Flag.</description> 130 <bitOffset>6</bitOffset> 131 <bitWidth>1</bitWidth> 132 </field> 133 <field> 134 <name>TXFULL</name> 135 <description>Transmit FIFO Full Flag.</description> 136 <bitOffset>7</bitOffset> 137 <bitWidth>1</bitWidth> 138 </field> 139 <field> 140 <name>RXELT</name> 141 <description>Number of Bytes in the Receive FIFO.</description> 142 <bitOffset>8</bitOffset> 143 <bitWidth>4</bitWidth> 144 </field> 145 <field> 146 <name>TXELT</name> 147 <description>Number of Bytes in the Transmit FIFO.</description> 148 <bitOffset>12</bitOffset> 149 <bitWidth>4</bitWidth> 150 </field> 151 </fields> 152 </register> 153 <register> 154 <name>PN</name> 155 <description>Pin Register.</description> 156 <addressOffset>0x08</addressOffset> 157 <fields> 158 <field> 159 <name>CRDRST</name> 160 <description>Smart Card Reset Pin Control.</description> 161 <bitOffset>0</bitOffset> 162 <bitWidth>1</bitWidth> 163 </field> 164 <field> 165 <name>CRDCLK</name> 166 <description>Smart Card Clock Piin Control.</description> 167 <bitOffset>1</bitOffset> 168 <bitWidth>1</bitWidth> 169 </field> 170 <field> 171 <name>CRDIO</name> 172 <description>Smart Card IO Pin Control.</description> 173 <bitOffset>2</bitOffset> 174 <bitWidth>1</bitWidth> 175 </field> 176 <field> 177 <name>CRDC4</name> 178 <description>Smart Card SCn_C4 Pin Control.</description> 179 <bitOffset>3</bitOffset> 180 <bitWidth>1</bitWidth> 181 </field> 182 <field> 183 <name>CRDC8</name> 184 <description>Smart Card SCn_C8 Pin Control.</description> 185 <bitOffset>4</bitOffset> 186 <bitWidth>1</bitWidth> 187 </field> 188 <field> 189 <name>CLKSEL</name> 190 <description>Smart Card Clock Select.</description> 191 <bitOffset>5</bitOffset> 192 <bitWidth>1</bitWidth> 193 </field> 194 <field> 195 <name>IO_C48_EN</name> 196 <description>Pin Enable.</description> 197 <bitOffset>16</bitOffset> 198 <bitWidth>1</bitWidth> 199 </field> 200 </fields> 201 </register> 202 <register> 203 <name>ETUR</name> 204 <description>ETU Register.</description> 205 <addressOffset>0x0C</addressOffset> 206 <fields> 207 <field> 208 <name>ETU</name> 209 <description>Elemental Time Unit Value.</description> 210 <bitOffset>0</bitOffset> 211 <bitWidth>15</bitWidth> 212 </field> 213 <field> 214 <name>COMP</name> 215 <description>Compensation Mode Enable Bit.</description> 216 <bitOffset>15</bitOffset> 217 <bitWidth>1</bitWidth> 218 </field> 219 <field> 220 <name>HALF</name> 221 <description>Half ETU Count Selection Bit.</description> 222 <bitOffset>16</bitOffset> 223 <bitWidth>1</bitWidth> 224 </field> 225 </fields> 226 </register> 227 <register> 228 <name>GTR</name> 229 <description>Guard Time Register.</description> 230 <addressOffset>0x10</addressOffset> 231 <fields> 232 <field> 233 <name>GT</name> 234 <description>Guard Time.</description> 235 <bitOffset>0</bitOffset> 236 <bitWidth>16</bitWidth> 237 </field> 238 </fields> 239 </register> 240 <register> 241 <name>WT0R</name> 242 <description>Waiting Time 0 Register.</description> 243 <addressOffset>0x14</addressOffset> 244 <fields> 245 <field> 246 <name>WT</name> 247 <description>Wait Time.</description> 248 <bitOffset>0</bitOffset> 249 <bitWidth>32</bitWidth> 250 </field> 251 </fields> 252 </register> 253 <register> 254 <name>WT1R</name> 255 <description>Waiting Time 1 Register.</description> 256 <addressOffset>0x18</addressOffset> 257 <fields> 258 <field> 259 <name>WT</name> 260 <description>Wait Time.</description> 261 <bitOffset>0</bitOffset> 262 <bitWidth>8</bitWidth> 263 </field> 264 </fields> 265 </register> 266 <register> 267 <name>IER</name> 268 <description>Interrupt Enable Register.</description> 269 <addressOffset>0x1C</addressOffset> 270 <fields> 271 <field> 272 <name>PARIE</name> 273 <description>Parity Error Interrupt Enable.</description> 274 <bitOffset>0</bitOffset> 275 <bitWidth>1</bitWidth> 276 </field> 277 <field> 278 <name>WTIE</name> 279 <description>Waiting Time Overflow Interrupt Enable.</description> 280 <bitOffset>1</bitOffset> 281 <bitWidth>1</bitWidth> 282 </field> 283 <field> 284 <name>CTIE</name> 285 <description>Clock Counter Overflow Interrupt Enable.</description> 286 <bitOffset>2</bitOffset> 287 <bitWidth>1</bitWidth> 288 </field> 289 <field> 290 <name>TCIE</name> 291 <description>Character Transmission Completion Interrupt Enable.</description> 292 <bitOffset>3</bitOffset> 293 <bitWidth>1</bitWidth> 294 </field> 295 <field> 296 <name>RXEIE</name> 297 <description>Receive FIFO Empty Interrupt Enable.</description> 298 <bitOffset>4</bitOffset> 299 <bitWidth>1</bitWidth> 300 </field> 301 <field> 302 <name>RXTIE</name> 303 <description>Receive FIFO Threshold Reached Interrupt Enable.</description> 304 <bitOffset>5</bitOffset> 305 <bitWidth>1</bitWidth> 306 </field> 307 <field> 308 <name>RXFIE</name> 309 <description>Receive FIFO Full Interrupt Enable.</description> 310 <bitOffset>6</bitOffset> 311 <bitWidth>1</bitWidth> 312 </field> 313 <field> 314 <name>TXEIE</name> 315 <description>Transmit FIFO Empty Interrupt Enable.</description> 316 <bitOffset>7</bitOffset> 317 <bitWidth>1</bitWidth> 318 </field> 319 <field> 320 <name>TXTIE</name> 321 <description>Transmit FIFO Threshold Reached Interrupt Enable.</description> 322 <bitOffset>8</bitOffset> 323 <bitWidth>1</bitWidth> 324 </field> 325 </fields> 326 </register> 327 <register> 328 <name>ISR</name> 329 <description>Interrupt Status Register.</description> 330 <addressOffset>0x20</addressOffset> 331 <fields> 332 <field> 333 <name>PARIS</name> 334 <description>Parity Error Interrupt Status Flag.</description> 335 <bitOffset>0</bitOffset> 336 <bitWidth>1</bitWidth> 337 </field> 338 <field> 339 <name>WTIS</name> 340 <description>Waiting Time Overflow Interrupt Status Flag.</description> 341 <bitOffset>1</bitOffset> 342 <bitWidth>1</bitWidth> 343 </field> 344 <field> 345 <name>CTIS</name> 346 <description>Clock Counter Overflow Interrupt Status Flag.</description> 347 <bitOffset>2</bitOffset> 348 <bitWidth>1</bitWidth> 349 </field> 350 <field> 351 <name>TCIS</name> 352 <description>Character Transmission Completion Interrupt Status Flag.</description> 353 <bitOffset>3</bitOffset> 354 <bitWidth>1</bitWidth> 355 </field> 356 <field> 357 <name>RXEIS</name> 358 <description>Receive FIFO Empty Interrupt Status Flag.</description> 359 <bitOffset>4</bitOffset> 360 <bitWidth>1</bitWidth> 361 </field> 362 <field> 363 <name>RXTIS</name> 364 <description>Receive FIFO Threshold Reached Interrupt Status Flag.</description> 365 <bitOffset>5</bitOffset> 366 <bitWidth>1</bitWidth> 367 </field> 368 <field> 369 <name>RXFIS</name> 370 <description>Receive FIFO Full Interrupt Status Flag.</description> 371 <bitOffset>6</bitOffset> 372 <bitWidth>1</bitWidth> 373 </field> 374 <field> 375 <name>TXEIS</name> 376 <description>Transmit FIFO Empty Interrupt Status Flag.</description> 377 <bitOffset>7</bitOffset> 378 <bitWidth>1</bitWidth> 379 </field> 380 <field> 381 <name>TXTIS</name> 382 <description>Transmit FIFO Threshold Reached Interrupt Status Flag.</description> 383 <bitOffset>8</bitOffset> 384 <bitWidth>1</bitWidth> 385 </field> 386 </fields> 387 </register> 388 <register> 389 <name>TXR</name> 390 <description>Transmit Register.</description> 391 <addressOffset>0x24</addressOffset> 392 <fields> 393 <field> 394 <name>DATA</name> 395 <description>Transmit Data.</description> 396 <bitOffset>0</bitOffset> 397 <bitWidth>8</bitWidth> 398 </field> 399 </fields> 400 </register> 401 <register> 402 <name>RXR</name> 403 <description>Receive Register.</description> 404 <addressOffset>0x28</addressOffset> 405 <fields> 406 <field> 407 <name>DATA</name> 408 <description>Receive Data.</description> 409 <bitOffset>0</bitOffset> 410 <bitWidth>8</bitWidth> 411 </field> 412 <field> 413 <name>PARER</name> 414 <description>Parity Error Detect Bit.</description> 415 <bitOffset>8</bitOffset> 416 <bitWidth>1</bitWidth> 417 </field> 418 </fields> 419 </register> 420 <register> 421 <name>CCR</name> 422 <description>Clock Counter Register.</description> 423 <addressOffset>0x2C</addressOffset> 424 <fields> 425 <field> 426 <name>CCYC</name> 427 <description>Number of Clock Cycles to Count.</description> 428 <bitOffset>0</bitOffset> 429 <bitWidth>24</bitWidth> 430 </field> 431 <field> 432 <name>MAN</name> 433 <description>Manual Mode.</description> 434 <bitOffset>31</bitOffset> 435 <bitWidth>1</bitWidth> 436 </field> 437 </fields> 438 </register> 439 </registers> 440 </peripheral> 441 <!--SC: Smart Card Interface--> 442</device>
