1 /** 2 * @file ptg_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PTG_REVA Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_PTG_PTG_REVA_REGS_H_ 28 #define LIBRARIES_PERIPHDRIVERS_SOURCE_PTG_PTG_REVA_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup ptg_reva 66 * @defgroup ptg_reva_registers PTG_REVA_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the PTG_REVA Peripheral Module. 68 * @details Pulse Train Generation 69 */ 70 71 /** 72 * @ingroup ptg_reva_registers 73 * Structure type to access the PTG_REVA Registers. 74 */ 75 typedef struct { 76 __IO uint32_t enable; /**< <tt>\b 0x0000:</tt> PTG_REVA ENABLE Register */ 77 __IO uint32_t resync; /**< <tt>\b 0x0004:</tt> PTG_REVA RESYNC Register */ 78 __IO uint32_t stop_intfl; /**< <tt>\b 0x0008:</tt> PTG_REVA STOP_INTFL Register */ 79 __IO uint32_t stop_inten; /**< <tt>\b 0x000C:</tt> PTG_REVA STOP_INTEN Register */ 80 __O uint32_t safe_en; /**< <tt>\b 0x0010:</tt> PTG_REVA SAFE_EN Register */ 81 __O uint32_t safe_dis; /**< <tt>\b 0x0014:</tt> PTG_REVA SAFE_DIS Register */ 82 __IO uint32_t ready_intfl; /**< <tt>\b 0x0018:</tt> PTG_REVA READY_INTFL Register */ 83 __IO uint32_t ready_inten; /**< <tt>\b 0x001C:</tt> PTG_REVA READY_INTEN Register */ 84 } mxc_ptg_reva_regs_t; 85 86 /* Register offsets for module PTG_REVA */ 87 /** 88 * @ingroup ptg_reva_registers 89 * @defgroup PTG_REVA_Register_Offsets Register Offsets 90 * @brief PTG_REVA Peripheral Register Offsets from the PTG_REVA Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_PTG_REVA_ENABLE ((uint32_t)0x00000000UL) /**< Offset from PTG_REVA Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_PTG_REVA_RESYNC ((uint32_t)0x00000004UL) /**< Offset from PTG_REVA Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_PTG_REVA_STOP_INTFL ((uint32_t)0x00000008UL) /**< Offset from PTG_REVA Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_PTG_REVA_STOP_INTEN ((uint32_t)0x0000000CUL) /**< Offset from PTG_REVA Base Address: <tt> 0x000C</tt> */ 97 #define MXC_R_PTG_REVA_SAFE_EN ((uint32_t)0x00000010UL) /**< Offset from PTG_REVA Base Address: <tt> 0x0010</tt> */ 98 #define MXC_R_PTG_REVA_SAFE_DIS ((uint32_t)0x00000014UL) /**< Offset from PTG_REVA Base Address: <tt> 0x0014</tt> */ 99 #define MXC_R_PTG_REVA_READY_INTFL ((uint32_t)0x00000018UL) /**< Offset from PTG_REVA Base Address: <tt> 0x0018</tt> */ 100 #define MXC_R_PTG_REVA_READY_INTEN ((uint32_t)0x0000001CUL) /**< Offset from PTG_REVA Base Address: <tt> 0x001C</tt> */ 101 /**@} end of group ptg_reva_registers */ 102 103 /** 104 * @ingroup ptg_reva_registers 105 * @defgroup PTG_REVA_ENABLE PTG_REVA_ENABLE 106 * @brief Global Enable/Disable Controls for All Pulse Trains 107 * @{ 108 */ 109 #define MXC_F_PTG_REVA_ENABLE_PT0_POS 0 /**< ENABLE_PT0 Position */ 110 #define MXC_F_PTG_REVA_ENABLE_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT0_POS)) /**< ENABLE_PT0 Mask */ 111 112 #define MXC_F_PTG_REVA_ENABLE_PT1_POS 1 /**< ENABLE_PT1 Position */ 113 #define MXC_F_PTG_REVA_ENABLE_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT1_POS)) /**< ENABLE_PT1 Mask */ 114 115 #define MXC_F_PTG_REVA_ENABLE_PT2_POS 2 /**< ENABLE_PT2 Position */ 116 #define MXC_F_PTG_REVA_ENABLE_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT2_POS)) /**< ENABLE_PT2 Mask */ 117 118 #define MXC_F_PTG_REVA_ENABLE_PT3_POS 3 /**< ENABLE_PT3 Position */ 119 #define MXC_F_PTG_REVA_ENABLE_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT3_POS)) /**< ENABLE_PT3 Mask */ 120 121 #define MXC_F_PTG_REVA_ENABLE_PT4_POS 4 /**< ENABLE_PT4 Position */ 122 #define MXC_F_PTG_REVA_ENABLE_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT4_POS)) /**< ENABLE_PT4 Mask */ 123 124 #define MXC_F_PTG_REVA_ENABLE_PT5_POS 5 /**< ENABLE_PT5 Position */ 125 #define MXC_F_PTG_REVA_ENABLE_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT5_POS)) /**< ENABLE_PT5 Mask */ 126 127 #define MXC_F_PTG_REVA_ENABLE_PT6_POS 6 /**< ENABLE_PT6 Position */ 128 #define MXC_F_PTG_REVA_ENABLE_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT6_POS)) /**< ENABLE_PT6 Mask */ 129 130 #define MXC_F_PTG_REVA_ENABLE_PT7_POS 7 /**< ENABLE_PT7 Position */ 131 #define MXC_F_PTG_REVA_ENABLE_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT7_POS)) /**< ENABLE_PT7 Mask */ 132 133 #define MXC_F_PTG_REVA_ENABLE_PT8_POS 8 /**< ENABLE_PT8 Position */ 134 #define MXC_F_PTG_REVA_ENABLE_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT8_POS)) /**< ENABLE_PT8 Mask */ 135 136 #define MXC_F_PTG_REVA_ENABLE_PT9_POS 9 /**< ENABLE_PT9 Position */ 137 #define MXC_F_PTG_REVA_ENABLE_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT9_POS)) /**< ENABLE_PT9 Mask */ 138 139 #define MXC_F_PTG_REVA_ENABLE_PT10_POS 10 /**< ENABLE_PT10 Position */ 140 #define MXC_F_PTG_REVA_ENABLE_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT10_POS)) /**< ENABLE_PT10 Mask */ 141 142 #define MXC_F_PTG_REVA_ENABLE_PT11_POS 11 /**< ENABLE_PT11 Position */ 143 #define MXC_F_PTG_REVA_ENABLE_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT11_POS)) /**< ENABLE_PT11 Mask */ 144 145 #define MXC_F_PTG_REVA_ENABLE_PT12_POS 12 /**< ENABLE_PT12 Position */ 146 #define MXC_F_PTG_REVA_ENABLE_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT12_POS)) /**< ENABLE_PT12 Mask */ 147 148 #define MXC_F_PTG_REVA_ENABLE_PT13_POS 13 /**< ENABLE_PT13 Position */ 149 #define MXC_F_PTG_REVA_ENABLE_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT13_POS)) /**< ENABLE_PT13 Mask */ 150 151 #define MXC_F_PTG_REVA_ENABLE_PT14_POS 14 /**< ENABLE_PT14 Position */ 152 #define MXC_F_PTG_REVA_ENABLE_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT14_POS)) /**< ENABLE_PT14 Mask */ 153 154 #define MXC_F_PTG_REVA_ENABLE_PT15_POS 15 /**< ENABLE_PT15 Position */ 155 #define MXC_F_PTG_REVA_ENABLE_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_ENABLE_PT15_POS)) /**< ENABLE_PT15 Mask */ 156 157 /**@} end of group PTG_REVA_ENABLE_Register */ 158 159 /** 160 * @ingroup ptg_reva_registers 161 * @defgroup PTG_REVA_RESYNC PTG_REVA_RESYNC 162 * @brief Global Resync (All Pulse Trains) Control 163 * @{ 164 */ 165 #define MXC_F_PTG_REVA_RESYNC_PT0_POS 0 /**< RESYNC_PT0 Position */ 166 #define MXC_F_PTG_REVA_RESYNC_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT0_POS)) /**< RESYNC_PT0 Mask */ 167 168 #define MXC_F_PTG_REVA_RESYNC_PT1_POS 1 /**< RESYNC_PT1 Position */ 169 #define MXC_F_PTG_REVA_RESYNC_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT1_POS)) /**< RESYNC_PT1 Mask */ 170 171 #define MXC_F_PTG_REVA_RESYNC_PT2_POS 2 /**< RESYNC_PT2 Position */ 172 #define MXC_F_PTG_REVA_RESYNC_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT2_POS)) /**< RESYNC_PT2 Mask */ 173 174 #define MXC_F_PTG_REVA_RESYNC_PT3_POS 3 /**< RESYNC_PT3 Position */ 175 #define MXC_F_PTG_REVA_RESYNC_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT3_POS)) /**< RESYNC_PT3 Mask */ 176 177 #define MXC_F_PTG_REVA_RESYNC_PT4_POS 4 /**< RESYNC_PT4 Position */ 178 #define MXC_F_PTG_REVA_RESYNC_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT4_POS)) /**< RESYNC_PT4 Mask */ 179 180 #define MXC_F_PTG_REVA_RESYNC_PT5_POS 5 /**< RESYNC_PT5 Position */ 181 #define MXC_F_PTG_REVA_RESYNC_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT5_POS)) /**< RESYNC_PT5 Mask */ 182 183 #define MXC_F_PTG_REVA_RESYNC_PT6_POS 6 /**< RESYNC_PT6 Position */ 184 #define MXC_F_PTG_REVA_RESYNC_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT6_POS)) /**< RESYNC_PT6 Mask */ 185 186 #define MXC_F_PTG_REVA_RESYNC_PT7_POS 7 /**< RESYNC_PT7 Position */ 187 #define MXC_F_PTG_REVA_RESYNC_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT7_POS)) /**< RESYNC_PT7 Mask */ 188 189 #define MXC_F_PTG_REVA_RESYNC_PT8_POS 8 /**< RESYNC_PT8 Position */ 190 #define MXC_F_PTG_REVA_RESYNC_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT8_POS)) /**< RESYNC_PT8 Mask */ 191 192 #define MXC_F_PTG_REVA_RESYNC_PT9_POS 9 /**< RESYNC_PT9 Position */ 193 #define MXC_F_PTG_REVA_RESYNC_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT9_POS)) /**< RESYNC_PT9 Mask */ 194 195 #define MXC_F_PTG_REVA_RESYNC_PT10_POS 10 /**< RESYNC_PT10 Position */ 196 #define MXC_F_PTG_REVA_RESYNC_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT10_POS)) /**< RESYNC_PT10 Mask */ 197 198 #define MXC_F_PTG_REVA_RESYNC_PT11_POS 11 /**< RESYNC_PT11 Position */ 199 #define MXC_F_PTG_REVA_RESYNC_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT11_POS)) /**< RESYNC_PT11 Mask */ 200 201 #define MXC_F_PTG_REVA_RESYNC_PT12_POS 12 /**< RESYNC_PT12 Position */ 202 #define MXC_F_PTG_REVA_RESYNC_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT12_POS)) /**< RESYNC_PT12 Mask */ 203 204 #define MXC_F_PTG_REVA_RESYNC_PT13_POS 13 /**< RESYNC_PT13 Position */ 205 #define MXC_F_PTG_REVA_RESYNC_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT13_POS)) /**< RESYNC_PT13 Mask */ 206 207 #define MXC_F_PTG_REVA_RESYNC_PT14_POS 14 /**< RESYNC_PT14 Position */ 208 #define MXC_F_PTG_REVA_RESYNC_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT14_POS)) /**< RESYNC_PT14 Mask */ 209 210 #define MXC_F_PTG_REVA_RESYNC_PT15_POS 15 /**< RESYNC_PT15 Position */ 211 #define MXC_F_PTG_REVA_RESYNC_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_RESYNC_PT15_POS)) /**< RESYNC_PT15 Mask */ 212 213 /**@} end of group PTG_REVA_RESYNC_Register */ 214 215 /** 216 * @ingroup ptg_reva_registers 217 * @defgroup PTG_REVA_STOP_INTFL PTG_REVA_STOP_INTFL 218 * @brief Pulse Train Interrupt Flags 219 * @{ 220 */ 221 #define MXC_F_PTG_REVA_STOP_INTFL_PT0_POS 0 /**< STOP_INTFL_PT0 Position */ 222 #define MXC_F_PTG_REVA_STOP_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT0_POS)) /**< STOP_INTFL_PT0 Mask */ 223 224 #define MXC_F_PTG_REVA_STOP_INTFL_PT1_POS 1 /**< STOP_INTFL_PT1 Position */ 225 #define MXC_F_PTG_REVA_STOP_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT1_POS)) /**< STOP_INTFL_PT1 Mask */ 226 227 #define MXC_F_PTG_REVA_STOP_INTFL_PT2_POS 2 /**< STOP_INTFL_PT2 Position */ 228 #define MXC_F_PTG_REVA_STOP_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT2_POS)) /**< STOP_INTFL_PT2 Mask */ 229 230 #define MXC_F_PTG_REVA_STOP_INTFL_PT3_POS 3 /**< STOP_INTFL_PT3 Position */ 231 #define MXC_F_PTG_REVA_STOP_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT3_POS)) /**< STOP_INTFL_PT3 Mask */ 232 233 #define MXC_F_PTG_REVA_STOP_INTFL_PT4_POS 4 /**< STOP_INTFL_PT4 Position */ 234 #define MXC_F_PTG_REVA_STOP_INTFL_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT4_POS)) /**< STOP_INTFL_PT4 Mask */ 235 236 #define MXC_F_PTG_REVA_STOP_INTFL_PT5_POS 5 /**< STOP_INTFL_PT5 Position */ 237 #define MXC_F_PTG_REVA_STOP_INTFL_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT5_POS)) /**< STOP_INTFL_PT5 Mask */ 238 239 #define MXC_F_PTG_REVA_STOP_INTFL_PT6_POS 6 /**< STOP_INTFL_PT6 Position */ 240 #define MXC_F_PTG_REVA_STOP_INTFL_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT6_POS)) /**< STOP_INTFL_PT6 Mask */ 241 242 #define MXC_F_PTG_REVA_STOP_INTFL_PT7_POS 7 /**< STOP_INTFL_PT7 Position */ 243 #define MXC_F_PTG_REVA_STOP_INTFL_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT7_POS)) /**< STOP_INTFL_PT7 Mask */ 244 245 #define MXC_F_PTG_REVA_STOP_INTFL_PT8_POS 8 /**< STOP_INTFL_PT8 Position */ 246 #define MXC_F_PTG_REVA_STOP_INTFL_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT8_POS)) /**< STOP_INTFL_PT8 Mask */ 247 248 #define MXC_F_PTG_REVA_STOP_INTFL_PT9_POS 9 /**< STOP_INTFL_PT9 Position */ 249 #define MXC_F_PTG_REVA_STOP_INTFL_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT9_POS)) /**< STOP_INTFL_PT9 Mask */ 250 251 #define MXC_F_PTG_REVA_STOP_INTFL_PT10_POS 10 /**< STOP_INTFL_PT10 Position */ 252 #define MXC_F_PTG_REVA_STOP_INTFL_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT10_POS)) /**< STOP_INTFL_PT10 Mask */ 253 254 #define MXC_F_PTG_REVA_STOP_INTFL_PT11_POS 11 /**< STOP_INTFL_PT11 Position */ 255 #define MXC_F_PTG_REVA_STOP_INTFL_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT11_POS)) /**< STOP_INTFL_PT11 Mask */ 256 257 #define MXC_F_PTG_REVA_STOP_INTFL_PT12_POS 12 /**< STOP_INTFL_PT12 Position */ 258 #define MXC_F_PTG_REVA_STOP_INTFL_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT12_POS)) /**< STOP_INTFL_PT12 Mask */ 259 260 #define MXC_F_PTG_REVA_STOP_INTFL_PT13_POS 13 /**< STOP_INTFL_PT13 Position */ 261 #define MXC_F_PTG_REVA_STOP_INTFL_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT13_POS)) /**< STOP_INTFL_PT13 Mask */ 262 263 #define MXC_F_PTG_REVA_STOP_INTFL_PT14_POS 14 /**< STOP_INTFL_PT14 Position */ 264 #define MXC_F_PTG_REVA_STOP_INTFL_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT14_POS)) /**< STOP_INTFL_PT14 Mask */ 265 266 #define MXC_F_PTG_REVA_STOP_INTFL_PT15_POS 15 /**< STOP_INTFL_PT15 Position */ 267 #define MXC_F_PTG_REVA_STOP_INTFL_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTFL_PT15_POS)) /**< STOP_INTFL_PT15 Mask */ 268 269 /**@} end of group PTG_REVA_STOP_INTFL_Register */ 270 271 /** 272 * @ingroup ptg_reva_registers 273 * @defgroup PTG_REVA_STOP_INTEN PTG_REVA_STOP_INTEN 274 * @brief Pulse Train Interrupt Enable/Disable 275 * @{ 276 */ 277 #define MXC_F_PTG_REVA_STOP_INTEN_PT0_POS 0 /**< STOP_INTEN_PT0 Position */ 278 #define MXC_F_PTG_REVA_STOP_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT0_POS)) /**< STOP_INTEN_PT0 Mask */ 279 280 #define MXC_F_PTG_REVA_STOP_INTEN_PT1_POS 1 /**< STOP_INTEN_PT1 Position */ 281 #define MXC_F_PTG_REVA_STOP_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT1_POS)) /**< STOP_INTEN_PT1 Mask */ 282 283 #define MXC_F_PTG_REVA_STOP_INTEN_PT2_POS 2 /**< STOP_INTEN_PT2 Position */ 284 #define MXC_F_PTG_REVA_STOP_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT2_POS)) /**< STOP_INTEN_PT2 Mask */ 285 286 #define MXC_F_PTG_REVA_STOP_INTEN_PT3_POS 3 /**< STOP_INTEN_PT3 Position */ 287 #define MXC_F_PTG_REVA_STOP_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT3_POS)) /**< STOP_INTEN_PT3 Mask */ 288 289 #define MXC_F_PTG_REVA_STOP_INTEN_PT4_POS 4 /**< STOP_INTEN_PT4 Position */ 290 #define MXC_F_PTG_REVA_STOP_INTEN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT4_POS)) /**< STOP_INTEN_PT4 Mask */ 291 292 #define MXC_F_PTG_REVA_STOP_INTEN_PT5_POS 5 /**< STOP_INTEN_PT5 Position */ 293 #define MXC_F_PTG_REVA_STOP_INTEN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT5_POS)) /**< STOP_INTEN_PT5 Mask */ 294 295 #define MXC_F_PTG_REVA_STOP_INTEN_PT6_POS 6 /**< STOP_INTEN_PT6 Position */ 296 #define MXC_F_PTG_REVA_STOP_INTEN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT6_POS)) /**< STOP_INTEN_PT6 Mask */ 297 298 #define MXC_F_PTG_REVA_STOP_INTEN_PT7_POS 7 /**< STOP_INTEN_PT7 Position */ 299 #define MXC_F_PTG_REVA_STOP_INTEN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT7_POS)) /**< STOP_INTEN_PT7 Mask */ 300 301 #define MXC_F_PTG_REVA_STOP_INTEN_PT8_POS 8 /**< STOP_INTEN_PT8 Position */ 302 #define MXC_F_PTG_REVA_STOP_INTEN_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT8_POS)) /**< STOP_INTEN_PT8 Mask */ 303 304 #define MXC_F_PTG_REVA_STOP_INTEN_PT9_POS 9 /**< STOP_INTEN_PT9 Position */ 305 #define MXC_F_PTG_REVA_STOP_INTEN_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT9_POS)) /**< STOP_INTEN_PT9 Mask */ 306 307 #define MXC_F_PTG_REVA_STOP_INTEN_PT10_POS 10 /**< STOP_INTEN_PT10 Position */ 308 #define MXC_F_PTG_REVA_STOP_INTEN_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT10_POS)) /**< STOP_INTEN_PT10 Mask */ 309 310 #define MXC_F_PTG_REVA_STOP_INTEN_PT11_POS 11 /**< STOP_INTEN_PT11 Position */ 311 #define MXC_F_PTG_REVA_STOP_INTEN_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT11_POS)) /**< STOP_INTEN_PT11 Mask */ 312 313 #define MXC_F_PTG_REVA_STOP_INTEN_PT12_POS 12 /**< STOP_INTEN_PT12 Position */ 314 #define MXC_F_PTG_REVA_STOP_INTEN_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT12_POS)) /**< STOP_INTEN_PT12 Mask */ 315 316 #define MXC_F_PTG_REVA_STOP_INTEN_PT13_POS 13 /**< STOP_INTEN_PT13 Position */ 317 #define MXC_F_PTG_REVA_STOP_INTEN_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT13_POS)) /**< STOP_INTEN_PT13 Mask */ 318 319 #define MXC_F_PTG_REVA_STOP_INTEN_PT14_POS 14 /**< STOP_INTEN_PT14 Position */ 320 #define MXC_F_PTG_REVA_STOP_INTEN_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT14_POS)) /**< STOP_INTEN_PT14 Mask */ 321 322 #define MXC_F_PTG_REVA_STOP_INTEN_PT15_POS 15 /**< STOP_INTEN_PT15 Position */ 323 #define MXC_F_PTG_REVA_STOP_INTEN_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_STOP_INTEN_PT15_POS)) /**< STOP_INTEN_PT15 Mask */ 324 325 /**@} end of group PTG_REVA_STOP_INTEN_Register */ 326 327 /** 328 * @ingroup ptg_reva_registers 329 * @defgroup PTG_REVA_SAFE_EN PTG_REVA_SAFE_EN 330 * @brief Pulse Train Global Safe Enable. 331 * @{ 332 */ 333 #define MXC_F_PTG_REVA_SAFE_EN_PT0_POS 0 /**< SAFE_EN_PT0 Position */ 334 #define MXC_F_PTG_REVA_SAFE_EN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT0_POS)) /**< SAFE_EN_PT0 Mask */ 335 336 #define MXC_F_PTG_REVA_SAFE_EN_PT1_POS 1 /**< SAFE_EN_PT1 Position */ 337 #define MXC_F_PTG_REVA_SAFE_EN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT1_POS)) /**< SAFE_EN_PT1 Mask */ 338 339 #define MXC_F_PTG_REVA_SAFE_EN_PT2_POS 2 /**< SAFE_EN_PT2 Position */ 340 #define MXC_F_PTG_REVA_SAFE_EN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT2_POS)) /**< SAFE_EN_PT2 Mask */ 341 342 #define MXC_F_PTG_REVA_SAFE_EN_PT3_POS 3 /**< SAFE_EN_PT3 Position */ 343 #define MXC_F_PTG_REVA_SAFE_EN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT3_POS)) /**< SAFE_EN_PT3 Mask */ 344 345 #define MXC_F_PTG_REVA_SAFE_EN_PT4_POS 4 /**< SAFE_EN_PT4 Position */ 346 #define MXC_F_PTG_REVA_SAFE_EN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT4_POS)) /**< SAFE_EN_PT4 Mask */ 347 348 #define MXC_F_PTG_REVA_SAFE_EN_PT5_POS 5 /**< SAFE_EN_PT5 Position */ 349 #define MXC_F_PTG_REVA_SAFE_EN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT5_POS)) /**< SAFE_EN_PT5 Mask */ 350 351 #define MXC_F_PTG_REVA_SAFE_EN_PT6_POS 6 /**< SAFE_EN_PT6 Position */ 352 #define MXC_F_PTG_REVA_SAFE_EN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT6_POS)) /**< SAFE_EN_PT6 Mask */ 353 354 #define MXC_F_PTG_REVA_SAFE_EN_PT7_POS 7 /**< SAFE_EN_PT7 Position */ 355 #define MXC_F_PTG_REVA_SAFE_EN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT7_POS)) /**< SAFE_EN_PT7 Mask */ 356 357 #define MXC_F_PTG_REVA_SAFE_EN_PT8_POS 8 /**< SAFE_EN_PT8 Position */ 358 #define MXC_F_PTG_REVA_SAFE_EN_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT8_POS)) /**< SAFE_EN_PT8 Mask */ 359 360 #define MXC_F_PTG_REVA_SAFE_EN_PT9_POS 9 /**< SAFE_EN_PT9 Position */ 361 #define MXC_F_PTG_REVA_SAFE_EN_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT9_POS)) /**< SAFE_EN_PT9 Mask */ 362 363 #define MXC_F_PTG_REVA_SAFE_EN_PT10_POS 10 /**< SAFE_EN_PT10 Position */ 364 #define MXC_F_PTG_REVA_SAFE_EN_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT10_POS)) /**< SAFE_EN_PT10 Mask */ 365 366 #define MXC_F_PTG_REVA_SAFE_EN_PT11_POS 11 /**< SAFE_EN_PT11 Position */ 367 #define MXC_F_PTG_REVA_SAFE_EN_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT11_POS)) /**< SAFE_EN_PT11 Mask */ 368 369 #define MXC_F_PTG_REVA_SAFE_EN_PT12_POS 12 /**< SAFE_EN_PT12 Position */ 370 #define MXC_F_PTG_REVA_SAFE_EN_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT12_POS)) /**< SAFE_EN_PT12 Mask */ 371 372 #define MXC_F_PTG_REVA_SAFE_EN_PT13_POS 13 /**< SAFE_EN_PT13 Position */ 373 #define MXC_F_PTG_REVA_SAFE_EN_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT13_POS)) /**< SAFE_EN_PT13 Mask */ 374 375 #define MXC_F_PTG_REVA_SAFE_EN_PT14_POS 14 /**< SAFE_EN_PT14 Position */ 376 #define MXC_F_PTG_REVA_SAFE_EN_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT14_POS)) /**< SAFE_EN_PT14 Mask */ 377 378 #define MXC_F_PTG_REVA_SAFE_EN_PT15_POS 15 /**< SAFE_EN_PT15 Position */ 379 #define MXC_F_PTG_REVA_SAFE_EN_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_EN_PT15_POS)) /**< SAFE_EN_PT15 Mask */ 380 381 /**@} end of group PTG_REVA_SAFE_EN_Register */ 382 383 /** 384 * @ingroup ptg_reva_registers 385 * @defgroup PTG_REVA_SAFE_DIS PTG_REVA_SAFE_DIS 386 * @brief Pulse Train Global Safe Disable. 387 * @{ 388 */ 389 #define MXC_F_PTG_REVA_SAFE_DIS_PT0_POS 0 /**< SAFE_DIS_PT0 Position */ 390 #define MXC_F_PTG_REVA_SAFE_DIS_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT0_POS)) /**< SAFE_DIS_PT0 Mask */ 391 392 #define MXC_F_PTG_REVA_SAFE_DIS_PT1_POS 1 /**< SAFE_DIS_PT1 Position */ 393 #define MXC_F_PTG_REVA_SAFE_DIS_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT1_POS)) /**< SAFE_DIS_PT1 Mask */ 394 395 #define MXC_F_PTG_REVA_SAFE_DIS_PT2_POS 2 /**< SAFE_DIS_PT2 Position */ 396 #define MXC_F_PTG_REVA_SAFE_DIS_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT2_POS)) /**< SAFE_DIS_PT2 Mask */ 397 398 #define MXC_F_PTG_REVA_SAFE_DIS_PT3_POS 3 /**< SAFE_DIS_PT3 Position */ 399 #define MXC_F_PTG_REVA_SAFE_DIS_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT3_POS)) /**< SAFE_DIS_PT3 Mask */ 400 401 #define MXC_F_PTG_REVA_SAFE_DIS_PT4_POS 4 /**< SAFE_DIS_PT4 Position */ 402 #define MXC_F_PTG_REVA_SAFE_DIS_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT4_POS)) /**< SAFE_DIS_PT4 Mask */ 403 404 #define MXC_F_PTG_REVA_SAFE_DIS_PT5_POS 5 /**< SAFE_DIS_PT5 Position */ 405 #define MXC_F_PTG_REVA_SAFE_DIS_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT5_POS)) /**< SAFE_DIS_PT5 Mask */ 406 407 #define MXC_F_PTG_REVA_SAFE_DIS_PT6_POS 6 /**< SAFE_DIS_PT6 Position */ 408 #define MXC_F_PTG_REVA_SAFE_DIS_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT6_POS)) /**< SAFE_DIS_PT6 Mask */ 409 410 #define MXC_F_PTG_REVA_SAFE_DIS_PT7_POS 7 /**< SAFE_DIS_PT7 Position */ 411 #define MXC_F_PTG_REVA_SAFE_DIS_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT7_POS)) /**< SAFE_DIS_PT7 Mask */ 412 413 #define MXC_F_PTG_REVA_SAFE_DIS_PT8_POS 8 /**< SAFE_DIS_PT8 Position */ 414 #define MXC_F_PTG_REVA_SAFE_DIS_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT8_POS)) /**< SAFE_DIS_PT8 Mask */ 415 416 #define MXC_F_PTG_REVA_SAFE_DIS_PT9_POS 9 /**< SAFE_DIS_PT9 Position */ 417 #define MXC_F_PTG_REVA_SAFE_DIS_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT9_POS)) /**< SAFE_DIS_PT9 Mask */ 418 419 #define MXC_F_PTG_REVA_SAFE_DIS_PT10_POS 10 /**< SAFE_DIS_PT10 Position */ 420 #define MXC_F_PTG_REVA_SAFE_DIS_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT10_POS)) /**< SAFE_DIS_PT10 Mask */ 421 422 #define MXC_F_PTG_REVA_SAFE_DIS_PT11_POS 11 /**< SAFE_DIS_PT11 Position */ 423 #define MXC_F_PTG_REVA_SAFE_DIS_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT11_POS)) /**< SAFE_DIS_PT11 Mask */ 424 425 #define MXC_F_PTG_REVA_SAFE_DIS_PT12_POS 12 /**< SAFE_DIS_PT12 Position */ 426 #define MXC_F_PTG_REVA_SAFE_DIS_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT12_POS)) /**< SAFE_DIS_PT12 Mask */ 427 428 #define MXC_F_PTG_REVA_SAFE_DIS_PT13_POS 13 /**< SAFE_DIS_PT13 Position */ 429 #define MXC_F_PTG_REVA_SAFE_DIS_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT13_POS)) /**< SAFE_DIS_PT13 Mask */ 430 431 #define MXC_F_PTG_REVA_SAFE_DIS_PT14_POS 14 /**< SAFE_DIS_PT14 Position */ 432 #define MXC_F_PTG_REVA_SAFE_DIS_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT14_POS)) /**< SAFE_DIS_PT14 Mask */ 433 434 #define MXC_F_PTG_REVA_SAFE_DIS_PT15_POS 15 /**< SAFE_DIS_PT15 Position */ 435 #define MXC_F_PTG_REVA_SAFE_DIS_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_SAFE_DIS_PT15_POS)) /**< SAFE_DIS_PT15 Mask */ 436 437 /**@} end of group PTG_REVA_SAFE_DIS_Register */ 438 439 /** 440 * @ingroup ptg_reva_registers 441 * @defgroup PTG_REVA_READY_INTFL PTG_REVA_READY_INTFL 442 * @brief Pulse Train Ready Interrupt Flags 443 * @{ 444 */ 445 #define MXC_F_PTG_REVA_READY_INTFL_PT0_POS 0 /**< READY_INTFL_PT0 Position */ 446 #define MXC_F_PTG_REVA_READY_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT0_POS)) /**< READY_INTFL_PT0 Mask */ 447 448 #define MXC_F_PTG_REVA_READY_INTFL_PT1_POS 1 /**< READY_INTFL_PT1 Position */ 449 #define MXC_F_PTG_REVA_READY_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT1_POS)) /**< READY_INTFL_PT1 Mask */ 450 451 #define MXC_F_PTG_REVA_READY_INTFL_PT2_POS 2 /**< READY_INTFL_PT2 Position */ 452 #define MXC_F_PTG_REVA_READY_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT2_POS)) /**< READY_INTFL_PT2 Mask */ 453 454 #define MXC_F_PTG_REVA_READY_INTFL_PT3_POS 3 /**< READY_INTFL_PT3 Position */ 455 #define MXC_F_PTG_REVA_READY_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT3_POS)) /**< READY_INTFL_PT3 Mask */ 456 457 #define MXC_F_PTG_REVA_READY_INTFL_PT4_POS 4 /**< READY_INTFL_PT4 Position */ 458 #define MXC_F_PTG_REVA_READY_INTFL_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT4_POS)) /**< READY_INTFL_PT4 Mask */ 459 460 #define MXC_F_PTG_REVA_READY_INTFL_PT5_POS 5 /**< READY_INTFL_PT5 Position */ 461 #define MXC_F_PTG_REVA_READY_INTFL_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT5_POS)) /**< READY_INTFL_PT5 Mask */ 462 463 #define MXC_F_PTG_REVA_READY_INTFL_PT6_POS 6 /**< READY_INTFL_PT6 Position */ 464 #define MXC_F_PTG_REVA_READY_INTFL_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT6_POS)) /**< READY_INTFL_PT6 Mask */ 465 466 #define MXC_F_PTG_REVA_READY_INTFL_PT7_POS 7 /**< READY_INTFL_PT7 Position */ 467 #define MXC_F_PTG_REVA_READY_INTFL_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT7_POS)) /**< READY_INTFL_PT7 Mask */ 468 469 #define MXC_F_PTG_REVA_READY_INTFL_PT8_POS 8 /**< READY_INTFL_PT8 Position */ 470 #define MXC_F_PTG_REVA_READY_INTFL_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT8_POS)) /**< READY_INTFL_PT8 Mask */ 471 472 #define MXC_F_PTG_REVA_READY_INTFL_PT9_POS 9 /**< READY_INTFL_PT9 Position */ 473 #define MXC_F_PTG_REVA_READY_INTFL_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT9_POS)) /**< READY_INTFL_PT9 Mask */ 474 475 #define MXC_F_PTG_REVA_READY_INTFL_PT10_POS 10 /**< READY_INTFL_PT10 Position */ 476 #define MXC_F_PTG_REVA_READY_INTFL_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT10_POS)) /**< READY_INTFL_PT10 Mask */ 477 478 #define MXC_F_PTG_REVA_READY_INTFL_PT11_POS 11 /**< READY_INTFL_PT11 Position */ 479 #define MXC_F_PTG_REVA_READY_INTFL_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT11_POS)) /**< READY_INTFL_PT11 Mask */ 480 481 #define MXC_F_PTG_REVA_READY_INTFL_PT12_POS 12 /**< READY_INTFL_PT12 Position */ 482 #define MXC_F_PTG_REVA_READY_INTFL_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT12_POS)) /**< READY_INTFL_PT12 Mask */ 483 484 #define MXC_F_PTG_REVA_READY_INTFL_PT13_POS 13 /**< READY_INTFL_PT13 Position */ 485 #define MXC_F_PTG_REVA_READY_INTFL_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT13_POS)) /**< READY_INTFL_PT13 Mask */ 486 487 #define MXC_F_PTG_REVA_READY_INTFL_PT14_POS 14 /**< READY_INTFL_PT14 Position */ 488 #define MXC_F_PTG_REVA_READY_INTFL_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT14_POS)) /**< READY_INTFL_PT14 Mask */ 489 490 #define MXC_F_PTG_REVA_READY_INTFL_PT15_POS 15 /**< READY_INTFL_PT15 Position */ 491 #define MXC_F_PTG_REVA_READY_INTFL_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTFL_PT15_POS)) /**< READY_INTFL_PT15 Mask */ 492 493 /**@} end of group PTG_REVA_READY_INTFL_Register */ 494 495 /** 496 * @ingroup ptg_reva_registers 497 * @defgroup PTG_REVA_READY_INTEN PTG_REVA_READY_INTEN 498 * @brief Pulse Train Ready Interrupt Enable/Disable 499 * @{ 500 */ 501 #define MXC_F_PTG_REVA_READY_INTEN_PT0_POS 0 /**< READY_INTEN_PT0 Position */ 502 #define MXC_F_PTG_REVA_READY_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT0_POS)) /**< READY_INTEN_PT0 Mask */ 503 504 #define MXC_F_PTG_REVA_READY_INTEN_PT1_POS 1 /**< READY_INTEN_PT1 Position */ 505 #define MXC_F_PTG_REVA_READY_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT1_POS)) /**< READY_INTEN_PT1 Mask */ 506 507 #define MXC_F_PTG_REVA_READY_INTEN_PT2_POS 2 /**< READY_INTEN_PT2 Position */ 508 #define MXC_F_PTG_REVA_READY_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT2_POS)) /**< READY_INTEN_PT2 Mask */ 509 510 #define MXC_F_PTG_REVA_READY_INTEN_PT3_POS 3 /**< READY_INTEN_PT3 Position */ 511 #define MXC_F_PTG_REVA_READY_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT3_POS)) /**< READY_INTEN_PT3 Mask */ 512 513 #define MXC_F_PTG_REVA_READY_INTEN_PT4_POS 4 /**< READY_INTEN_PT4 Position */ 514 #define MXC_F_PTG_REVA_READY_INTEN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT4_POS)) /**< READY_INTEN_PT4 Mask */ 515 516 #define MXC_F_PTG_REVA_READY_INTEN_PT5_POS 5 /**< READY_INTEN_PT5 Position */ 517 #define MXC_F_PTG_REVA_READY_INTEN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT5_POS)) /**< READY_INTEN_PT5 Mask */ 518 519 #define MXC_F_PTG_REVA_READY_INTEN_PT6_POS 6 /**< READY_INTEN_PT6 Position */ 520 #define MXC_F_PTG_REVA_READY_INTEN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT6_POS)) /**< READY_INTEN_PT6 Mask */ 521 522 #define MXC_F_PTG_REVA_READY_INTEN_PT7_POS 7 /**< READY_INTEN_PT7 Position */ 523 #define MXC_F_PTG_REVA_READY_INTEN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT7_POS)) /**< READY_INTEN_PT7 Mask */ 524 525 #define MXC_F_PTG_REVA_READY_INTEN_PT8_POS 8 /**< READY_INTEN_PT8 Position */ 526 #define MXC_F_PTG_REVA_READY_INTEN_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT8_POS)) /**< READY_INTEN_PT8 Mask */ 527 528 #define MXC_F_PTG_REVA_READY_INTEN_PT9_POS 9 /**< READY_INTEN_PT9 Position */ 529 #define MXC_F_PTG_REVA_READY_INTEN_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT9_POS)) /**< READY_INTEN_PT9 Mask */ 530 531 #define MXC_F_PTG_REVA_READY_INTEN_PT10_POS 10 /**< READY_INTEN_PT10 Position */ 532 #define MXC_F_PTG_REVA_READY_INTEN_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT10_POS)) /**< READY_INTEN_PT10 Mask */ 533 534 #define MXC_F_PTG_REVA_READY_INTEN_PT11_POS 11 /**< READY_INTEN_PT11 Position */ 535 #define MXC_F_PTG_REVA_READY_INTEN_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT11_POS)) /**< READY_INTEN_PT11 Mask */ 536 537 #define MXC_F_PTG_REVA_READY_INTEN_PT12_POS 12 /**< READY_INTEN_PT12 Position */ 538 #define MXC_F_PTG_REVA_READY_INTEN_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT12_POS)) /**< READY_INTEN_PT12 Mask */ 539 540 #define MXC_F_PTG_REVA_READY_INTEN_PT13_POS 13 /**< READY_INTEN_PT13 Position */ 541 #define MXC_F_PTG_REVA_READY_INTEN_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT13_POS)) /**< READY_INTEN_PT13 Mask */ 542 543 #define MXC_F_PTG_REVA_READY_INTEN_PT14_POS 14 /**< READY_INTEN_PT14 Position */ 544 #define MXC_F_PTG_REVA_READY_INTEN_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT14_POS)) /**< READY_INTEN_PT14 Mask */ 545 546 #define MXC_F_PTG_REVA_READY_INTEN_PT15_POS 15 /**< READY_INTEN_PT15 Position */ 547 #define MXC_F_PTG_REVA_READY_INTEN_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_REVA_READY_INTEN_PT15_POS)) /**< READY_INTEN_PT15 Mask */ 548 549 /**@} end of group PTG_REVA_READY_INTEN_Register */ 550 551 #ifdef __cplusplus 552 } 553 #endif 554 555 #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_PTG_PTG_REVA_REGS_H_ 556
