1 /** 2 * @file pt_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PT Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _PT_REVA_REGS_H_ 27 #define _PT_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup pt 65 * @defgroup pt_registers PT_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the PT Peripheral Module. 67 * @details Pulse Train 68 */ 69 70 /** 71 * @ingroup pt_registers 72 * Structure type to access the PT Registers. 73 */ 74 typedef struct { 75 __IO uint32_t rate_length; /**< <tt>\b 0x0000:</tt> PT RATE_LENGTH Register */ 76 __IO uint32_t train; /**< <tt>\b 0x0004:</tt> PT TRAIN Register */ 77 __IO uint32_t loop; /**< <tt>\b 0x0008:</tt> PT LOOP Register */ 78 __IO uint32_t restart; /**< <tt>\b 0x000C:</tt> PT RESTART Register */ 79 } mxc_pt_reva_regs_t; 80 81 /* Register offsets for module PT */ 82 /** 83 * @ingroup pt_registers 84 * @defgroup PT_Register_Offsets Register Offsets 85 * @brief PT Peripheral Register Offsets from the PT Base Peripheral Address. 86 * @{ 87 */ 88 #define MXC_R_PT_REVA_RATE_LENGTH ((uint32_t)0x00000000UL) /**< Offset from PT Base Address: <tt> 0x0000</tt> */ 89 #define MXC_R_PT_REVA_TRAIN ((uint32_t)0x00000004UL) /**< Offset from PT Base Address: <tt> 0x0004</tt> */ 90 #define MXC_R_PT_REVA_LOOP ((uint32_t)0x00000008UL) /**< Offset from PT Base Address: <tt> 0x0008</tt> */ 91 #define MXC_R_PT_REVA_RESTART ((uint32_t)0x0000000CUL) /**< Offset from PT Base Address: <tt> 0x000C</tt> */ 92 /**@} end of group pt_registers */ 93 94 /** 95 * @ingroup pt_registers 96 * @defgroup PT_RATE_LENGTH PT_RATE_LENGTH 97 * @brief Pulse Train Configuration 98 * @{ 99 */ 100 #define MXC_F_PT_REVA_RATE_LENGTH_RATE_CONTROL_POS 0 /**< RATE_LENGTH_RATE_CONTROL Position */ 101 #define MXC_F_PT_REVA_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x7FFFFFFUL << MXC_F_PT_REVA_RATE_LENGTH_RATE_CONTROL_POS)) /**< RATE_LENGTH_RATE_CONTROL Mask */ 102 103 #define MXC_F_PT_REVA_RATE_LENGTH_MODE_POS 27 /**< RATE_LENGTH_MODE Position */ 104 #define MXC_F_PT_REVA_RATE_LENGTH_MODE ((uint32_t)(0x1FUL << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS)) /**< RATE_LENGTH_MODE Mask */ 105 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_32_BIT ((uint32_t)0x0UL) /**< RATE_LENGTH_MODE_32_BIT Value */ 106 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_32_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_32_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_32_BIT Setting */ 107 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)0x1UL) /**< RATE_LENGTH_MODE_SQUARE_WAVE Value */ 108 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_SQUARE_WAVE (MXC_V_PT_REVA_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_SQUARE_WAVE Setting */ 109 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_2_BIT ((uint32_t)0x2UL) /**< RATE_LENGTH_MODE_2_BIT Value */ 110 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_2_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_2_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_2_BIT Setting */ 111 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_3_BIT ((uint32_t)0x3UL) /**< RATE_LENGTH_MODE_3_BIT Value */ 112 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_3_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_3_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_3_BIT Setting */ 113 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_4_BIT ((uint32_t)0x4UL) /**< RATE_LENGTH_MODE_4_BIT Value */ 114 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_4_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_4_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_4_BIT Setting */ 115 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_5_BIT ((uint32_t)0x5UL) /**< RATE_LENGTH_MODE_5_BIT Value */ 116 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_5_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_5_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_5_BIT Setting */ 117 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_6_BIT ((uint32_t)0x6UL) /**< RATE_LENGTH_MODE_6_BIT Value */ 118 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_6_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_6_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_6_BIT Setting */ 119 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_7_BIT ((uint32_t)0x7UL) /**< RATE_LENGTH_MODE_7_BIT Value */ 120 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_7_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_7_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_7_BIT Setting */ 121 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_8_BIT ((uint32_t)0x8UL) /**< RATE_LENGTH_MODE_8_BIT Value */ 122 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_8_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_8_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_8_BIT Setting */ 123 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_9_BIT ((uint32_t)0x9UL) /**< RATE_LENGTH_MODE_9_BIT Value */ 124 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_9_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_9_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_9_BIT Setting */ 125 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_10_BIT ((uint32_t)0xAUL) /**< RATE_LENGTH_MODE_10_BIT Value */ 126 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_10_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_10_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_10_BIT Setting */ 127 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_11_BIT ((uint32_t)0xBUL) /**< RATE_LENGTH_MODE_11_BIT Value */ 128 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_11_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_11_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_11_BIT Setting */ 129 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_12_BIT ((uint32_t)0xCUL) /**< RATE_LENGTH_MODE_12_BIT Value */ 130 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_12_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_12_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_12_BIT Setting */ 131 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_13_BIT ((uint32_t)0xDUL) /**< RATE_LENGTH_MODE_13_BIT Value */ 132 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_13_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_13_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_13_BIT Setting */ 133 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_14_BIT ((uint32_t)0xEUL) /**< RATE_LENGTH_MODE_14_BIT Value */ 134 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_14_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_14_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_14_BIT Setting */ 135 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_15_BIT ((uint32_t)0xFUL) /**< RATE_LENGTH_MODE_15_BIT Value */ 136 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_15_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_15_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_15_BIT Setting */ 137 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_16_BIT ((uint32_t)0x10UL) /**< RATE_LENGTH_MODE_16_BIT Value */ 138 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_16_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_16_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_16_BIT Setting */ 139 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_17_BIT ((uint32_t)0x11UL) /**< RATE_LENGTH_MODE_17_BIT Value */ 140 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_17_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_17_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_17_BIT Setting */ 141 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_18_BIT ((uint32_t)0x12UL) /**< RATE_LENGTH_MODE_18_BIT Value */ 142 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_18_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_18_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_18_BIT Setting */ 143 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_19_BIT ((uint32_t)0x13UL) /**< RATE_LENGTH_MODE_19_BIT Value */ 144 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_19_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_19_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_19_BIT Setting */ 145 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_20_BIT ((uint32_t)0x14UL) /**< RATE_LENGTH_MODE_20_BIT Value */ 146 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_20_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_20_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_20_BIT Setting */ 147 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_21_BIT ((uint32_t)0x15UL) /**< RATE_LENGTH_MODE_21_BIT Value */ 148 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_21_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_21_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_21_BIT Setting */ 149 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_22_BIT ((uint32_t)0x16UL) /**< RATE_LENGTH_MODE_22_BIT Value */ 150 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_22_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_22_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_22_BIT Setting */ 151 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_23_BIT ((uint32_t)0x17UL) /**< RATE_LENGTH_MODE_23_BIT Value */ 152 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_23_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_23_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_23_BIT Setting */ 153 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_24_BIT ((uint32_t)0x18UL) /**< RATE_LENGTH_MODE_24_BIT Value */ 154 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_24_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_24_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_24_BIT Setting */ 155 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_25_BIT ((uint32_t)0x19UL) /**< RATE_LENGTH_MODE_25_BIT Value */ 156 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_25_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_25_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_25_BIT Setting */ 157 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_26_BIT ((uint32_t)0x1AUL) /**< RATE_LENGTH_MODE_26_BIT Value */ 158 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_26_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_26_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_26_BIT Setting */ 159 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_27_BIT ((uint32_t)0x1BUL) /**< RATE_LENGTH_MODE_27_BIT Value */ 160 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_27_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_27_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_27_BIT Setting */ 161 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_28_BIT ((uint32_t)0x1CUL) /**< RATE_LENGTH_MODE_28_BIT Value */ 162 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_28_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_28_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_28_BIT Setting */ 163 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_29_BIT ((uint32_t)0x1DUL) /**< RATE_LENGTH_MODE_29_BIT Value */ 164 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_29_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_29_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_29_BIT Setting */ 165 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_30_BIT ((uint32_t)0x1EUL) /**< RATE_LENGTH_MODE_30_BIT Value */ 166 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_30_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_30_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_30_BIT Setting */ 167 #define MXC_V_PT_REVA_RATE_LENGTH_MODE_31_BIT ((uint32_t)0x1FUL) /**< RATE_LENGTH_MODE_31_BIT Value */ 168 #define MXC_S_PT_REVA_RATE_LENGTH_MODE_31_BIT (MXC_V_PT_REVA_RATE_LENGTH_MODE_31_BIT << MXC_F_PT_REVA_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_31_BIT Setting */ 169 170 /**@} end of group PT_RATE_LENGTH_Register */ 171 172 /** 173 * @ingroup pt_registers 174 * @defgroup PT_LOOP PT_LOOP 175 * @brief Pulse Train Loop Count 176 * @{ 177 */ 178 #define MXC_F_PT_REVA_LOOP_COUNT_POS 0 /**< LOOP_COUNT Position */ 179 #define MXC_F_PT_REVA_LOOP_COUNT ((uint32_t)(0xFFFFUL << MXC_F_PT_REVA_LOOP_COUNT_POS)) /**< LOOP_COUNT Mask */ 180 181 #define MXC_F_PT_REVA_LOOP_DELAY_POS 16 /**< LOOP_DELAY Position */ 182 #define MXC_F_PT_REVA_LOOP_DELAY ((uint32_t)(0xFFFUL << MXC_F_PT_REVA_LOOP_DELAY_POS)) /**< LOOP_DELAY Mask */ 183 184 /**@} end of group PT_LOOP_Register */ 185 186 /** 187 * @ingroup pt_registers 188 * @defgroup PT_RESTART PT_RESTART 189 * @brief Pulse Train Auto-Restart Configuration. 190 * @{ 191 */ 192 #define MXC_F_PT_REVA_RESTART_PT_X_SELECT_POS 0 /**< RESTART_PT_REVA_X_SELECT Position */ 193 #define MXC_F_PT_REVA_RESTART_PT_X_SELECT ((uint32_t)(0x1FUL << MXC_F_PT_REVA_RESTART_PT_X_SELECT_POS)) /**< RESTART_PT_REVA_X_SELECT Mask */ 194 195 #define MXC_F_PT_REVA_RESTART_ON_PT_X_LOOP_EXIT_POS 7 /**< RESTART_ON_PT_REVA_X_LOOP_EXIT Position */ 196 #define MXC_F_PT_REVA_RESTART_ON_PT_X_LOOP_EXIT ((uint32_t)(0x1UL << MXC_F_PT_REVA_RESTART_ON_PT_X_LOOP_EXIT_POS)) /**< RESTART_ON_PT_REVA_X_LOOP_EXIT Mask */ 197 198 #define MXC_F_PT_REVA_RESTART_PT_Y_SELECT_POS 8 /**< RESTART_PT_REVA_Y_SELECT Position */ 199 #define MXC_F_PT_REVA_RESTART_PT_Y_SELECT ((uint32_t)(0x1FUL << MXC_F_PT_REVA_RESTART_PT_Y_SELECT_POS)) /**< RESTART_PT_REVA_Y_SELECT Mask */ 200 201 #define MXC_F_PT_REVA_RESTART_ON_PT_Y_LOOP_EXIT_POS 15 /**< RESTART_ON_PT_REVA_Y_LOOP_EXIT Position */ 202 #define MXC_F_PT_REVA_RESTART_ON_PT_Y_LOOP_EXIT ((uint32_t)(0x1UL << MXC_F_PT_REVA_RESTART_ON_PT_Y_LOOP_EXIT_POS)) /**< RESTART_ON_PT_REVA_Y_LOOP_EXIT Mask */ 203 204 /**@} end of group PT_RESTART_Register */ 205 206 #ifdef __cplusplus 207 } 208 #endif 209 210 #endif /* _PT_REVA_REGS_H_ */ 211
