1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include "pt.h"
22 #include "adc.h"
23 #include "gcr_regs.h"
24 #include "pt_regs.h"
25 #include "ptg_regs.h"
26 #include "pt_reva.h"
27
MXC_PT_Init(mxc_clk_scale_t clk_scale)28 void MXC_PT_Init(mxc_clk_scale_t clk_scale)
29 {
30 MXC_ASSERT(clk_scale <= 128);
31
32 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_PT);
33 MXC_SYS_Reset_Periph(MXC_SYS_RESET1_PT);
34
35 //set clock scale
36 MXC_GCR->clkctrl &= ~MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128;
37
38 switch (clk_scale) {
39 case MXC_PT_CLK_DIV1:
40 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1;
41 break;
42
43 case MXC_PT_CLK_DIV2:
44 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2;
45 break;
46
47 case MXC_PT_CLK_DIV4:
48 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4;
49 break;
50
51 case MXC_PT_CLK_DIV8:
52 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8;
53 break;
54
55 case MXC_PT_CLK_DIV16:
56 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16;
57 break;
58
59 case MXC_PT_CLK_DIV32:
60 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32;
61 break;
62
63 case MXC_PT_CLK_DIV64:
64 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64;
65 break;
66
67 case MXC_PT_CLK_DIV128:
68 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128;
69 break;
70 }
71
72 MXC_PT_RevA_Init((mxc_ptg_reva_regs_t *)MXC_PTG, clk_scale);
73 }
74
MXC_PT_Shutdown(uint32_t pts)75 void MXC_PT_Shutdown(uint32_t pts)
76 {
77 if (MXC_PT_RevA_Shutdown((mxc_ptg_reva_regs_t *)MXC_PTG, pts)) {
78 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_PT);
79 }
80 }
81
MXC_PT_Config(mxc_pt_cfg_t * cfg)82 int MXC_PT_Config(mxc_pt_cfg_t *cfg)
83 {
84 MXC_PT_RevA_Config((mxc_ptg_reva_regs_t *)MXC_PTG, cfg);
85
86 switch (cfg->channel) {
87 case 0:
88 MXC_GPIO_Config(&gpio_cfg_pt0);
89 break;
90
91 case 1:
92 MXC_GPIO_Config(&gpio_cfg_pt1);
93 break;
94
95 case 2:
96 MXC_GPIO_Config(&gpio_cfg_pt2);
97 break;
98
99 case 3:
100 MXC_GPIO_Config(&gpio_cfg_pt3);
101 break;
102
103 default:
104 return E_BAD_PARAM;
105 }
106
107 return E_NO_ERROR;
108 }
109
MXC_PT_SqrWaveConfig(unsigned channel,uint32_t freq)110 int MXC_PT_SqrWaveConfig(unsigned channel, uint32_t freq)
111 {
112 mxc_pt_cfg_t sqwcfg;
113
114 MXC_PT_RevA_SqrWaveConfig((mxc_ptg_reva_regs_t *)MXC_PTG, &sqwcfg, channel, freq);
115 return MXC_PT_Config(&sqwcfg);
116 }
117
MXC_PT_Start(unsigned pts)118 void MXC_PT_Start(unsigned pts)
119 {
120 MXC_PT_RevA_Start((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
121 }
122
MXC_PT_Stop(unsigned pts)123 void MXC_PT_Stop(unsigned pts)
124 {
125 MXC_PT_RevA_Stop((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
126 }
127
MXC_PT_IsActive(uint32_t pts)128 uint32_t MXC_PT_IsActive(uint32_t pts)
129 {
130 return MXC_PT_RevA_IsActive((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
131 }
132
MXC_PT_SetPattern(unsigned pts,uint32_t pattern)133 void MXC_PT_SetPattern(unsigned pts, uint32_t pattern)
134 {
135 MXC_PT_RevA_SetPattern(pts, pattern);
136 }
137
MXC_PT_EnableInt(uint32_t pts)138 void MXC_PT_EnableInt(uint32_t pts)
139 {
140 MXC_PT_RevA_EnableStopInt((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
141 }
142
MXC_PT_DisableInt(uint32_t pts)143 void MXC_PT_DisableInt(uint32_t pts)
144 {
145 MXC_PT_RevA_DisableStopInt((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
146 }
147
MXC_PT_GetFlags(void)148 uint32_t MXC_PT_GetFlags(void)
149 {
150 return MXC_PT_RevA_GetStopFlags((mxc_ptg_reva_regs_t *)MXC_PTG);
151 }
152
MXC_PT_ClearFlags(uint32_t flags)153 void MXC_PT_ClearFlags(uint32_t flags)
154 {
155 MXC_PT_RevA_ClearStopFlags((mxc_ptg_reva_regs_t *)MXC_PTG, flags);
156 }
157
MXC_PT_EnableRestart(unsigned start,unsigned stop,uint8_t restartIndex)158 void MXC_PT_EnableRestart(unsigned start, unsigned stop, uint8_t restartIndex)
159 {
160 MXC_PT_RevA_EnableRestart(start, stop, restartIndex);
161 }
162
MXC_PT_DisableRestart(unsigned channel,uint8_t restartIndex)163 void MXC_PT_DisableRestart(unsigned channel, uint8_t restartIndex)
164 {
165 MXC_PT_RevA_DisableRestart(channel, restartIndex);
166 }
167
MXC_PT_Resync(uint32_t pts)168 void MXC_PT_Resync(uint32_t pts)
169 {
170 MXC_PT_RevA_Resync((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
171 }
172
MXC_PT_EnableReadyInt(uint32_t pts)173 void MXC_PT_EnableReadyInt(uint32_t pts)
174 {
175 MXC_PT_RevA_EnableReadyInt((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
176 }
177
MXC_PT_DisableReadyInt(uint32_t pts)178 void MXC_PT_DisableReadyInt(uint32_t pts)
179 {
180 MXC_PT_RevA_DisableReadyInt((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
181 }
182
MXC_PT_GetReadyFlags(void)183 uint32_t MXC_PT_GetReadyFlags(void)
184 {
185 return MXC_PT_RevA_GetReadyFlags((mxc_ptg_reva_regs_t *)MXC_PTG);
186 }
187
MXC_PT_ClearReadyFlags(uint32_t flags)188 void MXC_PT_ClearReadyFlags(uint32_t flags)
189 {
190 MXC_PT_RevA_ClearReadyFlags((mxc_ptg_reva_regs_t *)MXC_PTG, flags);
191 }
192
