1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include "pt.h"
22 #include "gcr_regs.h"
23 #include "pt_regs.h"
24 #include "ptg_regs.h"
25 #include "pt_reva.h"
26
MXC_PT_Init(mxc_ptg_regs_t * ptg,mxc_clk_scale_t clk_scale)27 void MXC_PT_Init(mxc_ptg_regs_t *ptg, mxc_clk_scale_t clk_scale)
28 {
29 MXC_ASSERT(clk_scale <= 128);
30 MXC_GCR->perckcn0 &= ~MXC_F_GCR_PERCKCN0_PTD;
31
32 MXC_GCR->rstr1 |= MXC_F_GCR_RSTR1_PT;
33
34 while (MXC_GCR->rstr1 & MXC_F_GCR_RSTR1_PT) {}
35
36 //set clock scale
37 MXC_GCR->clkcn &= ~MXC_S_GCR_CLKCN_PSC_DIV128;
38
39 switch (clk_scale) {
40 case MXC_PT_CLK_DIV1:
41 MXC_GCR->clkcn |= MXC_S_GCR_CLKCN_PSC_DIV1;
42 break;
43
44 case MXC_PT_CLK_DIV2:
45 MXC_GCR->clkcn |= MXC_S_GCR_CLKCN_PSC_DIV2;
46 break;
47
48 case MXC_PT_CLK_DIV4:
49 MXC_GCR->clkcn |= MXC_S_GCR_CLKCN_PSC_DIV4;
50 break;
51
52 case MXC_PT_CLK_DIV8:
53 MXC_GCR->clkcn |= MXC_S_GCR_CLKCN_PSC_DIV8;
54 break;
55
56 case MXC_PT_CLK_DIV16:
57 MXC_GCR->clkcn |= MXC_S_GCR_CLKCN_PSC_DIV16;
58 break;
59
60 case MXC_PT_CLK_DIV32:
61 MXC_GCR->clkcn |= MXC_S_GCR_CLKCN_PSC_DIV32;
62 break;
63
64 case MXC_PT_CLK_DIV64:
65 MXC_GCR->clkcn |= MXC_S_GCR_CLKCN_PSC_DIV64;
66 break;
67
68 case MXC_PT_CLK_DIV128:
69 MXC_GCR->clkcn |= MXC_S_GCR_CLKCN_PSC_DIV128;
70 break;
71 }
72
73 MXC_PT_RevA_Init((mxc_ptg_reva_regs_t *)ptg, clk_scale);
74 }
75
MXC_PT_Shutdown(mxc_ptg_regs_t * ptg,uint32_t pts)76 void MXC_PT_Shutdown(mxc_ptg_regs_t *ptg, uint32_t pts)
77 {
78 if (MXC_PT_RevA_Shutdown((mxc_ptg_reva_regs_t *)ptg, pts)) {
79 MXC_GCR->perckcn0 |= MXC_F_GCR_PERCKCN0_PTD;
80 }
81 }
82
MXC_PT_Config(mxc_ptg_regs_t * ptg,mxc_pt_cfg_t * cfg)83 int MXC_PT_Config(mxc_ptg_regs_t *ptg, mxc_pt_cfg_t *cfg)
84 {
85 MXC_PT_RevA_Config((mxc_ptg_reva_regs_t *)ptg, cfg);
86
87 switch (cfg->channel) {
88 case 0:
89 MXC_GPIO_Config(&gpio_cfg_pt0);
90 break;
91
92 case 1:
93 MXC_GPIO_Config(&gpio_cfg_pt1);
94 break;
95
96 case 2:
97 MXC_GPIO_Config(&gpio_cfg_pt2);
98 break;
99
100 case 3:
101 MXC_GPIO_Config(&gpio_cfg_pt3);
102 break;
103
104 case 4:
105 MXC_GPIO_Config(&gpio_cfg_pt4);
106 break;
107
108 case 5:
109 MXC_GPIO_Config(&gpio_cfg_pt5);
110 break;
111
112 case 6:
113 MXC_GPIO_Config(&gpio_cfg_pt6);
114 break;
115
116 case 7:
117 MXC_GPIO_Config(&gpio_cfg_pt7);
118 break;
119
120 case 8:
121 MXC_GPIO_Config(&gpio_cfg_pt8);
122 break;
123
124 case 9:
125 MXC_GPIO_Config(&gpio_cfg_pt9);
126 break;
127
128 case 10:
129 MXC_GPIO_Config(&gpio_cfg_pt10);
130 break;
131
132 case 11:
133 MXC_GPIO_Config(&gpio_cfg_pt11);
134 break;
135
136 case 12:
137 MXC_GPIO_Config(&gpio_cfg_pt12);
138 break;
139
140 case 13:
141 MXC_GPIO_Config(&gpio_cfg_pt13);
142 break;
143
144 case 14:
145 MXC_GPIO_Config(&gpio_cfg_pt14);
146 break;
147
148 case 15:
149 MXC_GPIO_Config(&gpio_cfg_pt15);
150 break;
151
152 default:
153 return E_BAD_PARAM;
154 break;
155 }
156
157 return E_NO_ERROR;
158 }
159
MXC_PT_SqrWaveConfig(mxc_ptg_regs_t * ptg,unsigned channel,uint32_t freq)160 int MXC_PT_SqrWaveConfig(mxc_ptg_regs_t *ptg, unsigned channel, uint32_t freq)
161 {
162 mxc_pt_cfg_t sqwcfg;
163
164 MXC_PT_RevA_SqrWaveConfig((mxc_ptg_reva_regs_t *)ptg, &sqwcfg, channel, freq);
165 return MXC_PT_Config(ptg, &sqwcfg);
166 }
167
MXC_PT_Start(mxc_ptg_regs_t * ptg,unsigned pts)168 void MXC_PT_Start(mxc_ptg_regs_t *ptg, unsigned pts)
169 {
170 MXC_PT_RevA_Start((mxc_ptg_reva_regs_t *)ptg, pts);
171 }
172
MXC_PT_Stop(mxc_ptg_regs_t * ptg,unsigned pts)173 void MXC_PT_Stop(mxc_ptg_regs_t *ptg, unsigned pts)
174 {
175 MXC_PT_RevA_Stop((mxc_ptg_reva_regs_t *)ptg, pts);
176 }
177
MXC_PT_IsActive(mxc_ptg_regs_t * ptg,uint32_t pts)178 uint32_t MXC_PT_IsActive(mxc_ptg_regs_t *ptg, uint32_t pts)
179 {
180 return MXC_PT_RevA_IsActive((mxc_ptg_reva_regs_t *)ptg, pts);
181 }
182
MXC_PT_SetPattern(unsigned pts,uint32_t pattern)183 void MXC_PT_SetPattern(unsigned pts, uint32_t pattern)
184 {
185 MXC_PT_RevA_SetPattern(pts, pattern);
186 }
187
MXC_PT_EnableInt(mxc_ptg_regs_t * ptg,uint32_t pts)188 void MXC_PT_EnableInt(mxc_ptg_regs_t *ptg, uint32_t pts)
189 {
190 MXC_PT_RevA_EnableInt((mxc_ptg_reva_regs_t *)ptg, pts);
191 }
192
MXC_PT_DisableInt(mxc_ptg_regs_t * ptg,uint32_t pts)193 void MXC_PT_DisableInt(mxc_ptg_regs_t *ptg, uint32_t pts)
194 {
195 MXC_PT_RevA_DisableInt((mxc_ptg_reva_regs_t *)ptg, pts);
196 }
197
MXC_PT_GetFlags(mxc_ptg_regs_t * ptg)198 uint32_t MXC_PT_GetFlags(mxc_ptg_regs_t *ptg)
199 {
200 return MXC_PT_RevA_GetFlags((mxc_ptg_reva_regs_t *)ptg);
201 }
202
MXC_PT_ClearFlags(mxc_ptg_regs_t * ptg,uint32_t flags)203 void MXC_PT_ClearFlags(mxc_ptg_regs_t *ptg, uint32_t flags)
204 {
205 MXC_PT_RevA_ClearFlags((mxc_ptg_reva_regs_t *)ptg, flags);
206 }
207
MXC_PT_EnableRestart(unsigned start,unsigned stop,uint8_t restartIndex)208 void MXC_PT_EnableRestart(unsigned start, unsigned stop, uint8_t restartIndex)
209 {
210 MXC_PT_RevA_EnableRestart(start, stop, restartIndex);
211 }
212
MXC_PT_DisableRestart(unsigned channel,uint8_t restartIndex)213 void MXC_PT_DisableRestart(unsigned channel, uint8_t restartIndex)
214 {
215 MXC_PT_RevA_DisableRestart(channel, restartIndex);
216 }
217
MXC_PT_Resync(mxc_ptg_regs_t * ptg,uint32_t pts)218 void MXC_PT_Resync(mxc_ptg_regs_t *ptg, uint32_t pts)
219 {
220 MXC_PT_RevA_Resync((mxc_ptg_reva_regs_t *)ptg, pts);
221 }
222
