1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include "pt.h"
22 #include "adc.h"
23 #include "gcr_regs.h"
24 #include "pt_regs.h"
25 #include "ptg_regs.h"
26 #include "pt_reva.h"
27
MXC_PT_Init(mxc_clk_scale_t clk_scale)28 void MXC_PT_Init(mxc_clk_scale_t clk_scale)
29 {
30 MXC_ASSERT(clk_scale <= 128);
31
32 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_PT);
33 MXC_SYS_Reset_Periph(MXC_SYS_RESET1_PT);
34
35 //set clock scale
36 MXC_GCR->clkctrl &= ~MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128;
37
38 switch (clk_scale) {
39 case MXC_PT_CLK_DIV1:
40 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1;
41 break;
42
43 case MXC_PT_CLK_DIV2:
44 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2;
45 break;
46
47 case MXC_PT_CLK_DIV4:
48 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4;
49 break;
50
51 case MXC_PT_CLK_DIV8:
52 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8;
53 break;
54
55 case MXC_PT_CLK_DIV16:
56 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16;
57 break;
58
59 case MXC_PT_CLK_DIV32:
60 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32;
61 break;
62
63 case MXC_PT_CLK_DIV64:
64 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64;
65 break;
66
67 case MXC_PT_CLK_DIV128:
68 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128;
69 break;
70 }
71
72 MXC_PT_RevA_Init((mxc_ptg_reva_regs_t *)MXC_PTG, clk_scale);
73 }
74
MXC_PT_Shutdown(uint32_t pts)75 void MXC_PT_Shutdown(uint32_t pts)
76 {
77 if (MXC_PT_RevA_Shutdown((mxc_ptg_reva_regs_t *)MXC_PTG, pts)) {
78 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_PT);
79 }
80 }
81
MXC_PT_Config(mxc_pt_cfg_t * cfg)82 int MXC_PT_Config(mxc_pt_cfg_t *cfg)
83 {
84 MXC_PT_RevA_Config((mxc_ptg_reva_regs_t *)MXC_PTG, cfg);
85
86 switch (cfg->channel) {
87 case 0:
88 MXC_GPIO_Config(&gpio_cfg_pt0);
89 break;
90
91 case 1:
92 MXC_GPIO_Config(&gpio_cfg_pt1);
93 break;
94
95 case 2:
96 MXC_GPIO_Config(&gpio_cfg_pt2);
97 break;
98
99 case 3:
100 MXC_GPIO_Config(&gpio_cfg_pt3);
101 break;
102
103 case 4:
104 MXC_GPIO_Config(&gpio_cfg_pt4);
105 break;
106
107 case 5:
108 MXC_GPIO_Config(&gpio_cfg_pt5);
109 break;
110
111 case 6:
112 MXC_GPIO_Config(&gpio_cfg_pt6);
113 break;
114
115 case 7:
116 MXC_GPIO_Config(&gpio_cfg_pt7);
117 break;
118
119 default:
120 return E_BAD_PARAM;
121 break;
122 }
123
124 return E_NO_ERROR;
125 }
126
MXC_PT_SqrWaveConfig(unsigned channel,uint32_t freq)127 int MXC_PT_SqrWaveConfig(unsigned channel, uint32_t freq)
128 {
129 mxc_pt_cfg_t sqwcfg;
130
131 MXC_PT_RevA_SqrWaveConfig((mxc_ptg_reva_regs_t *)MXC_PTG, &sqwcfg, channel, freq);
132 return MXC_PT_Config(&sqwcfg);
133 }
134
MXC_PT_Start(unsigned pts)135 void MXC_PT_Start(unsigned pts)
136 {
137 MXC_PT_RevA_Start((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
138 }
139
MXC_PT_Stop(unsigned pts)140 void MXC_PT_Stop(unsigned pts)
141 {
142 MXC_PT_RevA_Stop((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
143 }
144
MXC_PT_IsActive(uint32_t pts)145 uint32_t MXC_PT_IsActive(uint32_t pts)
146 {
147 return MXC_PT_RevA_IsActive((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
148 }
149
MXC_PT_SetPattern(unsigned pts,uint32_t pattern)150 void MXC_PT_SetPattern(unsigned pts, uint32_t pattern)
151 {
152 MXC_PT_RevA_SetPattern(pts, pattern);
153 }
154
MXC_PT_EnableInt(uint32_t pts)155 void MXC_PT_EnableInt(uint32_t pts)
156 {
157 MXC_PT_RevA_EnableInt((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
158 }
159
MXC_PT_DisableInt(uint32_t pts)160 void MXC_PT_DisableInt(uint32_t pts)
161 {
162 MXC_PT_RevA_DisableInt((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
163 }
164
MXC_PT_GetFlags(void)165 uint32_t MXC_PT_GetFlags(void)
166 {
167 return MXC_PT_RevA_GetFlags((mxc_ptg_reva_regs_t *)MXC_PTG);
168 }
169
MXC_PT_ClearFlags(uint32_t flags)170 void MXC_PT_ClearFlags(uint32_t flags)
171 {
172 MXC_PT_RevA_ClearFlags((mxc_ptg_reva_regs_t *)MXC_PTG, flags);
173 }
174
MXC_PT_EnableRestart(unsigned start,unsigned stop,uint8_t restartIndex)175 void MXC_PT_EnableRestart(unsigned start, unsigned stop, uint8_t restartIndex)
176 {
177 MXC_PT_RevA_EnableRestart(start, stop, restartIndex);
178 }
179
MXC_PT_DisableRestart(unsigned channel,uint8_t restartIndex)180 void MXC_PT_DisableRestart(unsigned channel, uint8_t restartIndex)
181 {
182 MXC_PT_RevA_DisableRestart(channel, restartIndex);
183 }
184
MXC_PT_Resync(uint32_t pts)185 void MXC_PT_Resync(uint32_t pts)
186 {
187 MXC_PT_RevA_Resync((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
188 }
189
