1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include "mxc_sys.h"
22 #include "mxc_pins.h"
23 #include "gpio.h"
24 #include "pt.h"
25 #include "gcr_regs.h"
26 #include "pt_regs.h"
27 #include "ptg_regs.h"
28 #include "pt_reva.h"
29
MXC_PT_Init(mxc_clk_scale_t clk_scale)30 void MXC_PT_Init(mxc_clk_scale_t clk_scale)
31 {
32 MXC_ASSERT(clk_scale <= 128);
33
34 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_PT);
35 MXC_SYS_Reset_Periph(MXC_SYS_RESET1_PT);
36
37 //set clock scale
38 MXC_GCR->clkctrl &= ~MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128;
39
40 switch (clk_scale) {
41 case MXC_PT_CLK_DIV1:
42 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1;
43 break;
44
45 case MXC_PT_CLK_DIV2:
46 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2;
47 break;
48
49 case MXC_PT_CLK_DIV4:
50 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4;
51 break;
52
53 case MXC_PT_CLK_DIV8:
54 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8;
55 break;
56
57 case MXC_PT_CLK_DIV16:
58 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16;
59 break;
60
61 case MXC_PT_CLK_DIV32:
62 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32;
63 break;
64
65 case MXC_PT_CLK_DIV64:
66 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64;
67 break;
68
69 case MXC_PT_CLK_DIV128:
70 MXC_GCR->clkctrl |= MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128;
71 break;
72 }
73
74 MXC_PT_RevA_Init((mxc_ptg_reva_regs_t *)MXC_PTG, clk_scale);
75 }
76
MXC_PT_Shutdown(uint32_t pts)77 void MXC_PT_Shutdown(uint32_t pts)
78 {
79 if (MXC_PT_RevA_Shutdown((mxc_ptg_reva_regs_t *)MXC_PTG, pts)) {
80 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_PT);
81 }
82 }
83
MXC_PT_Config(mxc_pt_cfg_t * cfg)84 int MXC_PT_Config(mxc_pt_cfg_t *cfg)
85 {
86 MXC_PT_RevA_Config((mxc_ptg_reva_regs_t *)MXC_PTG, cfg);
87
88 switch (cfg->channel) {
89 case 0:
90 MXC_GPIO_Config(&gpio_cfg_pt0);
91 break;
92
93 case 1:
94 MXC_GPIO_Config(&gpio_cfg_pt1);
95 break;
96
97 case 2:
98 MXC_GPIO_Config(&gpio_cfg_pt2);
99 break;
100
101 case 3:
102 MXC_GPIO_Config(&gpio_cfg_pt3);
103 break;
104
105 default:
106 return E_BAD_PARAM;
107 }
108
109 return E_NO_ERROR;
110 }
111
MXC_PT_SqrWaveConfig(unsigned channel,uint32_t freq)112 int MXC_PT_SqrWaveConfig(unsigned channel, uint32_t freq)
113 {
114 mxc_pt_cfg_t sqwcfg;
115
116 MXC_PT_RevA_SqrWaveConfig((mxc_ptg_reva_regs_t *)MXC_PTG, &sqwcfg, channel, freq);
117 return MXC_PT_Config(&sqwcfg);
118 }
119
MXC_PT_Start(unsigned pts)120 void MXC_PT_Start(unsigned pts)
121 {
122 MXC_PT_RevA_Start((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
123 }
124
MXC_PT_Stop(unsigned pts)125 void MXC_PT_Stop(unsigned pts)
126 {
127 MXC_PT_RevA_Stop((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
128 }
129
MXC_PT_IsActive(uint32_t pts)130 uint32_t MXC_PT_IsActive(uint32_t pts)
131 {
132 return MXC_PT_RevA_IsActive((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
133 }
134
MXC_PT_SetPattern(unsigned pts,uint32_t pattern)135 void MXC_PT_SetPattern(unsigned pts, uint32_t pattern)
136 {
137 MXC_PT_RevA_SetPattern(pts, pattern);
138 }
139
MXC_PT_EnableStopInt(uint32_t pts)140 void MXC_PT_EnableStopInt(uint32_t pts)
141 {
142 MXC_PT_RevA_EnableStopInt((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
143 }
144
MXC_PT_DisableStopInt(uint32_t pts)145 void MXC_PT_DisableStopInt(uint32_t pts)
146 {
147 MXC_PT_RevA_DisableStopInt((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
148 }
149
MXC_PT_GetStopFlags(void)150 uint32_t MXC_PT_GetStopFlags(void)
151 {
152 return MXC_PT_RevA_GetStopFlags((mxc_ptg_reva_regs_t *)MXC_PTG);
153 }
154
MXC_PT_ClearStopFlags(uint32_t flags)155 void MXC_PT_ClearStopFlags(uint32_t flags)
156 {
157 MXC_PT_RevA_ClearStopFlags((mxc_ptg_reva_regs_t *)MXC_PTG, flags);
158 }
159
MXC_PT_EnableRestart(unsigned start,unsigned stop,uint8_t restartIndex)160 void MXC_PT_EnableRestart(unsigned start, unsigned stop, uint8_t restartIndex)
161 {
162 MXC_PT_RevA_EnableRestart(start, stop, restartIndex);
163 }
164
MXC_PT_DisableRestart(unsigned channel,uint8_t restartIndex)165 void MXC_PT_DisableRestart(unsigned channel, uint8_t restartIndex)
166 {
167 MXC_PT_RevA_DisableRestart(channel, restartIndex);
168 }
169
MXC_PT_Resync(uint32_t pts)170 void MXC_PT_Resync(uint32_t pts)
171 {
172 MXC_PT_RevA_Resync((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
173 }
174
MXC_PT_EnableReadyInt(uint32_t pts)175 void MXC_PT_EnableReadyInt(uint32_t pts)
176 {
177 MXC_PT_RevA_EnableReadyInt((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
178 }
179
MXC_PT_DisableReadyInt(uint32_t pts)180 void MXC_PT_DisableReadyInt(uint32_t pts)
181 {
182 MXC_PT_RevA_DisableReadyInt((mxc_ptg_reva_regs_t *)MXC_PTG, pts);
183 }
184
MXC_PT_GetReadyFlags(void)185 uint32_t MXC_PT_GetReadyFlags(void)
186 {
187 return MXC_PT_RevA_GetReadyFlags((mxc_ptg_reva_regs_t *)MXC_PTG);
188 }
189
MXC_PT_ClearReadyFlags(uint32_t flags)190 void MXC_PT_ClearReadyFlags(uint32_t flags)
191 {
192 MXC_PT_RevA_ClearReadyFlags((mxc_ptg_reva_regs_t *)MXC_PTG, flags);
193 }
194
