1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>PWRSEQ</name> 5 <description>Power Sequencer / Low Power Control Register.</description> 6 <baseAddress>0x40006800</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>LPCTRL</name> 15 <description>Low Power Control Register.</description> 16 <addressOffset>0x00</addressOffset> 17 <fields> 18 <field> 19 <name>RAMRET_EN</name> 20 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>4</bitWidth> 23 </field> 24 <field> 25 <name>OVR</name> 26 <description>Operating Voltage Range</description> 27 <bitOffset>4</bitOffset> 28 <bitWidth>2</bitWidth> 29 <enumeratedValues> 30 <enumeratedValue> 31 <name>1_1V</name> 32 <description>1.1V</description> 33 <value>2</value> 34 </enumeratedValue> 35 </enumeratedValues> 36 </field> 37 <field> 38 <name>RETREG_EN</name> 39 <description>Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. </description> 40 <bitOffset>8</bitOffset> 41 <bitWidth>1</bitWidth> 42 <enumeratedValues> 43 <enumeratedValue> 44 <name>dis</name> 45 <description>Disabled.</description> 46 <value>0</value> 47 </enumeratedValue> 48 <enumeratedValue> 49 <name>en</name> 50 <description>Enabled.</description> 51 <value>1</value> 52 </enumeratedValue> 53 </enumeratedValues> 54 </field> 55 <field> 56 <name>FASTWK_EN</name> 57 <description>Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). </description> 58 <bitOffset>10</bitOffset> 59 <bitWidth>1</bitWidth> 60 <enumeratedValues> 61 <enumeratedValue> 62 <name>dis</name> 63 <description>Disabled.</description> 64 <value>0</value> 65 </enumeratedValue> 66 <enumeratedValue> 67 <name>en</name> 68 <description>Enabled.</description> 69 <value>1</value> 70 </enumeratedValue> 71 </enumeratedValues> 72 </field> 73 <field> 74 <name>BGOFF</name> 75 <description>Bandgap OFF. This controls the System Bandgap in DeepSleep mode.</description> 76 <bitOffset>11</bitOffset> 77 <bitWidth>1</bitWidth> 78 <enumeratedValues> 79 <enumeratedValue> 80 <name>on</name> 81 <description>Bandgap is always ON.</description> 82 <value>0</value> 83 </enumeratedValue> 84 <enumeratedValue> 85 <name>off</name> 86 <description>Bandgap is OFF in DeepSleep mode (default).</description> 87 <value>1</value> 88 </enumeratedValue> 89 </enumeratedValues> 90 </field> 91 <field> 92 <name>VCOREPOR_DIS</name> 93 <description>VCore Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode.</description> 94 <bitOffset>12</bitOffset> 95 <bitWidth>1</bitWidth> 96 <enumeratedValues> 97 <enumeratedValue> 98 <name>dis</name> 99 <description>Disabled.</description> 100 <value>0</value> 101 </enumeratedValue> 102 <enumeratedValue> 103 <name>en</name> 104 <description>Enabled.</description> 105 <value>1</value> 106 </enumeratedValue> 107 </enumeratedValues> 108 </field> 109 <field> 110 <name>VDDIOHHVMON_DIS</name> 111 <description>VDDIOH High Voltage Monitor Disable.</description> 112 <bitOffset>17</bitOffset> 113 <bitWidth>1</bitWidth> 114 <enumeratedValues> 115 <enumeratedValue> 116 <name>en</name> 117 <description>Enable if Bandgap is ON (default) </description> 118 <value>0</value> 119 </enumeratedValue> 120 <enumeratedValue> 121 <name>dis</name> 122 <description>Disabled.</description> 123 <value>1</value> 124 </enumeratedValue> 125 </enumeratedValues> 126 </field> 127 <field> 128 <name>VDDIOHVMON_DIS</name> 129 <description>VDDIO High Voltage Monitor Disable.</description> 130 <bitOffset>18</bitOffset> 131 <bitWidth>1</bitWidth> 132 <enumeratedValues> 133 <enumeratedValue> 134 <name>en</name> 135 <description>Enable if Bandgap is ON (default) </description> 136 <value>0</value> 137 </enumeratedValue> 138 <enumeratedValue> 139 <name>dis</name> 140 <description>Disabled.</description> 141 <value>1</value> 142 </enumeratedValue> 143 </enumeratedValues> 144 </field> 145 <field> 146 <name>VCOREHVMON_DIS</name> 147 <description>VCORE High Voltage Monitor Disable.</description> 148 <bitOffset>19</bitOffset> 149 <bitWidth>1</bitWidth> 150 <enumeratedValues> 151 <enumeratedValue> 152 <name>en</name> 153 <description>Enable if Bandgap is ON (default) </description> 154 <value>0</value> 155 </enumeratedValue> 156 <enumeratedValue> 157 <name>dis</name> 158 <description>Disabled.</description> 159 <value>1</value> 160 </enumeratedValue> 161 </enumeratedValues> 162 </field> 163 <field> 164 <name>VCOREMON_DIS</name> 165 <description>Vcore Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes.</description> 166 <bitOffset>20</bitOffset> 167 <bitWidth>1</bitWidth> 168 <enumeratedValues> 169 <enumeratedValue> 170 <name>en</name> 171 <description>Enable if Bandgap is ON (default) </description> 172 <value>0</value> 173 </enumeratedValue> 174 <enumeratedValue> 175 <name>dis</name> 176 <description>Disabled.</description> 177 <value>1</value> 178 </enumeratedValue> 179 </enumeratedValues> 180 </field> 181 <field> 182 <name>VRTCMON_DIS</name> 183 <description>VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes.</description> 184 <bitOffset>21</bitOffset> 185 <bitWidth>1</bitWidth> 186 <enumeratedValues> 187 <enumeratedValue> 188 <name>en</name> 189 <description>Enable if Bandgap is ON (default) </description> 190 <value>0</value> 191 </enumeratedValue> 192 <enumeratedValue> 193 <name>dis</name> 194 <description>Disabled.</description> 195 <value>1</value> 196 </enumeratedValue> 197 </enumeratedValues> 198 </field> 199 <field> 200 <name>VDDAMON_DIS</name> 201 <description>VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 202 <bitOffset>22</bitOffset> 203 <bitWidth>1</bitWidth> 204 <enumeratedValues> 205 <enumeratedValue> 206 <name>en</name> 207 <description>Enable if Bandgap is ON (default) </description> 208 <value>0</value> 209 </enumeratedValue> 210 <enumeratedValue> 211 <name>dis</name> 212 <description>Disabled.</description> 213 <value>1</value> 214 </enumeratedValue> 215 </enumeratedValues> 216 </field> 217 <field> 218 <name>VDDIOMON_DIS</name> 219 <description>VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 220 <bitOffset>23</bitOffset> 221 <bitWidth>1</bitWidth> 222 <enumeratedValues> 223 <enumeratedValue> 224 <name>en</name> 225 <description>Enable if Bandgap is ON (default) </description> 226 <value>0</value> 227 </enumeratedValue> 228 <enumeratedValue> 229 <name>dis</name> 230 <description>Disabled.</description> 231 <value>1</value> 232 </enumeratedValue> 233 </enumeratedValues> 234 </field> 235 <field> 236 <name>VDDIOHMON_DIS</name> 237 <description>VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 238 <bitOffset>24</bitOffset> 239 <bitWidth>1</bitWidth> 240 <enumeratedValues> 241 <enumeratedValue> 242 <name>en</name> 243 <description>Enable if Bandgap is ON (default) </description> 244 <value>0</value> 245 </enumeratedValue> 246 <enumeratedValue> 247 <name>dis</name> 248 <description>Disabled.</description> 249 <value>1</value> 250 </enumeratedValue> 251 </enumeratedValues> 252 </field> 253 <field> 254 <name>VDDBMON_DIS</name> 255 <description>VDDB Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods.</description> 256 <bitOffset>27</bitOffset> 257 <bitWidth>1</bitWidth> 258 <enumeratedValues> 259 <enumeratedValue> 260 <name>dis</name> 261 <description>Disabled.</description> 262 <value>0</value> 263 </enumeratedValue> 264 <enumeratedValue> 265 <name>en</name> 266 <description>Enabled.</description> 267 <value>1</value> 268 </enumeratedValue> 269 </enumeratedValues> 270 </field> 271 <field> 272 <name>DEEPSLEEP_PDOUT_DIS</name> 273 <description>PDOWN out enable in DEEPSLEEP mode.</description> 274 <bitOffset>30</bitOffset> 275 <bitWidth>1</bitWidth> 276 </field> 277 </fields> 278 </register> 279 <register> 280 <name>LPWKFL0</name> 281 <description>Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.</description> 282 <addressOffset>0x04</addressOffset> 283 <fields> 284 <field> 285 <name>WAKEST</name> 286 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 287 <bitOffset>0</bitOffset> 288 <bitWidth>1</bitWidth> 289 </field> 290 </fields> 291 </register> 292 <register> 293 <name>LPWKEN0</name> 294 <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description> 295 <addressOffset>0x08</addressOffset> 296 <fields> 297 <field> 298 <name>WAKEEN</name> 299 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 300 <bitOffset>0</bitOffset> 301 <bitWidth>31</bitWidth> 302 </field> 303 </fields> 304 </register> 305 <register derivedFrom="LPWKFL0"> 306 <name>LPWKFL1</name> 307 <description>Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.</description> 308 <addressOffset>0x0C</addressOffset> 309 </register> 310 <register derivedFrom="LPWKEN0"> 311 <name>LPWKEN1</name> 312 <description>Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.</description> 313 <addressOffset>0x10</addressOffset> 314 </register> 315 <register derivedFrom="LPWKFL0"> 316 <name>LPWKFL2</name> 317 <description>Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2.</description> 318 <addressOffset>0x14</addressOffset> 319 </register> 320 <register derivedFrom="LPWKEN0"> 321 <name>LPWKEN2</name> 322 <description>Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2.</description> 323 <addressOffset>0x18</addressOffset> 324 </register> 325 <register derivedFrom="LPWKFL0"> 326 <name>LPWKFL3</name> 327 <description>Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3.</description> 328 <addressOffset>0x1C</addressOffset> 329 </register> 330 <register derivedFrom="LPWKEN0"> 331 <name>LPWKEN3</name> 332 <description>Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3.</description> 333 <addressOffset>0x20</addressOffset> 334 </register> 335 <register> 336 <name>LPPWKFL</name> 337 <description>Low Power Peripheral Wakeup Status Register.</description> 338 <addressOffset>0x30</addressOffset> 339 <fields> 340 <field> 341 <name>USBLS</name> 342 <description>USB UTMI Linestate Detect Wakeup Flag (write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN.</description> 343 <bitOffset>0</bitOffset> 344 <bitWidth>2</bitWidth> 345 </field> 346 <field> 347 <name>USBVBUS</name> 348 <description>USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off.</description> 349 <bitOffset>2</bitOffset> 350 <bitWidth>1</bitWidth> 351 </field> 352 <field> 353 <name>CPU1</name> 354 <description>CPU1 Detect Wakeup Flag (wite one to clear). This bit will be set when the SDMA IRQ transitions from low to high, or high to low.</description> 355 <bitOffset>3</bitOffset> 356 <bitWidth>1</bitWidth> 357 </field> 358 <field> 359 <name>BACKUP</name> 360 <description>Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode.</description> 361 <bitOffset>16</bitOffset> 362 <bitWidth>1</bitWidth> 363 </field> 364 <field> 365 <name>RESET</name> 366 <description>Reset Detect Wakeup Flag (write one to clear). This bit will be set when the external reset causes wakeup</description> 367 <bitOffset>17</bitOffset> 368 <bitWidth>1</bitWidth> 369 </field> 370 <field> 371 <name>DRS_EVT</name> 372 <description>Tamper Detext Status. Can only be cleared with a system reset.</description> 373 <bitOffset>19</bitOffset> 374 <bitWidth>1</bitWidth> 375 </field> 376 </fields> 377 </register> 378 <register> 379 <name>LPPWKEN</name> 380 <description>Low Power Peripheral Wakeup Enable Register.</description> 381 <addressOffset>0x34</addressOffset> 382 <fields> 383 <field> 384 <name>USBLS</name> 385 <description>USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal (s) on transition (s) from low to high or high to low when PM.USBWKEN is set.</description> 386 <bitOffset>0</bitOffset> 387 <bitWidth>2</bitWidth> 388 </field> 389 <field> 390 <name>USBVBUS</name> 391 <description>USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status.</description> 392 <bitOffset>2</bitOffset> 393 <bitWidth>1</bitWidth> 394 </field> 395 <field> 396 <name>CPU1</name> 397 <description>CPU1 Wakeup Enable.</description> 398 <bitOffset>3</bitOffset> 399 <bitWidth>1</bitWidth> 400 </field> 401 </fields> 402 </register> 403 <register> 404 <name>LPMEMSD</name> 405 <description>Low Power Memory Shutdown Control.</description> 406 <addressOffset>0x40</addressOffset> 407 <fields> 408 <field> 409 <name>RAM0</name> 410 <description>System RAM block 0 Shut Down.</description> 411 <bitOffset>0</bitOffset> 412 <bitWidth>1</bitWidth> 413 <enumeratedValues> 414 <enumeratedValue> 415 <name>normal</name> 416 <description>Normal Operating Mode.</description> 417 <value>0</value> 418 </enumeratedValue> 419 <enumeratedValue> 420 <name>shutdown</name> 421 <description>Shutdown Mode.</description> 422 <value>1</value> 423 </enumeratedValue> 424 </enumeratedValues> 425 </field> 426 <field> 427 <name>RAM1</name> 428 <description>System RAM block 1 Shut Down.</description> 429 <bitOffset>1</bitOffset> 430 <bitWidth>1</bitWidth> 431 <enumeratedValues> 432 <enumeratedValue> 433 <name>normal</name> 434 <description>Normal Operating Mode.</description> 435 <value>0</value> 436 </enumeratedValue> 437 <enumeratedValue> 438 <name>shutdown</name> 439 <description>Shutdown Mode.</description> 440 <value>1</value> 441 </enumeratedValue> 442 </enumeratedValues> 443 </field> 444 <field> 445 <name>RAM2</name> 446 <description>System RAM block 2 Shut Down.</description> 447 <bitOffset>2</bitOffset> 448 <bitWidth>1</bitWidth> 449 <enumeratedValues> 450 <enumeratedValue> 451 <name>normal</name> 452 <description>Normal Operating Mode.</description> 453 <value>0</value> 454 </enumeratedValue> 455 <enumeratedValue> 456 <name>shutdown</name> 457 <description>Shutdown Mode.</description> 458 <value>1</value> 459 </enumeratedValue> 460 </enumeratedValues> 461 </field> 462 <field> 463 <name>RAM3</name> 464 <description>System RAM block 3 Shut Down.</description> 465 <bitOffset>3</bitOffset> 466 <bitWidth>1</bitWidth> 467 <enumeratedValues> 468 <enumeratedValue> 469 <name>normal</name> 470 <description>Normal Operating Mode.</description> 471 <value>0</value> 472 </enumeratedValue> 473 <enumeratedValue> 474 <name>shutdown</name> 475 <description>Shutdown Mode.</description> 476 <value>1</value> 477 </enumeratedValue> 478 </enumeratedValues> 479 </field> 480 <field> 481 <name>RAM4</name> 482 <description>System RAM block 4 Shut Down.</description> 483 <bitOffset>4</bitOffset> 484 <bitWidth>1</bitWidth> 485 <enumeratedValues> 486 <enumeratedValue> 487 <name>normal</name> 488 <description>Normal Operating Mode.</description> 489 <value>0</value> 490 </enumeratedValue> 491 <enumeratedValue> 492 <name>shutdown</name> 493 <description>Shutdown Mode.</description> 494 <value>1</value> 495 </enumeratedValue> 496 </enumeratedValues> 497 </field> 498 <field> 499 <name>RAM5</name> 500 <description>System RAM block 5 Shut Down.</description> 501 <bitOffset>5</bitOffset> 502 <bitWidth>1</bitWidth> 503 <enumeratedValues> 504 <enumeratedValue> 505 <name>normal</name> 506 <description>Normal Operating Mode.</description> 507 <value>0</value> 508 </enumeratedValue> 509 <enumeratedValue> 510 <name>shutdown</name> 511 <description>Shutdown Mode.</description> 512 <value>1</value> 513 </enumeratedValue> 514 </enumeratedValues> 515 </field> 516 <field> 517 <name>RAM6</name> 518 <description>System RAM block 6 Shut Down.</description> 519 <bitOffset>6</bitOffset> 520 <bitWidth>1</bitWidth> 521 <enumeratedValues> 522 <enumeratedValue> 523 <name>normal</name> 524 <description>Normal Operating Mode.</description> 525 <value>0</value> 526 </enumeratedValue> 527 <enumeratedValue> 528 <name>shutdown</name> 529 <description>Shutdown Mode.</description> 530 <value>1</value> 531 </enumeratedValue> 532 </enumeratedValues> 533 </field> 534 <field> 535 <name>ICCXIP</name> 536 <description>XiP Instruction Cache RAM Shut Down.</description> 537 <bitOffset>8</bitOffset> 538 <bitWidth>1</bitWidth> 539 <enumeratedValues> 540 <enumeratedValue> 541 <name>normal</name> 542 <description>Normal Operating Mode.</description> 543 <value>0</value> 544 </enumeratedValue> 545 <enumeratedValue> 546 <name>shutdown</name> 547 <description>Shutdown Mode.</description> 548 <value>1</value> 549 </enumeratedValue> 550 </enumeratedValues> 551 </field> 552 <field> 553 <name>CRYPTO</name> 554 <description>MAA memory Shut Down.</description> 555 <bitOffset>10</bitOffset> 556 <bitWidth>1</bitWidth> 557 <enumeratedValues> 558 <enumeratedValue> 559 <name>normal</name> 560 <description>Normal Operating Mode.</description> 561 <value>0</value> 562 </enumeratedValue> 563 <enumeratedValue> 564 <name>shutdown</name> 565 <description>Shutdown Mode.</description> 566 <value>1</value> 567 </enumeratedValue> 568 </enumeratedValues> 569 </field> 570 <field> 571 <name>USBFIFO</name> 572 <description>USB FIFO Shut Down.</description> 573 <bitOffset>11</bitOffset> 574 <bitWidth>1</bitWidth> 575 <enumeratedValues> 576 <enumeratedValue> 577 <name>normal</name> 578 <description>Normal Operating Mode.</description> 579 <value>0</value> 580 </enumeratedValue> 581 <enumeratedValue> 582 <name>shutdown</name> 583 <description>Shutdown Mode.</description> 584 <value>1</value> 585 </enumeratedValue> 586 </enumeratedValues> 587 </field> 588 <field> 589 <name>ROM0</name> 590 <description>ROM0 Shut Down.</description> 591 <bitOffset>12</bitOffset> 592 <bitWidth>1</bitWidth> 593 <enumeratedValues> 594 <enumeratedValue> 595 <name>normal</name> 596 <description>Normal Operating Mode.</description> 597 <value>0</value> 598 </enumeratedValue> 599 <enumeratedValue> 600 <name>shutdown</name> 601 <description>Shutdown Mode.</description> 602 <value>1</value> 603 </enumeratedValue> 604 </enumeratedValues> 605 </field> 606 <field> 607 <name>MEUMEM</name> 608 <description>MEU memory Shut Down.</description> 609 <bitOffset>13</bitOffset> 610 <bitWidth>1</bitWidth> 611 <enumeratedValues> 612 <enumeratedValue> 613 <name>normal</name> 614 <description>Normal Operating Mode.</description> 615 <value>0</value> 616 </enumeratedValue> 617 <enumeratedValue> 618 <name>shutdown</name> 619 <description>Shutdown Mode.</description> 620 <value>1</value> 621 </enumeratedValue> 622 </enumeratedValues> 623 </field> 624 <field> 625 <name>ROM1</name> 626 <description>ROM1 Shut Down.</description> 627 <bitOffset>15</bitOffset> 628 <bitWidth>1</bitWidth> 629 <enumeratedValues> 630 <enumeratedValue> 631 <name>normal</name> 632 <description>Normal Operating Mode.</description> 633 <value>0</value> 634 </enumeratedValue> 635 <enumeratedValue> 636 <name>shutdown</name> 637 <description>Shutdown Mode.</description> 638 <value>1</value> 639 </enumeratedValue> 640 </enumeratedValues> 641 </field> 642 </fields> 643 </register> 644 <register> 645 <name>LPVDDPD</name> 646 <description>Low Power VDD Domain Power Down Control.</description> 647 <addressOffset>0x44</addressOffset> 648 </register> 649 <register> 650 <name>GP0</name> 651 <description>General Purpose Register 0</description> 652 <addressOffset>0x48</addressOffset> 653 </register> 654 <register> 655 <name>GP1</name> 656 <description>General Purpose Register 1</description> 657 <addressOffset>0x4C</addressOffset> 658 </register> 659 </registers> 660 </peripheral> 661 <!-- PWRSEQ: Power sequencer --> 662</device>
