1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>PWRSEQ</name> 5 <description>Power Sequencer / Low Power Control Register.</description> 6 <baseAddress>0x40106800</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> <!-- LPCN Register --> 14 <name>LPCN</name> 15 <description>Low Power Control Register.</description> 16 <addressOffset>0x00</addressOffset> 17 <fields> 18 <field> 19 <name>RAM0RET_EN</name> 20 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>1</bitWidth> 23 <access>read-write</access> 24 <enumeratedValues> 25 <enumeratedValue> 26 <name>dis</name> 27 <description>Disable Ram Retention.</description> 28 <value>0</value> 29 </enumeratedValue> 30 <enumeratedValue> 31 <name>en</name> 32 <description>Enable System RAM 0 retention.</description> 33 <value>1</value> 34 </enumeratedValue> 35 </enumeratedValues> 36 </field> 37 <field> 38 <name>RAM1RET_EN</name> 39 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 40 <bitOffset>1</bitOffset> 41 <bitWidth>1</bitWidth> 42 <access>read-write</access> 43 <enumeratedValues> 44 <enumeratedValue> 45 <name>dis</name> 46 <description>Disable Ram Retention.</description> 47 <value>0</value> 48 </enumeratedValue> 49 <enumeratedValue> 50 <name>en</name> 51 <description>Enable System RAM 1 retention.</description> 52 <value>1</value> 53 </enumeratedValue> 54 </enumeratedValues> 55 </field> 56 <field> 57 <name>RAM2RET_EN</name> 58 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 59 <bitOffset>2</bitOffset> 60 <bitWidth>1</bitWidth> 61 <access>read-write</access> 62 <enumeratedValues> 63 <enumeratedValue> 64 <name>dis</name> 65 <description>Disable Ram Retention.</description> 66 <value>0</value> 67 </enumeratedValue> 68 <enumeratedValue> 69 <name>en</name> 70 <description>Enable System RAM 2 retention.</description> 71 <value>1</value> 72 </enumeratedValue> 73 </enumeratedValues> 74 </field> 75 <field> 76 <name>RAM3RET_EN</name> 77 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 78 <bitOffset>3</bitOffset> 79 <bitWidth>1</bitWidth> 80 <access>read-write</access> 81 <enumeratedValues> 82 <enumeratedValue> 83 <name>dis</name> 84 <description>Disable Ram Retention.</description> 85 <value>0</value> 86 </enumeratedValue> 87 <enumeratedValue> 88 <name>en</name> 89 <description>Enable System RAM 3 retention.</description> 90 <value>1</value> 91 </enumeratedValue> 92 </enumeratedValues> 93 </field> 94 <field> 95 <name>OVR</name> 96 <description>Operating Voltage Range</description> 97 <bitOffset>4</bitOffset> 98 <bitWidth>2</bitWidth> 99 <access>read-write</access> 100 <enumeratedValues> 101 <enumeratedValue> 102 <name>0_9V</name> 103 <description>0.9V 12MHz</description> 104 <value>0</value> 105 </enumeratedValue> 106 <enumeratedValue> 107 <name>1_0V</name> 108 <description>1.0V 48MHz</description> 109 <value>1</value> 110 </enumeratedValue> 111 <enumeratedValue> 112 <name>1_1V</name> 113 <description>1.1V 96MHz</description> 114 <value>2</value> 115 </enumeratedValue> 116 </enumeratedValues> 117 </field> 118 <field> 119 <name>VCORE_DET_BYPASS</name> 120 <description>Block Auto-Detect</description> 121 <bitOffset>6</bitOffset> 122 <bitWidth>1</bitWidth> 123 <access>read-write</access> 124 <enumeratedValues> 125 <enumeratedValue> 126 <name>en</name> 127 <description>enable</description> 128 <value>0</value> 129 </enumeratedValue> 130 <enumeratedValue> 131 <name>dis</name> 132 <description>disable</description> 133 <value>1</value> 134 </enumeratedValue> 135 </enumeratedValues> 136 </field> 137 <field> 138 <name>FVDDEN</name> 139 <description>Flash VDD Enable, force the flash VDD to remain enabled during LP modes.</description> 140 <bitOffset>7</bitOffset> 141 <bitWidth>1</bitWidth> 142 <access>read-write</access> 143 <enumeratedValues> 144 <enumeratedValue> 145 <name>dis</name> 146 <description>enable</description> 147 <value>0</value> 148 </enumeratedValue> 149 <enumeratedValue> 150 <name>en</name> 151 <description>disable</description> 152 <value>1</value> 153 </enumeratedValue> 154 </enumeratedValues> 155 </field> 156 <field> 157 <name>RETREG_EN</name> 158 <description>Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. </description> 159 <bitOffset>8</bitOffset> 160 <bitWidth>1</bitWidth> 161 <access>read-write</access> 162 <enumeratedValues> 163 <enumeratedValue> 164 <name>dis</name> 165 <description>Disabled.</description> 166 <value>0</value> 167 </enumeratedValue> 168 <enumeratedValue> 169 <name>en</name> 170 <description>Enabled.</description> 171 <value>1</value> 172 </enumeratedValue> 173 </enumeratedValues> 174 </field> 175 <field> 176 <name>STORAGE_EN</name> 177 <description>STORAGE Mode ENable. This bit allows low-power background mode operations, while the CPU is in DeepSleep.</description> 178 <bitOffset>9</bitOffset> 179 <bitWidth>1</bitWidth> 180 <access>read-write</access> 181 <enumeratedValues> 182 <enumeratedValue> 183 <name>dis</name> 184 <description>Disabled.</description> 185 <value>0</value> 186 </enumeratedValue> 187 <enumeratedValue> 188 <name>en</name> 189 <description>Enabled.</description> 190 <value>1</value> 191 </enumeratedValue> 192 </enumeratedValues> 193 </field> 194 <field> 195 <name>FASTWK_EN</name> 196 <description>Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). </description> 197 <bitOffset>10</bitOffset> 198 <bitWidth>1</bitWidth> 199 <access>read-write</access> 200 <enumeratedValues> 201 <enumeratedValue> 202 <name>dis</name> 203 <description>Disabled.</description> 204 <value>0</value> 205 </enumeratedValue> 206 <enumeratedValue> 207 <name>en</name> 208 <description>Enabled.</description> 209 <value>1</value> 210 </enumeratedValue> 211 </enumeratedValues> 212 </field> 213 <field> 214 <name>BG_DIS</name> 215 <description>Bandgap OFF. This controls the System Bandgap in DeepSleep mode.</description> 216 <bitOffset>11</bitOffset> 217 <bitWidth>1</bitWidth> 218 <access>read-write</access> 219 <enumeratedValues> 220 <enumeratedValue> 221 <name>on</name> 222 <description>Bandgap is always ON.</description> 223 <value>0</value> 224 </enumeratedValue> 225 <enumeratedValue> 226 <name>off</name> 227 <description>Bandgap is OFF in DeepSleep mode (default).</description> 228 <value>1</value> 229 </enumeratedValue> 230 </enumeratedValues> 231 </field> 232 <field> 233 <name>VCOREPOR_DIS</name> 234 <description>VDDC (Vcore) Power on reset Monitor Disable.This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode.</description> 235 <bitOffset>12</bitOffset> 236 <bitWidth>1</bitWidth> 237 <access>read-write</access> 238 <enumeratedValues> 239 <enumeratedValue> 240 <name>en</name> 241 <description>Enable</description> 242 <value>0</value> 243 </enumeratedValue> 244 <enumeratedValue> 245 <name>dis</name> 246 <description>Disabled.</description> 247 <value>1</value> 248 </enumeratedValue> 249 </enumeratedValues> 250 </field> 251 <field> 252 <name>LDO_DIS</name> 253 <description>Disable Main LDO</description> 254 <bitOffset>16</bitOffset> 255 <bitWidth>1</bitWidth> 256 <access>read-write</access> 257 <enumeratedValues> 258 <enumeratedValue> 259 <name>en</name> 260 <description>Enable </description> 261 <value>0</value> 262 </enumeratedValue> 263 <enumeratedValue> 264 <name>dis</name> 265 <description>Disabled.</description> 266 <value>1</value> 267 </enumeratedValue> 268 </enumeratedValues> 269 </field> 270 <field> 271 <name>VCORE_EXT</name> 272 <description>Use external VCORE for 1V supply</description> 273 <bitOffset>17</bitOffset> 274 <bitWidth>1</bitWidth> 275 <access>read-write</access> 276 <enumeratedValues> 277 <enumeratedValue> 278 <name>dis</name> 279 <description>disable </description> 280 <value>0</value> 281 </enumeratedValue> 282 <enumeratedValue> 283 <name>en</name> 284 <description>use Vcore for retention.</description> 285 <value>1</value> 286 </enumeratedValue> 287 </enumeratedValues> 288 </field> 289 <field> 290 <name>VCOREMON_DIS</name> 291 <description>VDDC (Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes.</description> 292 <bitOffset>20</bitOffset> 293 <bitWidth>1</bitWidth> 294 <access>read-write</access> 295 <enumeratedValues> 296 <enumeratedValue> 297 <name>en</name> 298 <description>Enable</description> 299 <value>0</value> 300 </enumeratedValue> 301 <enumeratedValue> 302 <name>dis</name> 303 <description>Disabled.</description> 304 <value>1</value> 305 </enumeratedValue> 306 </enumeratedValues> 307 </field> 308 <field> 309 <name>VDDAMON_DIS</name> 310 <description>VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 311 <bitOffset>22</bitOffset> 312 <bitWidth>1</bitWidth> 313 <access>read-write</access> 314 <enumeratedValues> 315 <enumeratedValue> 316 <name>en</name> 317 <description>Enable if Bandgap is ON (default) </description> 318 <value>0</value> 319 </enumeratedValue> 320 <enumeratedValue> 321 <name>dis</name> 322 <description>Disabled.</description> 323 <value>1</value> 324 </enumeratedValue> 325 </enumeratedValues> 326 </field> 327 <field> 328 <name>PORVDDMON_DIS</name> 329 <description>VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods.</description> 330 <bitOffset>25</bitOffset> 331 <bitWidth>1</bitWidth> 332 <access>read-write</access> 333 <enumeratedValues> 334 <enumeratedValue> 335 <name>dis</name> 336 <description>Disabled.</description> 337 <value>0</value> 338 </enumeratedValue> 339 <enumeratedValue> 340 <name>en</name> 341 <description>Enabled.</description> 342 <value>1</value> 343 </enumeratedValue> 344 </enumeratedValues> 345 </field> 346 <field> 347 <name>VBBMON_DIS</name> 348 <description>VBB Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 349 <bitOffset>27</bitOffset> 350 <bitWidth>1</bitWidth> 351 <access>read-write</access> 352 <enumeratedValues> 353 <enumeratedValue> 354 <name>en</name> 355 <description>Enable if Bandgap is ON (default) </description> 356 <value>0</value> 357 </enumeratedValue> 358 <enumeratedValue> 359 <name>dis</name> 360 <description>Disabled.</description> 361 <value>1</value> 362 </enumeratedValue> 363 </enumeratedValues> 364 </field> 365 <field> 366 <name>INRO_EN</name> 367 <description>INRO remains on in all power modes if this bit is set otherwise it is controled by the LP controller</description> 368 <bitOffset>28</bitOffset> 369 <bitWidth>1</bitWidth> 370 <access>read-write</access> 371 </field> 372 <field> 373 <name>ERTCO_EN</name> 374 <description>XRTCO remains on in all power modes if this bit is set otherwise it is controled by the LP controller</description> 375 <bitOffset>29</bitOffset> 376 <bitWidth>1</bitWidth> 377 <access>read-write</access> 378 </field> 379 <field> 380 <name>TM_LPMODE</name> 381 <description>TBD</description> 382 <bitOffset>30</bitOffset> 383 <bitWidth>1</bitWidth> 384 <access>read-write</access> 385 </field> 386 <field> 387 <name>TM_PWRSEQ</name> 388 <description>TBD</description> 389 <bitOffset>31</bitOffset> 390 <bitWidth>1</bitWidth> 391 <access>read-write</access> 392 </field> 393 </fields> 394 </register> 395 <register> <!-- LPWKST0 Register --> 396 <name>LPWKST0</name> 397 <description>Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.</description> 398 <addressOffset>0x04</addressOffset> 399 <fields> 400 <field> 401 <name>ST</name> 402 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 403 <bitOffset>0</bitOffset> 404 <bitWidth>31</bitWidth> 405 <access>read-write</access> 406 <modifiedWriteValues>oneToClear</modifiedWriteValues> 407 </field> 408 </fields> 409 </register> 410 <register> <!-- LPWKEN0 Register --> 411 <name>LPWKEN0</name> 412 <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description> 413 <addressOffset>0x08</addressOffset> 414 <fields> 415 <field> 416 <name>EN</name> 417 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 418 <bitOffset>0</bitOffset> 419 <bitWidth>31</bitWidth> 420 <access>read-write</access> 421 </field> 422 </fields> 423 </register> 424 <register derivedFrom="LPWKST0"> <!-- LPWKST1 Register --> 425 <name>LPWKST1</name> 426 <description>Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.</description> 427 <addressOffset>0x0C</addressOffset> 428 </register> 429 <register derivedFrom="LPWKEN0"> <!-- LPWKEN1 Register --> 430 <name>LPWKEN1</name> 431 <description>Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.</description> 432 <addressOffset>0x10</addressOffset> 433 </register> 434 <register> <!-- LPPWKST Register --> 435 <name>LPPWKST</name> 436 <description>Low Power Peripheral Wakeup Status Register.</description> 437 <addressOffset>0x30</addressOffset> 438 <fields> 439 <field> 440 <name>LPTMR0</name> 441 <description>LPTM0 Wakeup Flag.</description> 442 <bitOffset>0</bitOffset> 443 <bitWidth>1</bitWidth> 444 <access>read-write</access> 445 <modifiedWriteValues>oneToClear</modifiedWriteValues> 446 </field> 447 <field> 448 <name>LPTMR1</name> 449 <description>LPTMR1 Wakeup Flag.</description> 450 <bitOffset>1</bitOffset> 451 <bitWidth>1</bitWidth> 452 <access>read-write</access> 453 <modifiedWriteValues>oneToClear</modifiedWriteValues> 454 </field> 455 <field> 456 <name>LPUART0</name> 457 <description>LPUART0 Wakeup Flag.</description> 458 <bitOffset>2</bitOffset> 459 <bitWidth>1</bitWidth> 460 <access>read-write</access> 461 <modifiedWriteValues>oneToClear</modifiedWriteValues> 462 </field> 463 <field> 464 <name>AINCOMP0</name> 465 <description>AINCOMP0 Wakeup Flag.</description> 466 <bitOffset>3</bitOffset> 467 <bitWidth>1</bitWidth> 468 <access>read-write</access> 469 <modifiedWriteValues>oneToClear</modifiedWriteValues> 470 </field> 471 <field> 472 <name>AINCOMP1</name> 473 <description>AINCOMP1 Wakeup Flag.</description> 474 <bitOffset>4</bitOffset> 475 <bitWidth>1</bitWidth> 476 <access>read-write</access> 477 <modifiedWriteValues>oneToClear</modifiedWriteValues> 478 </field> 479 <field> 480 <name>AINCOMP0_OUT</name> 481 <description>AINCOMP0 Status.</description> 482 <bitOffset>5</bitOffset> 483 <bitWidth>1</bitWidth> 484 <access>read-only</access> 485 </field> 486 <field> 487 <name>AINCOMP1_OUT</name> 488 <description>AINCOMP1 Status.</description> 489 <bitOffset>6</bitOffset> 490 <bitWidth>1</bitWidth> 491 <access>read-only</access> 492 </field> 493 <field> 494 <name>BACKUP</name> 495 <description>BBMODE Wakeup Flag.</description> 496 <bitOffset>16</bitOffset> 497 <bitWidth>1</bitWidth> 498 <access>read-write</access> 499 <modifiedWriteValues>oneToClear</modifiedWriteValues> 500 </field> 501 </fields> 502 </register> 503 <register> <!-- LPPWKEN Register --> 504 <name>LPPWKEN</name> 505 <description>Low Power Peripheral Wakeup Enable Register.</description> 506 <addressOffset>0x34</addressOffset> 507 <fields> 508 <field> 509 <name>LPTMR0</name> 510 <description> TIMER4 Wakeup Enable. This bit allows wakeup from the TIMER4.</description> 511 <bitOffset>0</bitOffset> 512 <bitWidth>1</bitWidth> 513 <access>read-write</access> 514 </field> 515 <field> 516 <name>LPTMR1</name> 517 <description> TIMER5 Wakeup Enable. This bit allows wakeup from the TIMER5.</description> 518 <bitOffset>1</bitOffset> 519 <bitWidth>1</bitWidth> 520 <access>read-write</access> 521 </field> 522 <field> 523 <name>LPUART0</name> 524 <description> LPUART Wakeup Enable. This bit allows wakeup from the LPUART.</description> 525 <bitOffset>2</bitOffset> 526 <bitWidth>1</bitWidth> 527 <access>read-write</access> 528 </field> 529 <field> 530 <name>AINCOMP0</name> 531 <description> AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0.</description> 532 <bitOffset>3</bitOffset> 533 <bitWidth>1</bitWidth> 534 <access>read-write</access> 535 </field> 536 <field> 537 <name>AINCOMP1</name> 538 <description> AINCOMP1 Wakeup Enable. This bit allows wakeup from the AINCOMP1.</description> 539 <bitOffset>4</bitOffset> 540 <bitWidth>1</bitWidth> 541 <access>read-write</access> 542 </field> 543 </fields> 544 </register> 545 <register> <!-- LPMEMSD Register --> 546 <name>LPMEMSD</name> 547 <description>Low Power Memory Shutdown Control.</description> 548 <addressOffset>0x40</addressOffset> 549 <fields> 550 <field> 551 <name>RAM0</name> 552 <description>System RAM block 0 Shut Down.</description> 553 <bitOffset>0</bitOffset> 554 <bitWidth>1</bitWidth> 555 <access>read-write</access> 556 <enumeratedValues> 557 <enumeratedValue> 558 <name>normal</name> 559 <description>Normal Operating Mode.</description> 560 <value>0</value> 561 </enumeratedValue> 562 <enumeratedValue> 563 <name>shutdown</name> 564 <description>Shutdown Mode.</description> 565 <value>1</value> 566 </enumeratedValue> 567 </enumeratedValues> 568 </field> 569 <field> 570 <name>RAM1</name> 571 <description>System RAM block 1 Shut Down.</description> 572 <bitOffset>1</bitOffset> 573 <bitWidth>1</bitWidth> 574 <access>read-write</access> 575 <enumeratedValues> 576 <enumeratedValue> 577 <name>normal</name> 578 <description>Normal Operating Mode.</description> 579 <value>0</value> 580 </enumeratedValue> 581 <enumeratedValue> 582 <name>shutdown</name> 583 <description>Shutdown Mode.</description> 584 <value>1</value> 585 </enumeratedValue> 586 </enumeratedValues> 587 </field> 588 <field> 589 <name>RAM2</name> 590 <description>System RAM block 2 Shut Down.</description> 591 <bitOffset>2</bitOffset> 592 <bitWidth>1</bitWidth> 593 <access>read-write</access> 594 <enumeratedValues> 595 <enumeratedValue> 596 <name>normal</name> 597 <description>Normal Operating Mode.</description> 598 <value>0</value> 599 </enumeratedValue> 600 <enumeratedValue> 601 <name>shutdown</name> 602 <description>Shutdown Mode.</description> 603 <value>1</value> 604 </enumeratedValue> 605 </enumeratedValues> 606 </field> 607 <field> 608 <name>RAM3</name> 609 <description>System RAM block 3 Shut Down.</description> 610 <bitOffset>3</bitOffset> 611 <bitWidth>1</bitWidth> 612 <access>read-write</access> 613 <enumeratedValues> 614 <enumeratedValue> 615 <name>normal</name> 616 <description>Normal Operating Mode.</description> 617 <value>0</value> 618 </enumeratedValue> 619 <enumeratedValue> 620 <name>shutdown</name> 621 <description>Shutdown Mode.</description> 622 <value>1</value> 623 </enumeratedValue> 624 </enumeratedValues> 625 </field> 626 </fields> 627 </register> 628 <register> <!-- GPR0 Register --> 629 <name>GPR0</name> 630 <description>General Purpose Register 0.</description> 631 <addressOffset>0x48</addressOffset> 632 </register> 633 <register> <!-- GPR1 Register --> 634 <name>GPR1</name> 635 <description>General Purpose Register 1.</description> 636 <addressOffset>0x4C</addressOffset> 637 </register> 638 </registers> 639 </peripheral> 640 <!-- PWRSEQ: Power sequencer --> 641</device> 642
