1<?xml version="1.0" encoding="utf-8" standalone="no"?>
2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd">
3 <peripheral>
4  <name>PWRSEQ</name>
5  <description>Power Sequencer / Low Power Control Register.</description>
6  <baseAddress>0x40006800</baseAddress>
7  <addressBlock>
8   <offset>0x00</offset>
9   <size>0x400</size>
10   <usage>registers</usage>
11  </addressBlock>
12  <registers>
13   <register>
14    <name>LPCN</name>
15    <description>Low Power Control Register.</description>
16    <addressOffset>0x00</addressOffset>
17    <fields>
18     <field>
19      <name>RAMRET0</name>
20      <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description>
21      <bitOffset>0</bitOffset>
22      <bitWidth>1</bitWidth>
23      <enumeratedValues>
24       <enumeratedValue>
25        <name>dis</name>
26        <description>Disable Ram Retention.</description>
27        <value>0</value>
28       </enumeratedValue>
29       <enumeratedValue>
30        <name>en</name>
31        <description>Enable System RAM 0 retention.</description>
32        <value>1</value>
33       </enumeratedValue>
34      </enumeratedValues>
35     </field>
36     <field>
37      <name>RAMRET1</name>
38      <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description>
39      <bitOffset>1</bitOffset>
40      <bitWidth>1</bitWidth>
41      <enumeratedValues>
42       <enumeratedValue>
43        <name>dis</name>
44        <description>Disable Ram Retention.</description>
45        <value>0</value>
46       </enumeratedValue>
47       <enumeratedValue>
48        <name>en</name>
49        <description>Enable System RAM 1 retention.</description>
50        <value>1</value>
51       </enumeratedValue>
52      </enumeratedValues>
53     </field>
54     <field>
55      <name>RAMRET2</name>
56      <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description>
57      <bitOffset>2</bitOffset>
58      <bitWidth>1</bitWidth>
59      <enumeratedValues>
60       <enumeratedValue>
61        <name>dis</name>
62        <description>Disable Ram Retention.</description>
63        <value>0</value>
64       </enumeratedValue>
65       <enumeratedValue>
66        <name>en</name>
67        <description>Enable System RAM 2 retention.</description>
68        <value>1</value>
69       </enumeratedValue>
70      </enumeratedValues>
71     </field>
72     <field>
73      <name>RAMRET3</name>
74      <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description>
75      <bitOffset>3</bitOffset>
76      <bitWidth>1</bitWidth>
77      <enumeratedValues>
78       <enumeratedValue>
79        <name>dis</name>
80        <description>Disable Ram Retention.</description>
81        <value>0</value>
82       </enumeratedValue>
83       <enumeratedValue>
84        <name>en</name>
85        <description>Enable System RAM 3 retention.</description>
86        <value>1</value>
87       </enumeratedValue>
88      </enumeratedValues>
89     </field>
90     <field>
91      <name>LPMCLKSEL</name>
92      <description>Low Power Mode APB Clock Select.</description>
93      <bitOffset>8</bitOffset>
94      <bitWidth>1</bitWidth>
95     </field>
96     <field>
97      <name>LPMFAST</name>
98      <description>Low Power Mode Clock Select.</description>
99      <bitOffset>9</bitOffset>
100      <bitWidth>1</bitWidth>
101     </field>
102     <field>
103      <name>BG_DIS</name>
104      <description>Bandgap OFF. This controls the System Bandgap in DeepSleep mode.</description>
105      <bitOffset>11</bitOffset>
106      <bitWidth>1</bitWidth>
107      <enumeratedValues>
108       <enumeratedValue>
109        <name>on</name>
110        <description>Bandgap is always ON.</description>
111        <value>0</value>
112       </enumeratedValue>
113       <enumeratedValue>
114        <name>off</name>
115        <description>Bandgap is OFF in DeepSleep mode (default).</description>
116        <value>1</value>
117       </enumeratedValue>
118      </enumeratedValues>
119     </field>
120     <field>
121      <name>LPWKST_CLR</name>
122      <description>Low Power Wakeup Status Register Clear</description>
123      <bitOffset>31</bitOffset>
124      <bitWidth>1</bitWidth>
125     </field>
126    </fields>
127   </register>
128   <register>
129    <name>LPWKST0</name>
130    <description>Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.</description>
131    <addressOffset>0x04</addressOffset>
132    <fields>
133     <field>
134      <name>WAKEST</name>
135      <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description>
136      <bitOffset>0</bitOffset>
137      <bitWidth>1</bitWidth>
138     </field>
139    </fields>
140   </register>
141   <register>
142    <name>LPWKEN0</name>
143    <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description>
144    <addressOffset>0x08</addressOffset>
145    <fields>
146     <field>
147      <name>WAKEEN</name>
148      <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description>
149      <bitOffset>0</bitOffset>
150      <bitWidth>31</bitWidth>
151     </field>
152    </fields>
153   </register>
154   <register derivedFrom="LPWKST0">
155    <name>LPWKST1</name>
156    <description>Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.</description>
157    <addressOffset>0x0C</addressOffset>
158   </register>
159   <register derivedFrom="LPWKEN0">
160    <name>LPWKEN1</name>
161    <description>Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.</description>
162    <addressOffset>0x10</addressOffset>
163   </register>
164   <register derivedFrom="LPWKST0">
165    <name>LPWKST2</name>
166    <description>Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2.</description>
167    <addressOffset>0x14</addressOffset>
168   </register>
169   <register derivedFrom="LPWKEN0">
170    <name>LPWKEN2</name>
171    <description>Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2.</description>
172    <addressOffset>0x18</addressOffset>
173   </register>
174   <register derivedFrom="LPWKST0">
175    <name>LPWKST3</name>
176    <description>Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3.</description>
177    <addressOffset>0x1C</addressOffset>
178   </register>
179   <register derivedFrom="LPWKEN0">
180    <name>LPWKEN3</name>
181    <description>Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3.</description>
182    <addressOffset>0x20</addressOffset>
183   </register>
184   <register>
185    <name>LPPWST</name>
186    <description>Low Power Peripheral Wakeup Status Register.</description>
187    <addressOffset>0x30</addressOffset>
188    <fields>
189     <field>
190      <name>AINCOMP0</name>
191      <description>Analog Input Comparator Wakeup Flag.</description>
192      <bitOffset>4</bitOffset>
193      <bitWidth>1</bitWidth>
194     </field>
195     <field>
196      <name>BACKUP</name>
197      <description>Backup Mode Wakeup Flag.</description>
198      <bitOffset>16</bitOffset>
199      <bitWidth>1</bitWidth>
200     </field>
201     <field>
202      <name>RESET</name>
203      <description>Reset Detected Wakeup Flag.</description>
204      <bitOffset>17</bitOffset>
205      <bitWidth>1</bitWidth>
206     </field>
207    </fields>
208   </register>
209   <register>
210    <name>LPPWEN</name>
211    <description>Low Power Peripheral Wakeup Enable Register.</description>
212    <addressOffset>0x34</addressOffset>
213    <fields>
214     <field>
215      <name>AINCOMP0</name>
216      <description> AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0.</description>
217      <bitOffset>4</bitOffset>
218      <bitWidth>1</bitWidth>
219     </field>
220     <field>
221      <name>WDT0</name>
222      <description> WDT0 Wakeup Enable. This bit allows wakeup from the WDT0.</description>
223      <bitOffset>8</bitOffset>
224      <bitWidth>1</bitWidth>
225     </field>
226     <field>
227      <name>WDT1</name>
228      <description> WDT1 Wakeup Enable. This bit allows wakeup from the WDT1.</description>
229      <bitOffset>9</bitOffset>
230      <bitWidth>1</bitWidth>
231     </field>
232     <field>
233      <name>CPU1</name>
234      <description> CPU1 Wakeup Enable. This bit allows wakeup from the CPU1.</description>
235      <bitOffset>10</bitOffset>
236      <bitWidth>1</bitWidth>
237     </field>
238     <field>
239      <name>TMR0</name>
240      <description> TMR0 Wakeup Enable. This bit allows wakeup from the TMR0.</description>
241      <bitOffset>11</bitOffset>
242      <bitWidth>1</bitWidth>
243     </field>
244     <field>
245      <name>TMR1</name>
246      <description> TMR1 Wakeup Enable. This bit allows wakeup from the TMR1.</description>
247      <bitOffset>12</bitOffset>
248      <bitWidth>1</bitWidth>
249     </field>
250     <field>
251      <name>TMR2</name>
252      <description> TMR2 Wakeup Enable. This bit allows wakeup from the TMR2.</description>
253      <bitOffset>13</bitOffset>
254      <bitWidth>1</bitWidth>
255     </field>
256     <field>
257      <name>TMR3</name>
258      <description> TMR3 Wakeup Enable. This bit allows wakeup from the TMR3.</description>
259      <bitOffset>14</bitOffset>
260      <bitWidth>1</bitWidth>
261     </field>
262     <field>
263      <name>TMR4</name>
264      <description> TMR4 Wakeup Enable. This bit allows wakeup from the TMR4.</description>
265      <bitOffset>15</bitOffset>
266      <bitWidth>1</bitWidth>
267     </field>
268     <field>
269      <name>TMR5</name>
270      <description> TMR5 Wakeup Enable. This bit allows wakeup from the TMR5.</description>
271      <bitOffset>16</bitOffset>
272      <bitWidth>1</bitWidth>
273     </field>
274     <field>
275      <name>UART0</name>
276      <description> UART0 Wakeup Enable. This bit allows wakeup from the UART0.</description>
277      <bitOffset>17</bitOffset>
278      <bitWidth>1</bitWidth>
279     </field>
280     <field>
281      <name>UART1</name>
282      <description> UART1 Wakeup Enable. This bit allows wakeup from the UART1.</description>
283      <bitOffset>18</bitOffset>
284      <bitWidth>1</bitWidth>
285     </field>
286     <field>
287      <name>UART2</name>
288      <description> UART2 Wakeup Enable. This bit allows wakeup from the UART2.</description>
289      <bitOffset>19</bitOffset>
290      <bitWidth>1</bitWidth>
291     </field>
292     <field>
293      <name>UART3</name>
294      <description> UART3 Wakeup Enable. This bit allows wakeup from the UART3.</description>
295      <bitOffset>20</bitOffset>
296      <bitWidth>1</bitWidth>
297     </field>
298     <field>
299      <name>I2C0</name>
300      <description> I2C0 Wakeup Enable. This bit allows wakeup from the I2C0.</description>
301      <bitOffset>21</bitOffset>
302      <bitWidth>1</bitWidth>
303     </field>
304     <field>
305      <name>I2C1</name>
306      <description> I2C1 Wakeup Enable. This bit allows wakeup from the I2C1.</description>
307      <bitOffset>22</bitOffset>
308      <bitWidth>1</bitWidth>
309     </field>
310     <field>
311      <name>I2C2</name>
312      <description> I2C2 Wakeup Enable. This bit allows wakeup from the I2C2.</description>
313      <bitOffset>23</bitOffset>
314      <bitWidth>1</bitWidth>
315     </field>
316     <field>
317      <name>I2S</name>
318      <description> I2S Wakeup Enable. This bit allows wakeup from the I2S.</description>
319      <bitOffset>24</bitOffset>
320      <bitWidth>1</bitWidth>
321     </field>
322     <field>
323      <name>SPI1</name>
324      <description> SPI1 Wakeup Enable. This bit allows wakeup from the SPI1.</description>
325      <bitOffset>25</bitOffset>
326      <bitWidth>1</bitWidth>
327     </field>
328     <field>
329      <name>LPCMP</name>
330      <description> LPCMP Wakeup Enable. This bit allows wakeup from the LPCMP.</description>
331      <bitOffset>26</bitOffset>
332      <bitWidth>1</bitWidth>
333     </field>
334    </fields>
335   </register>
336   <register>
337    <name>VBTLEPD</name>
338    <description>Low-Power VBTLE Power Down Register.</description>
339    <addressOffset>0x44</addressOffset>
340    <fields>
341     <field>
342      <name>BTLE</name>
343      <description>Power Down SIMO VREGO_D.</description>
344      <bitOffset>1</bitOffset>
345      <bitWidth>1</bitWidth>
346     </field>
347    </fields>
348   </register>
349   <register>
350    <name>GP0</name>
351    <description>General Purpose Register 0</description>
352    <addressOffset>0x48</addressOffset>
353   </register>
354   <register>
355    <name>GP1</name>
356    <description>General Purpose Register 1</description>
357    <addressOffset>0x4C</addressOffset>
358   </register>
359  </registers>
360 </peripheral>
361<!-- PWRSEQ: Power sequencer          -->
362</device>
363