1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>PWRSEQ</name> 5 <description>Power Sequencer / Low Power Control Register.</description> 6 <baseAddress>0x40006800</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>LPCN</name> 15 <description>Low Power Control Register.</description> 16 <addressOffset>0x00</addressOffset> 17 <fields> 18 <field> 19 <name>RAMRET_EN</name> 20 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>2</bitWidth> 23 </field> 24 <field> 25 <name>LDO_DIS</name> 26 <description>LDO Disabled</description> 27 <bitOffset>16</bitOffset> 28 <bitWidth>1</bitWidth> 29 </field> 30 <field> 31 <name>VCOREMON_DIS</name> 32 <description>Vcore Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes.</description> 33 <bitOffset>20</bitOffset> 34 <bitWidth>1</bitWidth> 35 <enumeratedValues> 36 <enumeratedValue> 37 <name>en</name> 38 <description>Enable if Bandgap is ON (default) </description> 39 <value>0</value> 40 </enumeratedValue> 41 <enumeratedValue> 42 <name>dis</name> 43 <description>Disabled.</description> 44 <value>1</value> 45 </enumeratedValue> 46 </enumeratedValues> 47 </field> 48 <field> 49 <name>VDDAMON_DIS</name> 50 <description>VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 51 <bitOffset>22</bitOffset> 52 <bitWidth>1</bitWidth> 53 <enumeratedValues> 54 <enumeratedValue> 55 <name>en</name> 56 <description>Enable if Bandgap is ON (default) </description> 57 <value>0</value> 58 </enumeratedValue> 59 <enumeratedValue> 60 <name>dis</name> 61 <description>Disabled.</description> 62 <value>1</value> 63 </enumeratedValue> 64 </enumeratedValues> 65 </field> 66 </fields> 67 </register> 68 <register> 69 <name>LPWKST0</name> 70 <description>Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.</description> 71 <addressOffset>0x04</addressOffset> 72 <fields> 73 <field> 74 <name>ST</name> 75 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 76 <bitOffset>0</bitOffset> 77 <bitWidth>16</bitWidth> 78 </field> 79 </fields> 80 </register> 81 <register> 82 <name>LPWKEN0</name> 83 <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description> 84 <addressOffset>0x08</addressOffset> 85 <fields> 86 <field> 87 <name>EN</name> 88 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 89 <bitOffset>0</bitOffset> 90 <bitWidth>16</bitWidth> 91 </field> 92 </fields> 93 </register> 94 <register> 95 <name>LPWKST1</name> 96 <description>Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.</description> 97 <addressOffset>0x0C</addressOffset> 98 <fields> 99 <field> 100 <name>ST</name> 101 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 102 <bitOffset>0</bitOffset> 103 <bitWidth>11</bitWidth> 104 </field> 105 </fields> 106 </register> 107 <register> 108 <name>LPWKEN1</name> 109 <description>Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.</description> 110 <addressOffset>0x10</addressOffset> 111 <fields> 112 <field> 113 <name>EN</name> 114 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 115 <bitOffset>0</bitOffset> 116 <bitWidth>11</bitWidth> 117 </field> 118 </fields> 119 </register> 120 <register> 121 <name>LPPWKST</name> 122 <description>Low Power Peripheral Wakeup Status Register.</description> 123 <addressOffset>0x30</addressOffset> 124 <fields> 125 <field> 126 <name>BBMOD</name> 127 <description>Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode.</description> 128 <bitOffset>16</bitOffset> 129 <bitWidth>1</bitWidth> 130 </field> 131 <field> 132 <name>RST</name> 133 <description>Reset Detect Wakeup Flag (write one to clear). This bit will be set when the external reset causes wakeup</description> 134 <bitOffset>17</bitOffset> 135 <bitWidth>1</bitWidth> 136 </field> 137 <field> 138 <name>SDMA1</name> 139 <description>Smart DMA (1) Detect Wakeup Flag (write one to clear). This bit will be set when the SDMA IRQ transitions from low to high or high to low</description> 140 <bitOffset>18</bitOffset> 141 <bitWidth>1</bitWidth> 142 </field> 143 </fields> 144 </register> 145 <register> 146 <name>LPMEMSD</name> 147 <description>Low Power Memory Shutdown Control.</description> 148 <addressOffset>0x40</addressOffset> 149 <fields> 150 <field> 151 <name>RAM0</name> 152 <description>System RAM block 0 Shut Down.</description> 153 <bitOffset>0</bitOffset> 154 <bitWidth>1</bitWidth> 155 <enumeratedValues> 156 <enumeratedValue> 157 <name>normal</name> 158 <description>Normal Operating Mode.</description> 159 <value>0</value> 160 </enumeratedValue> 161 <enumeratedValue> 162 <name>shutdown</name> 163 <description>Shutdown Mode.</description> 164 <value>1</value> 165 </enumeratedValue> 166 </enumeratedValues> 167 </field> 168 <field> 169 <name>RAM1</name> 170 <description>System RAM block 1 Shut Down.</description> 171 <bitOffset>1</bitOffset> 172 <bitWidth>1</bitWidth> 173 <enumeratedValues> 174 <enumeratedValue> 175 <name>normal</name> 176 <description>Normal Operating Mode.</description> 177 <value>0</value> 178 </enumeratedValue> 179 <enumeratedValue> 180 <name>shutdown</name> 181 <description>Shutdown Mode.</description> 182 <value>1</value> 183 </enumeratedValue> 184 </enumeratedValues> 185 </field> 186 <field> 187 <name>RAM2</name> 188 <description>System RAM block 2 Shut Down.</description> 189 <bitOffset>2</bitOffset> 190 <bitWidth>1</bitWidth> 191 <enumeratedValues> 192 <enumeratedValue> 193 <name>normal</name> 194 <description>Normal Operating Mode.</description> 195 <value>0</value> 196 </enumeratedValue> 197 <enumeratedValue> 198 <name>shutdown</name> 199 <description>Shutdown Mode.</description> 200 <value>1</value> 201 </enumeratedValue> 202 </enumeratedValues> 203 </field> 204 <field> 205 <name>RAM3</name> 206 <description>System RAM block 3 Shut Down.</description> 207 <bitOffset>3</bitOffset> 208 <bitWidth>1</bitWidth> 209 <enumeratedValues> 210 <enumeratedValue> 211 <name>normal</name> 212 <description>Normal Operating Mode.</description> 213 <value>0</value> 214 </enumeratedValue> 215 <enumeratedValue> 216 <name>shutdown</name> 217 <description>Shutdown Mode.</description> 218 <value>1</value> 219 </enumeratedValue> 220 </enumeratedValues> 221 </field> 222 <field> 223 <name>RAM4</name> 224 <description>System RAM block 4 Shut Down.</description> 225 <bitOffset>4</bitOffset> 226 <bitWidth>1</bitWidth> 227 <enumeratedValues> 228 <enumeratedValue> 229 <name>normal</name> 230 <description>Normal Operating Mode.</description> 231 <value>0</value> 232 </enumeratedValue> 233 <enumeratedValue> 234 <name>shutdown</name> 235 <description>Shutdown Mode.</description> 236 <value>1</value> 237 </enumeratedValue> 238 </enumeratedValues> 239 </field> 240 <field> 241 <name>ICACHE</name> 242 <description>Instruction Cache RAM Shut Down.</description> 243 <bitOffset>7</bitOffset> 244 <bitWidth>1</bitWidth> 245 <enumeratedValues> 246 <enumeratedValue> 247 <name>normal</name> 248 <description>Normal Operating Mode.</description> 249 <value>0</value> 250 </enumeratedValue> 251 <enumeratedValue> 252 <name>shutdown</name> 253 <description>Shutdown Mode.</description> 254 <value>1</value> 255 </enumeratedValue> 256 </enumeratedValues> 257 </field> 258 <field> 259 <name>ICACHEXIP</name> 260 <description>XiP Instruction Cache RAM Shut Down.</description> 261 <bitOffset>8</bitOffset> 262 <bitWidth>1</bitWidth> 263 <enumeratedValues> 264 <enumeratedValue> 265 <name>normal</name> 266 <description>Normal Operating Mode.</description> 267 <value>0</value> 268 </enumeratedValue> 269 <enumeratedValue> 270 <name>shutdown</name> 271 <description>Shutdown Mode.</description> 272 <value>1</value> 273 </enumeratedValue> 274 </enumeratedValues> 275 </field> 276 <field> 277 <name>ROM</name> 278 <description>ROM Shut Down.</description> 279 <bitOffset>12</bitOffset> 280 <bitWidth>1</bitWidth> 281 <enumeratedValues> 282 <enumeratedValue> 283 <name>normal</name> 284 <description>Normal Operating Mode.</description> 285 <value>0</value> 286 </enumeratedValue> 287 <enumeratedValue> 288 <name>shutdown</name> 289 <description>Shutdown Mode.</description> 290 <value>1</value> 291 </enumeratedValue> 292 </enumeratedValues> 293 </field> 294 </fields> 295 </register> 296 <register> 297 <name>GP0</name> 298 <description>Back Up General Purpose Register 0</description> 299 <addressOffset>0x48</addressOffset> 300 </register> 301 <register> 302 <name>GP1</name> 303 <description>Back Up General Purpose Register 1</description> 304 <addressOffset>0x4C</addressOffset> 305 </register> 306 </registers> 307 </peripheral> 308 <!-- PWRSEQ: Power sequencer --> 309</device>
