1<?xml version="1.0" encoding="utf-8" standalone="no"?>
2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd">
3 <peripheral>
4  <name>I2S</name>
5  <description>Inter-IC Sound Interface.</description>
6  <groupName>I2S</groupName>
7  <baseAddress>0x40060000</baseAddress>
8  <size>32</size>
9  <addressBlock>
10   <offset>0x00</offset>
11   <size>0x1000</size>
12   <usage>registers</usage>
13  </addressBlock>
14  <interrupt>
15   <name>I2S</name>
16   <description>I2S IRQ</description>
17   <value>99</value>
18  </interrupt>
19  <registers>
20   <register>
21    <name>CTRL0CH0</name>
22    <description>Global mode channel.</description>
23    <addressOffset>0x00</addressOffset>
24    <fields>
25     <field>
26      <name>LSB_FIRST</name>
27      <description>LSB Transmit Receive First.</description>
28      <bitRange>[1:1]</bitRange>
29      <access>read-write</access>
30     </field>
31     <field>
32      <name>PDM_FILT</name>
33      <description>PDM Filter.</description>
34      <bitRange>[2:2]</bitRange>
35      <access>read-write</access>
36     </field>
37     <field>
38      <name>PDM_EN</name>
39      <description>PDM Enable.</description>
40      <bitRange>[3:3]</bitRange>
41      <access>read-write</access>
42     </field>
43     <field>
44      <name>USEDDR</name>
45      <description>DDR.</description>
46      <bitRange>[4:4]</bitRange>
47      <access>read-write</access>
48     </field>
49     <field>
50      <name>PDM_INV</name>
51      <description>Invert PDM.</description>
52      <bitRange>[5:5]</bitRange>
53      <access>read-write</access>
54     </field>
55     <field>
56      <name>CH_MODE</name>
57      <description>SCK Select.</description>
58      <bitRange>[7:6]</bitRange>
59      <access>read-write</access>
60     </field>
61     <field>
62      <name>WS_POL</name>
63      <description>WS polarity select. </description>
64      <bitRange>[8:8]</bitRange>
65      <access>read-write</access>
66     </field>
67     <field>
68      <name>MSB_LOC</name>
69      <description>MSB location. </description>
70      <bitRange>[9:9]</bitRange>
71      <access>read-only</access>
72     </field>
73     <field>
74      <name>ALIGN</name>
75      <description>Align to MSB or LSB.</description>
76      <bitRange>[10:10]</bitRange>
77      <access>read-only</access>
78     </field>
79     <field>
80      <name>EXT_SEL</name>
81      <description>External SCK/WS selection.</description>
82      <bitRange>[11:11]</bitRange>
83      <access>read-write</access>
84     </field>
85     <field>
86      <name>STEREO</name>
87      <description>Stereo mode of I2S.</description>
88      <bitRange>[13:12]</bitRange>
89      <access>read-only</access>
90     </field>
91     <field>
92      <name>WSIZE</name>
93      <description>Data size when write to FIFO.</description>
94      <bitRange>[15:14]</bitRange>
95      <access>read-write</access>
96     </field>
97     <field>
98      <name>TX_EN</name>
99      <description>TX channel enable. </description>
100      <bitRange>[16:16]</bitRange>
101      <access>read-write</access>
102     </field>
103     <field>
104      <name>RX_EN</name>
105      <description>RX channel enable. </description>
106      <bitRange>[17:17]</bitRange>
107      <access>read-write</access>
108     </field>
109     <field>
110      <name>FLUSH</name>
111      <description>Flushes the TX/RX FIFO buffer. </description>
112      <bitRange>[18:18]</bitRange>
113      <access>read-write</access>
114     </field>
115     <field>
116      <name>RST</name>
117      <description>Write 1 to reset channel. </description>
118      <bitRange>[19:19]</bitRange>
119      <access>read-write</access>
120     </field>
121     <field>
122      <name>FIFO_LSB</name>
123      <description>Bit Field Control. </description>
124      <bitRange>[20:20]</bitRange>
125      <access>read-write</access>
126     </field>
127     <field>
128      <name>RX_THD_VAL</name>
129      <description>depth of receive FIFO for threshold interrupt generation. </description>
130      <bitRange>[31:24]</bitRange>
131      <access>read-write</access>
132     </field>
133    </fields>
134   </register>
135   <register>
136    <name>CTRL1CH0</name>
137    <description>Local channel Setup.</description>
138    <addressOffset>0x10</addressOffset>
139    <fields>
140     <field>
141      <name>BITS_WORD</name>
142      <description>I2S word length.</description>
143      <bitRange>[4:0]</bitRange>
144      <access>read-write</access>
145     </field>
146     <field>
147      <name>EN</name>
148      <description>I2S clock enable.</description>
149      <bitRange>[8:8]</bitRange>
150      <access>read-write</access>
151     </field>
152     <field>
153      <name>SMP_SIZE</name>
154      <description>I2S sample size length.</description>
155      <bitRange>[13:9]</bitRange>
156      <access>read-write</access>
157     </field>
158     <field>
159      <name>ADJUST</name>
160      <description>LSB/MSB Justify.</description>
161      <bitRange>[15:15]</bitRange>
162      <access>read-write</access>
163     </field>
164     <field>
165      <name>CLKDIV</name>
166      <description>I2S clock frequency divisor.</description>
167      <bitRange>[31:16]</bitRange>
168      <access>read-write</access>
169     </field>
170    </fields>
171   </register>
172   <register>
173    <name>FILTCH0</name>
174    <description>Filter.</description>
175    <addressOffset>0x20</addressOffset>
176   </register>
177   <register>
178    <name>DMACH0</name>
179    <description>DMA Control.</description>
180    <addressOffset>0x30</addressOffset>
181    <fields>
182     <field>
183      <name>DMA_TX_THD_VAL</name>
184      <description>TX FIFO Level DMA Trigger.</description>
185      <bitRange>[6:0]</bitRange>
186      <access>read-write</access>
187     </field>
188     <field>
189      <name>DMA_TX_EN</name>
190      <description>TX DMA channel enable.</description>
191      <bitRange>[7:7]</bitRange>
192      <access>read-write</access>
193     </field>
194     <field>
195      <name>DMA_RX_THD_VAL</name>
196      <description>RX FIFO Level DMA Trigger.</description>
197      <bitRange>[14:8]</bitRange>
198      <access>read-write</access>
199     </field>
200     <field>
201      <name>DMA_RX_EN</name>
202      <description>RX DMA channel enable.</description>
203      <bitRange>[15:15]</bitRange>
204      <access>read-write</access>
205     </field>
206     <field>
207      <name>TX_LVL</name>
208      <description>Number of data word in the TX FIFO.</description>
209      <bitRange>[23:16]</bitRange>
210      <access>read-write</access>
211     </field>
212     <field>
213      <name>RX_LVL</name>
214      <description>Number of data word in the RX FIFO.</description>
215      <bitRange>[31:24]</bitRange>
216      <access>read-write</access>
217     </field>
218    </fields>
219   </register>
220   <register>
221    <name>FIFOCH0</name>
222    <description>I2S Fifo.</description>
223    <addressOffset>0x40</addressOffset>
224    <fields>
225     <field>
226      <name>DATA</name>
227      <description>Load/unload location for TX and RX FIFO buffers.</description>
228      <bitRange>[31:0]</bitRange>
229      <access>read-write</access>
230     </field>
231    </fields>
232   </register>
233   <register>
234    <name>INTFL</name>
235    <description>ISR Status.</description>
236    <addressOffset>0x50</addressOffset>
237    <fields>
238     <field>
239      <name>RX_OV_CH0</name>
240      <description>Status for RX FIFO Overrun interrupt.</description>
241      <bitRange>[0:0]</bitRange>
242      <access>read-write</access>
243     </field>
244     <field>
245      <name>RX_THD_CH0</name>
246      <description>Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description>
247      <bitRange>[1:1]</bitRange>
248      <access>read-write</access>
249     </field>
250     <field>
251      <name>TX_OB_CH0</name>
252      <description>Status for interrupt when TX FIFO has only one byte remaining.</description>
253      <bitRange>[2:2]</bitRange>
254      <access>read-write</access>
255     </field>
256     <field>
257      <name>TX_HE_CH0</name>
258      <description>Status for interrupt when TX FIFO is half empty.</description>
259      <bitRange>[3:3]</bitRange>
260      <access>read-write</access>
261     </field>
262    </fields>
263   </register>
264   <register>
265    <name>INTEN</name>
266    <description>Interrupt Enable.</description>
267    <addressOffset>0x54</addressOffset>
268    <fields>
269     <field>
270      <name>RX_OV_CH0</name>
271      <description>Enable for RX FIFO Overrun interrupt.</description>
272      <bitRange>[0:0]</bitRange>
273      <access>read-write</access>
274     </field>
275     <field>
276      <name>RX_THD_CH0</name>
277      <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description>
278      <bitRange>[1:1]</bitRange>
279      <access>read-write</access>
280     </field>
281     <field>
282      <name>TX_OB_CH0</name>
283      <description>Enable for interrupt when TX FIFO has only one byte remaining.</description>
284      <bitRange>[2:2]</bitRange>
285      <access>read-write</access>
286     </field>
287     <field>
288      <name>TX_HE_CH0</name>
289      <description>Enable for interrupt when TX FIFO is half empty.</description>
290      <bitRange>[3:3]</bitRange>
291      <access>read-write</access>
292     </field>
293    </fields>
294   </register>
295   <register>
296    <name>EXTSETUP</name>
297    <description>Ext Control.</description>
298    <addressOffset>0x58</addressOffset>
299    <fields>
300     <field>
301      <name>EXT_BITS_WORD</name>
302      <description>Word Length for ch_mode.</description>
303      <bitRange>[4:0]</bitRange>
304      <access>read-write</access>
305     </field>
306    </fields>
307   </register>
308   <register>
309    <name>WKEN</name>
310    <description>Wakeup Enable.</description>
311    <addressOffset>0x5C</addressOffset>
312   </register>
313   <register>
314    <name>WKFL</name>
315    <description>Wakeup Flags.</description>
316    <addressOffset>0x60</addressOffset>
317   </register>
318  </registers>
319 </peripheral>
320<!-- I2S: Inter-IC Sound Interface -->
321</device>
322