1<?xml version="1.0" encoding="utf-8" standalone="no"?>
2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd">
3  <peripheral>
4    <name>I2S</name>
5    <description>Inter-IC Sound Interface.</description>
6    <groupName>I2S</groupName>
7    <baseAddress>0x40060000</baseAddress>
8    <size>32</size>
9    <addressBlock>
10      <offset>0x00</offset>
11      <size>0x1000</size>
12      <usage>registers</usage>
13    </addressBlock>
14    <interrupt>
15      <name>I2S</name>
16      <description>I2S IRQ</description>
17      <value>99</value>
18    </interrupt>
19    <registers>
20      <register>
21        <name>CTRL0CH0</name>
22        <description>Global mode channel.</description>
23        <addressOffset>0x00</addressOffset>
24        <fields>
25          <field>
26            <name>LSB_FIRST</name>
27            <description>LSB Transmit Receive First.</description>
28            <bitRange>[1:1]</bitRange>
29            <access>read-write</access>
30          </field>
31          <field>
32            <name>PDM_FILT</name>
33            <description>PDM Filter.</description>
34            <bitRange>[2:2]</bitRange>
35            <access>read-write</access>
36          </field>
37          <field>
38            <name>PDM_EN</name>
39            <description>PDM Enable.</description>
40            <bitRange>[3:3]</bitRange>
41            <access>read-write</access>
42          </field>
43          <field>
44            <name>USEDDR</name>
45            <description>DDR.</description>
46            <bitRange>[4:4]</bitRange>
47            <access>read-write</access>
48          </field>
49          <field>
50            <name>PDM_INV</name>
51            <description>Invert PDM.</description>
52            <bitRange>[5:5]</bitRange>
53            <access>read-write</access>
54          </field>
55          <field>
56            <name>CH_MODE</name>
57            <description>SCK Select.</description>
58            <bitRange>[7:6]</bitRange>
59            <access>read-write</access>
60          </field>
61          <field>
62            <name>WS_POL</name>
63            <description>WS polarity select. </description>
64            <bitRange>[8:8]</bitRange>
65            <access>read-write</access>
66          </field>
67          <field>
68            <name>MSB_LOC</name>
69            <description>MSB location. </description>
70            <bitRange>[9:9]</bitRange>
71            <access>read-only</access>
72          </field>
73          <field>
74            <name>ALIGN</name>
75            <description>Align to MSB or LSB.</description>
76            <bitRange>[10:10]</bitRange>
77            <access>read-only</access>
78          </field>
79          <field>
80            <name>EXT_SEL</name>
81            <description>External SCK/WS selection.</description>
82            <bitRange>[11:11]</bitRange>
83            <access>read-write</access>
84          </field>
85          <field>
86            <name>STEREO</name>
87            <description>Stereo mode of I2S.</description>
88            <bitRange>[13:12]</bitRange>
89            <access>read-only</access>
90          </field>
91          <field>
92            <name>WSIZE</name>
93            <description>Data size when write to FIFO.</description>
94            <bitRange>[15:14]</bitRange>
95            <access>read-write</access>
96          </field>
97          <field>
98            <name>TX_EN</name>
99            <description>TX channel enable. </description>
100            <bitRange>[16:16]</bitRange>
101            <access>read-write</access>
102          </field>
103          <field>
104            <name>RX_EN</name>
105            <description>RX channel enable. </description>
106            <bitRange>[17:17]</bitRange>
107            <access>read-write</access>
108          </field>
109          <field>
110            <name>FLUSH</name>
111            <description>Flushes the TX/RX FIFO buffer. </description>
112            <bitRange>[18:18]</bitRange>
113            <access>read-write</access>
114          </field>
115          <field>
116            <name>RST</name>
117            <description>Write 1 to reset channel. </description>
118            <bitRange>[19:19]</bitRange>
119            <access>read-write</access>
120          </field>
121          <field>
122            <name>FIFO_LSB</name>
123            <description>Bit Field Control. </description>
124            <bitRange>[20:20]</bitRange>
125            <access>read-write</access>
126          </field>
127          <field>
128            <name>RX_THD_VAL</name>
129            <description>depth of receive FIFO for threshold interrupt generation. </description>
130            <bitRange>[31:24]</bitRange>
131            <access>read-write</access>
132          </field>
133        </fields>
134      </register>
135      <register>
136        <name>CTRL1CH0</name>
137        <description>Local channel Setup.</description>
138        <addressOffset>0x10</addressOffset>
139        <fields>
140          <field>
141            <name>BITS_WORD</name>
142            <description>I2S word length.</description>
143            <bitRange>[4:0]</bitRange>
144            <access>read-write</access>
145          </field>
146          <field>
147            <name>EN</name>
148            <description>I2S clock enable.</description>
149            <bitRange>[8:8]</bitRange>
150            <access>read-write</access>
151          </field>
152          <field>
153            <name>SMP_SIZE</name>
154            <description>I2S sample size length.</description>
155            <bitRange>[13:9]</bitRange>
156            <access>read-write</access>
157          </field>
158          <field>
159            <name>CLKSEL</name>
160            <description>I2S clock select.</description>
161            <bitRange>[14:14]</bitRange>
162            <access>read-write</access>
163          </field>
164          <field>
165            <name>ADJUST</name>
166            <description>LSB/MSB Justify.</description>
167            <bitRange>[15:15]</bitRange>
168            <access>read-write</access>
169          </field>
170          <field>
171            <name>CLKDIV</name>
172            <description>I2S clock frequency divisor.</description>
173            <bitRange>[31:16]</bitRange>
174            <access>read-write</access>
175          </field>
176        </fields>
177      </register>
178      <register>
179        <name>FILTCH0</name>
180        <description>Filter.</description>
181        <addressOffset>0x20</addressOffset>
182      </register>
183      <register>
184        <name>DMACH0</name>
185        <description>DMA Control.</description>
186        <addressOffset>0x30</addressOffset>
187        <fields>
188          <field>
189            <name>DMA_TX_THD_VAL</name>
190            <description>TX FIFO Level DMA Trigger.</description>
191            <bitRange>[6:0]</bitRange>
192            <access>read-write</access>
193          </field>
194          <field>
195            <name>DMA_TX_EN</name>
196            <description>TX DMA channel enable.</description>
197            <bitRange>[7:7]</bitRange>
198            <access>read-write</access>
199          </field>
200          <field>
201            <name>DMA_RX_THD_VAL</name>
202            <description>RX FIFO Level DMA Trigger.</description>
203            <bitRange>[14:8]</bitRange>
204            <access>read-write</access>
205          </field>
206          <field>
207            <name>DMA_RX_EN</name>
208            <description>RX DMA channel enable.</description>
209            <bitRange>[15:15]</bitRange>
210            <access>read-write</access>
211          </field>
212          <field>
213            <name>TX_LVL</name>
214            <description>Number of data word in the TX FIFO.</description>
215            <bitRange>[23:16]</bitRange>
216            <access>read-write</access>
217          </field>
218          <field>
219            <name>RX_LVL</name>
220            <description>Number of data word in the RX FIFO.</description>
221            <bitRange>[31:24]</bitRange>
222            <access>read-write</access>
223          </field>
224        </fields>
225      </register>
226      <register>
227        <name>FIFOCH0</name>
228        <description>I2S Fifo.</description>
229        <addressOffset>0x40</addressOffset>
230        <fields>
231          <field>
232            <name>DATA</name>
233            <description>Load/unload location for TX and RX FIFO buffers.</description>
234            <bitRange>[31:0]</bitRange>
235            <access>read-write</access>
236          </field>
237        </fields>
238      </register>
239      <register>
240        <name>INTFL</name>
241        <description>ISR Status.</description>
242        <addressOffset>0x50</addressOffset>
243        <fields>
244          <field>
245            <name>RX_OV_CH0</name>
246            <description>Status for RX FIFO Overrun interrupt.</description>
247            <bitRange>[0:0]</bitRange>
248            <access>read-write</access>
249          </field>
250          <field>
251            <name>RX_THD_CH0</name>
252            <description>Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description>
253            <bitRange>[1:1]</bitRange>
254            <access>read-write</access>
255          </field>
256          <field>
257            <name>TX_OB_CH0</name>
258            <description>Status for interrupt when TX FIFO has only one byte remaining.</description>
259            <bitRange>[2:2]</bitRange>
260            <access>read-write</access>
261          </field>
262          <field>
263            <name>TX_HE_CH0</name>
264            <description>Status for interrupt when TX FIFO is half empty.</description>
265            <bitRange>[3:3]</bitRange>
266            <access>read-write</access>
267          </field>
268        </fields>
269      </register>
270      <register>
271        <name>INTEN</name>
272        <description>Interrupt Enable.</description>
273        <addressOffset>0x54</addressOffset>
274        <fields>
275          <field>
276            <name>RX_OV_CH0</name>
277            <description>Enable for RX FIFO Overrun interrupt.</description>
278            <bitRange>[0:0]</bitRange>
279            <access>read-write</access>
280          </field>
281          <field>
282            <name>RX_THD_CH0</name>
283            <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description>
284            <bitRange>[1:1]</bitRange>
285            <access>read-write</access>
286          </field>
287          <field>
288            <name>TX_OB_CH0</name>
289            <description>Enable for interrupt when TX FIFO has only one byte remaining.</description>
290            <bitRange>[2:2]</bitRange>
291            <access>read-write</access>
292          </field>
293          <field>
294            <name>TX_HE_CH0</name>
295            <description>Enable for interrupt when TX FIFO is half empty.</description>
296            <bitRange>[3:3]</bitRange>
297            <access>read-write</access>
298          </field>
299        </fields>
300      </register>
301      <register>
302        <name>EXTSETUP</name>
303        <description>Ext Control.</description>
304        <addressOffset>0x58</addressOffset>
305        <fields>
306          <field>
307            <name>EXT_BITS_WORD</name>
308            <description>Word Length for ch_mode.</description>
309            <bitRange>[4:0]</bitRange>
310            <access>read-write</access>
311          </field>
312        </fields>
313      </register>
314      <register>
315        <name>WKEN</name>
316        <description>Wakeup Enable.</description>
317        <addressOffset>0x5C</addressOffset>
318      </register>
319      <register>
320        <name>WKFL</name>
321        <description>Wakeup Flags.</description>
322        <addressOffset>0x60</addressOffset>
323      </register>
324    </registers>
325  </peripheral>
326  <!-- I2S: Inter-IC Sound Interface -->
327</device>