1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>I2C0</name> 5 <description>Inter-Integrated Circuit.</description> 6 <groupName>I2C</groupName> 7 <baseAddress>0x4001D000</baseAddress> 8 <size>32</size> 9 <addressBlock> 10 <offset>0x00</offset> 11 <size>0x1000</size> 12 <usage>registers</usage> 13 </addressBlock> 14 <interrupt> 15 <name>I2C0</name> 16 <description>I2C0 IRQ</description> 17 <value>13</value> 18 </interrupt> 19 <registers> 20 <register> 21 <name>CTRL</name> 22 <description>Control Register0.</description> 23 <addressOffset>0x00</addressOffset> 24 <fields> 25 <!-- FIELD 1 I2C Enable Control --> 26 <field> 27 <name>EN</name> 28 <description>I2C Enable.</description> 29 <bitRange>[0:0]</bitRange> 30 <access>read-write</access> 31 <enumeratedValues> 32 <enumeratedValue> 33 <name>dis</name> 34 <description>Disable I2C.</description> 35 <value>0</value> 36 </enumeratedValue> 37 <enumeratedValue> 38 <name>en</name> 39 <description>enable I2C.</description> 40 <value>1</value> 41 </enumeratedValue> 42 </enumeratedValues> 43 </field> 44 <!-- FIELD 2 Master mode control --> 45 <field> 46 <name>MST_MODE</name> 47 <description>Master Mode Enable.</description> 48 <bitRange>[1:1]</bitRange> 49 <access>read-write</access> 50 <enumeratedValues> 51 <enumeratedValue> 52 <name>slave_mode</name> 53 <description>Slave Mode.</description> 54 <value>0</value> 55 </enumeratedValue> 56 <enumeratedValue> 57 <name>master_mode</name> 58 <description>Master Mode.</description> 59 <value>1</value> 60 </enumeratedValue> 61 </enumeratedValues> 62 </field> 63 <!-- FIELD 3 General Call Address Control --> 64 <field> 65 <name>GC_ADDR_EN</name> 66 <description>General Call Address Enable.</description> 67 <bitRange>[2:2]</bitRange> 68 <access>read-write</access> 69 <enumeratedValues> 70 <enumeratedValue> 71 <name>dis</name> 72 <description>Ignore Gneral Call Address.</description> 73 <value>0</value> 74 </enumeratedValue> 75 <enumeratedValue> 76 <name>en</name> 77 <description>Acknowledge general call address.</description> 78 <value>1</value> 79 </enumeratedValue> 80 </enumeratedValues> 81 </field> 82 <!-- FIELD 4 Interactive Receive Mode --> 83 <field> 84 <name>IRXM_EN</name> 85 <description>Interactive Receive Mode.</description> 86 <bitRange>[3:3]</bitRange> 87 <access>read-write</access> 88 <enumeratedValues> 89 <enumeratedValue> 90 <name>dis</name> 91 <description>Disable Interactive Receive Mode.</description> 92 <value>0</value> 93 </enumeratedValue> 94 <enumeratedValue> 95 <name>en</name> 96 <description>Enable Interactive Receive Mode.</description> 97 <value>1</value> 98 </enumeratedValue> 99 </enumeratedValues> 100 </field> 101 <!-- FIELD 5 Interactive receive mode acknowledge --> 102 <field> 103 <name>IRXM_ACK</name> 104 <description>Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.</description> 105 <bitRange>[4:4]</bitRange> 106 <access>read-write</access> 107 <enumeratedValues> 108 <enumeratedValue> 109 <name>ack</name> 110 <description>return ACK (pulling SDA LOW).</description> 111 <value>0</value> 112 </enumeratedValue> 113 <enumeratedValue> 114 <name>nack</name> 115 <description>return NACK (leaving SDA HIGH).</description> 116 <value>1</value> 117 </enumeratedValue> 118 </enumeratedValues> 119 </field> 120 <!-- FIELD 6 SCL Pin Control --> 121 <field> 122 <name>SCL_OUT</name> 123 <description>SCL Output. This bits control SCL output when SWOE =1.</description> 124 <bitRange>[6:6]</bitRange> 125 <access>read-write</access> 126 <enumeratedValues> 127 <enumeratedValue> 128 <name>drive_scl_low</name> 129 <description>Drive SCL low. </description> 130 <value>0</value> 131 </enumeratedValue> 132 <enumeratedValue> 133 <name>release_scl</name> 134 <description>Release SCL.</description> 135 <value>1</value> 136 </enumeratedValue> 137 </enumeratedValues> 138 </field> 139 <!--FIELD 7 SDA Pin Control --> 140 <field> 141 <name>SDA_OUT</name> 142 <description>SDA Output. This bits control SDA output when SWOE = 1. </description> 143 <bitRange>[7:7]</bitRange> 144 <access>read-write</access> 145 <enumeratedValues> 146 <enumeratedValue> 147 <name>drive_sda_low</name> 148 <description>Drive SDA low. </description> 149 <value>0</value> 150 </enumeratedValue> 151 <enumeratedValue> 152 <name>release_sda</name> 153 <description>Release SDA.</description> 154 <value>1</value> 155 </enumeratedValue> 156 </enumeratedValues> 157 </field> 158 <!-- FIELD 8 SCL Status Read --> 159 <field> 160 <name>SCL</name> 161 <description>SCL status. This bit reflects the logic gate of SCL signal. </description> 162 <bitRange>[8:8]</bitRange> 163 <access>read-only</access> 164 </field> 165 <!-- FIELD 9 SDA Status Read --> 166 <field> 167 <name>SDA</name> 168 <description>SDA status. THis bit reflects the logic gate of SDA signal.</description> 169 <bitRange>[9:9]</bitRange> 170 <access>read-only</access> 171 </field> 172 <!-- FIELD 10 SOFTWARE OUTPUT ENABLE --> 173 <field> 174 <name>BB_EN</name> 175 <description>Software Output Enable.</description> 176 <bitRange>[10:10]</bitRange> 177 <access>read-write</access> 178 <enumeratedValues> 179 <enumeratedValue> 180 <name>outputs_disable</name> 181 <description>I2C Outputs SCLO and SDAO disabled. </description> 182 <value>0</value> 183 </enumeratedValue> 184 <enumeratedValue> 185 <name>outputs_enable</name> 186 <description>I2C Outputs SCLO and SDAO enabled.</description> 187 <value>1</value> 188 </enumeratedValue> 189 </enumeratedValues> 190 </field> 191 <!-- FIELD 11 READ/WRITE BIT STATUS --> 192 <field> 193 <name>READ</name> 194 <description>Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.</description> 195 <bitRange>[11:11]</bitRange> 196 <access>read-only</access> 197 <enumeratedValues> 198 <enumeratedValue> 199 <name>write</name> 200 <description>Write.</description> 201 <value>0</value> 202 </enumeratedValue> 203 <enumeratedValue> 204 <name>read</name> 205 <description>Read.</description> 206 <value>1</value> 207 </enumeratedValue> 208 </enumeratedValues> 209 </field> 210 <!-- FIELD 12 SCL Clock Stretch Control --> 211 <field> 212 <name>CLKSTR_DIS</name> 213 <description>This bit will disable slave clock stretching when set.</description> 214 <bitRange>[12:12]</bitRange> 215 <access>read-write</access> 216 <enumeratedValues> 217 <enumeratedValue> 218 <name>en</name> 219 <description>Slave clock stretching enabled.</description> 220 <value>0</value> 221 </enumeratedValue> 222 <enumeratedValue> 223 <name>dis</name> 224 <description>Slave clock stretching disabled.</description> 225 <value>1</value> 226 </enumeratedValue> 227 </enumeratedValues> 228 </field> 229 <!-- FIELD 13 SCL PULLUP CONTROL --> 230 <field> 231 <name>ONE_MST_MODE</name> 232 <description>SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. </description> 233 <bitRange>[13:13]</bitRange> 234 <access>read-write</access> 235 <enumeratedValues> 236 <enumeratedValue> 237 <name>dis</name> 238 <description>Standard open-drain operation: 239 drive low for 0, Hi-Z for 1</description> 240 <value>0</value> 241 </enumeratedValue> 242 <enumeratedValue> 243 <name>en</name> 244 <description>Non-standard push-pull operation: 245 drive low for 0, drive high for 1</description> 246 <value>1</value> 247 </enumeratedValue> 248 </enumeratedValues> 249 </field> 250 <!-- FIELD 15 High Speed Mode enable --> 251 <field> 252 <name>HS_EN</name> 253 <description>High speed mode enable</description> 254 <bitRange>[15:15]</bitRange> 255 <access>read-write</access> 256 </field> 257 </fields> 258 </register> 259 <register> 260 <name>STATUS</name> 261 <description>Status Register.</description> 262 <addressOffset>0x04</addressOffset> 263 <fields> 264 <field> 265 <name>BUSY</name> 266 <description>Bus Status.</description> 267 <bitRange>[0:0]</bitRange> 268 <access>read-only</access> 269 <enumeratedValues> 270 <enumeratedValue> 271 <name>idle</name> 272 <description>I2C Bus Idle.</description> 273 <value>0</value> 274 </enumeratedValue> 275 <enumeratedValue> 276 <name>busy</name> 277 <description>I2C Bus Busy.</description> 278 <value>1</value> 279 </enumeratedValue> 280 </enumeratedValues> 281 </field> 282 <field> 283 <name>RX_EM</name> 284 <description>RX empty.</description> 285 <bitRange>[1:1]</bitRange> 286 <access>read-only</access> 287 <enumeratedValues> 288 <enumeratedValue> 289 <name>not_empty</name> 290 <description>Not Empty.</description> 291 <value>0</value> 292 </enumeratedValue> 293 <enumeratedValue> 294 <name>empty</name> 295 <description>Empty.</description> 296 <value>1</value> 297 </enumeratedValue> 298 </enumeratedValues> 299 </field> 300 <field> 301 <name>RX_FULL</name> 302 <description>RX Full.</description> 303 <bitRange>[2:2]</bitRange> 304 <access>read-only</access> 305 <enumeratedValues> 306 <enumeratedValue> 307 <name>not_full</name> 308 <description>Not Full.</description> 309 <value>0</value> 310 </enumeratedValue> 311 <enumeratedValue> 312 <name>full</name> 313 <description>Full.</description> 314 <value>1</value> 315 </enumeratedValue> 316 </enumeratedValues> 317 </field> 318 <field> 319 <name>TX_EM</name> 320 <description>TX Empty.</description> 321 <bitRange>[3:3]</bitRange> 322 <enumeratedValues> 323 <enumeratedValue> 324 <name>not_empty</name> 325 <description>Not Empty.</description> 326 <value>0</value> 327 </enumeratedValue> 328 <enumeratedValue> 329 <name>empty</name> 330 <description>Empty.</description> 331 <value>1</value> 332 </enumeratedValue> 333 </enumeratedValues> 334 </field> 335 <field> 336 <name>TX_FULL</name> 337 <description>TX Full.</description> 338 <bitRange>[4:4]</bitRange> 339 <enumeratedValues> 340 <enumeratedValue> 341 <name>not_empty</name> 342 <description>Not Empty.</description> 343 <value>0</value> 344 </enumeratedValue> 345 <enumeratedValue> 346 <name>empty</name> 347 <description>Empty.</description> 348 <value>1</value> 349 </enumeratedValue> 350 </enumeratedValues> 351 </field> 352 <field> 353 <name>MST_BUSY</name> 354 <description>Clock Mode.</description> 355 <bitRange>[5:5]</bitRange> 356 <access>read-only</access> 357 <enumeratedValues> 358 <enumeratedValue> 359 <name>not_actively_driving_scl_clock</name> 360 <description>Device not actively driving SCL clock cycles.</description> 361 <value>0</value> 362 </enumeratedValue> 363 <enumeratedValue> 364 <name>actively_driving_scl_clock</name> 365 <description>Device operating as master and actively driving SCL clock cycles.</description> 366 <value>1</value> 367 </enumeratedValue> 368 </enumeratedValues> 369 </field> 370 </fields> 371 </register> 372 <register> 373 <name>INTFL0</name> 374 <description>Interrupt Status Register.</description> 375 <addressOffset>0x08</addressOffset> 376 <fields> 377 <field> 378 <name>DONE</name> 379 <description>Transfer Done Interrupt.</description> 380 <bitRange>[0:0]</bitRange> 381 <enumeratedValues> 382 <name>INT_FL0_Done</name> 383 <enumeratedValue> 384 <name>inactive</name> 385 <description>No Interrupt is Pending.</description> 386 <value>0</value> 387 </enumeratedValue> 388 <enumeratedValue> 389 <name>pending</name> 390 <description>An interrupt is pending.</description> 391 <value>1</value> 392 </enumeratedValue> 393 </enumeratedValues> 394 </field> 395 <field> 396 <name>IRXM</name> 397 <description>Interactive Receive Interrupt.</description> 398 <bitRange>[1:1]</bitRange> 399 <enumeratedValues> 400 <enumeratedValue> 401 <name>inactive</name> 402 <description>No Interrupt is Pending.</description> 403 <value>0</value> 404 </enumeratedValue> 405 <enumeratedValue> 406 <name>pending</name> 407 <description>An interrupt is pending.</description> 408 <value>1</value> 409 </enumeratedValue> 410 </enumeratedValues> 411 </field> 412 <field> 413 <name>GC_ADDR_MATCH</name> 414 <description>Slave General Call Address Match Interrupt.</description> 415 <bitRange>[2:2]</bitRange> 416 <enumeratedValues> 417 <enumeratedValue> 418 <name>inactive</name> 419 <description>No Interrupt is Pending.</description> 420 <value>0</value> 421 </enumeratedValue> 422 <enumeratedValue> 423 <name>pending</name> 424 <description>An interrupt is pending.</description> 425 <value>1</value> 426 </enumeratedValue> 427 </enumeratedValues> 428 </field> 429 <field> 430 <name>ADDR_MATCH</name> 431 <description>Slave Address Match Interrupt.</description> 432 <bitRange>[3:3]</bitRange> 433 <enumeratedValues> 434 <enumeratedValue> 435 <name>inactive</name> 436 <description>No Interrupt is Pending.</description> 437 <value>0</value> 438 </enumeratedValue> 439 <enumeratedValue> 440 <name>pending</name> 441 <description>An interrupt is pending.</description> 442 <value>1</value> 443 </enumeratedValue> 444 </enumeratedValues> 445 </field> 446 <field> 447 <name>RX_THD</name> 448 <description>Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.</description> 449 <bitRange>[4:4]</bitRange> 450 <enumeratedValues> 451 <enumeratedValue> 452 <name>inactive</name> 453 <description>No interrupt is pending.</description> 454 <value>0</value> 455 </enumeratedValue> 456 <enumeratedValue> 457 <name>pending</name> 458 <description>An interrupt is pending. RX_FIFO equal or more bytes than the threshold.</description> 459 <value>1</value> 460 </enumeratedValue> 461 </enumeratedValues> 462 </field> 463 <field> 464 <name>TX_THD</name> 465 <description>Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.</description> 466 <bitRange>[5:5]</bitRange> 467 <enumeratedValues> 468 <enumeratedValue> 469 <name>inactive</name> 470 <description>No interrupt is pending.</description> 471 <value>0</value> 472 </enumeratedValue> 473 <enumeratedValue> 474 <name>pending</name> 475 <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description> 476 <value>1</value> 477 </enumeratedValue> 478 </enumeratedValues> 479 </field> 480 <field> 481 <name>STOP</name> 482 <description>STOP Interrupt.</description> 483 <bitRange>[6:6]</bitRange> 484 <enumeratedValues> 485 <enumeratedValue> 486 <name>inactive</name> 487 <description>No interrupt is pending.</description> 488 <value>0</value> 489 </enumeratedValue> 490 <enumeratedValue> 491 <name>pending</name> 492 <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description> 493 <value>1</value> 494 </enumeratedValue> 495 </enumeratedValues> 496 </field> 497 <field> 498 <name>ADDR_ACK</name> 499 <description>Address Acknowledge Interrupt.</description> 500 <bitRange>[7:7]</bitRange> 501 <enumeratedValues> 502 <enumeratedValue> 503 <name>inactive</name> 504 <description>No Interrupt is Pending.</description> 505 <value>0</value> 506 </enumeratedValue> 507 <enumeratedValue> 508 <name>pending</name> 509 <description>An interrupt is pending.</description> 510 <value>1</value> 511 </enumeratedValue> 512 </enumeratedValues> 513 </field> 514 <field> 515 <name>ARB_ERR</name> 516 <description>Arbritation error Interrupt.</description> 517 <bitRange>[8:8]</bitRange> 518 <enumeratedValues> 519 <enumeratedValue> 520 <name>inactive</name> 521 <description>No Interrupt is Pending.</description> 522 <value>0</value> 523 </enumeratedValue> 524 <enumeratedValue> 525 <name>pending</name> 526 <description>An interrupt is pending.</description> 527 <value>1</value> 528 </enumeratedValue> 529 </enumeratedValues> 530 </field> 531 <field> 532 <name>TO_ERR</name> 533 <description>timeout Error Interrupt.</description> 534 <bitRange>[9:9]</bitRange> 535 <enumeratedValues> 536 <enumeratedValue> 537 <name>inactive</name> 538 <description>No Interrupt is Pending.</description> 539 <value>0</value> 540 </enumeratedValue> 541 <enumeratedValue> 542 <name>pending</name> 543 <description>An interrupt is pending.</description> 544 <value>1</value> 545 </enumeratedValue> 546 </enumeratedValues> 547 </field> 548 <field> 549 <name>ADDR_NACK_ERR</name> 550 <description>Address NACK Error Interrupt.</description> 551 <bitRange>[10:10]</bitRange> 552 <enumeratedValues> 553 <enumeratedValue> 554 <name>inactive</name> 555 <description>No Interrupt is Pending.</description> 556 <value>0</value> 557 </enumeratedValue> 558 <enumeratedValue> 559 <name>pending</name> 560 <description>An interrupt is pending.</description> 561 <value>1</value> 562 </enumeratedValue> 563 </enumeratedValues> 564 </field> 565 <field> 566 <name>DATA_ERR</name> 567 <description>Data NACK Error Interrupt.</description> 568 <bitRange>[11:11]</bitRange> 569 <enumeratedValues> 570 <enumeratedValue> 571 <name>inactive</name> 572 <description>No Interrupt is Pending.</description> 573 <value>0</value> 574 </enumeratedValue> 575 <enumeratedValue> 576 <name>pending</name> 577 <description>An interrupt is pending.</description> 578 <value>1</value> 579 </enumeratedValue> 580 </enumeratedValues> 581 </field> 582 <field> 583 <name>DNR_ERR</name> 584 <description>Do Not Respond Error Interrupt.</description> 585 <bitRange>[12:12]</bitRange> 586 <enumeratedValues> 587 <enumeratedValue> 588 <name>inactive</name> 589 <description>No Interrupt is Pending.</description> 590 <value>0</value> 591 </enumeratedValue> 592 <enumeratedValue> 593 <name>pending</name> 594 <description>An interrupt is pending.</description> 595 <value>1</value> 596 </enumeratedValue> 597 </enumeratedValues> 598 </field> 599 <field> 600 <name>START_ERR</name> 601 <description>Start Error Interrupt.</description> 602 <bitRange>[13:13]</bitRange> 603 <enumeratedValues> 604 <enumeratedValue> 605 <name>inactive</name> 606 <description>No Interrupt is Pending.</description> 607 <value>0</value> 608 </enumeratedValue> 609 <enumeratedValue> 610 <name>pending</name> 611 <description>An interrupt is pending.</description> 612 <value>1</value> 613 </enumeratedValue> 614 </enumeratedValues> 615 </field> 616 <field> 617 <name>STOP_ERR</name> 618 <description>Stop Error Interrupt.</description> 619 <bitRange>[14:14]</bitRange> 620 <enumeratedValues> 621 <enumeratedValue> 622 <name>inactive</name> 623 <description>No Interrupt is Pending.</description> 624 <value>0</value> 625 </enumeratedValue> 626 <enumeratedValue> 627 <name>pending</name> 628 <description>An interrupt is pending.</description> 629 <value>1</value> 630 </enumeratedValue> 631 </enumeratedValues> 632 </field> 633 <field> 634 <name>TX_LOCKOUT</name> 635 <description>Transmit Lock Out Interrupt.</description> 636 <bitRange>[15:15]</bitRange> 637 </field> 638 <field> 639 <name>MAMI</name> 640 <description>Multiple Address Match Interrupt</description> 641 <bitRange>[21:16]</bitRange> 642 </field> 643 <field> 644 <name>RD_ADDR_MATCH</name> 645 <description>Slave Read Address Match Interrupt</description> 646 <bitRange>[22:22]</bitRange> 647 </field> 648 <field> 649 <name>WR_ADDR_MATCH</name> 650 <description>Slave Write Address Match Interrupt</description> 651 <bitRange>[23:23]</bitRange> 652 </field> 653 </fields> 654 </register> 655 <register> 656 <name>INTEN0</name> 657 <description>Interrupt Enable Register.</description> 658 <addressOffset>0x0C</addressOffset> 659 <access>read-write</access> 660 <fields> 661 <field> 662 <name>DONE</name> 663 <description>Transfer Done Interrupt Enable.</description> 664 <bitRange>[0:0]</bitRange> 665 <access>read-write</access> 666 <enumeratedValues> 667 <enumeratedValue> 668 <name>dis</name> 669 <description>Interrupt disabled.</description> 670 <value>0</value> 671 </enumeratedValue> 672 <enumeratedValue> 673 <name>en</name> 674 <description>Interrupt enabled when DONE = 1.</description> 675 <value>1</value> 676 </enumeratedValue> 677 </enumeratedValues> 678 </field> 679 <field> 680 <name>IRXM</name> 681 <description>Description not available.</description> 682 <bitRange>[1:1]</bitRange> 683 <access>read-write</access> 684 <enumeratedValues> 685 <enumeratedValue> 686 <name>dis</name> 687 <description>Interrupt disabled.</description> 688 <value>0</value> 689 </enumeratedValue> 690 <enumeratedValue> 691 <name>en</name> 692 <description>Interrupt enabled when RX_MODE = 1.</description> 693 <value>1</value> 694 </enumeratedValue> 695 </enumeratedValues> 696 </field> 697 <field> 698 <name>GC_ADDR_MATCH</name> 699 <description>Slave mode general call address match received input enable.</description> 700 <bitRange>[2:2]</bitRange> 701 <access>read-write</access> 702 <enumeratedValues> 703 <enumeratedValue> 704 <name>dis</name> 705 <description>Interrupt disabled.</description> 706 <value>0</value> 707 </enumeratedValue> 708 <enumeratedValue> 709 <name>en</name> 710 <description>Interrupt enabled when GEN_CTRL_ADDR = 1.</description> 711 <value>1</value> 712 </enumeratedValue> 713 </enumeratedValues> 714 </field> 715 <field> 716 <name>ADDR_MATCH</name> 717 <description>Slave mode incoming address match interrupt.</description> 718 <bitRange>[3:3]</bitRange> 719 <access>read-write</access> 720 <enumeratedValues> 721 <enumeratedValue> 722 <name>dis</name> 723 <description>Interrupt disabled.</description> 724 <value>0</value> 725 </enumeratedValue> 726 <enumeratedValue> 727 <name>en</name> 728 <description>Interrupt enabled when ADDR_MATCH = 1.</description> 729 <value>1</value> 730 </enumeratedValue> 731 </enumeratedValues> 732 </field> 733 <field> 734 <name>RX_THD</name> 735 <description>RX FIFO Above Treshold Level Interrupt Enable.</description> 736 <bitRange>[4:4]</bitRange> 737 <access>read-write</access> 738 <enumeratedValues> 739 <enumeratedValue> 740 <name>dis</name> 741 <description>Interrupt disabled.</description> 742 <value>0</value> 743 </enumeratedValue> 744 <enumeratedValue> 745 <name>en</name> 746 <description>Interrupt enabled.</description> 747 <value>1</value> 748 </enumeratedValue> 749 </enumeratedValues> 750 </field> 751 <field> 752 <name>TX_THD</name> 753 <description>TX FIFO Below Treshold Level Interrupt Enable.</description> 754 <bitRange>[5:5]</bitRange> 755 <enumeratedValues> 756 <enumeratedValue> 757 <name>dis</name> 758 <description>Interrupt disabled.</description> 759 <value>0</value> 760 </enumeratedValue> 761 <enumeratedValue> 762 <name>en</name> 763 <description>Interrupt enabled.</description> 764 <value>1</value> 765 </enumeratedValue> 766 </enumeratedValues> 767 </field> 768 <field> 769 <name>STOP</name> 770 <description>Stop Interrupt Enable</description> 771 <bitRange>[6:6]</bitRange> 772 <access>read-write</access> 773 <enumeratedValues> 774 <enumeratedValue> 775 <name>dis</name> 776 <description>Interrupt disabled.</description> 777 <value>0</value> 778 </enumeratedValue> 779 <enumeratedValue> 780 <name>en</name> 781 <description>Interrupt enabled when STOP = 1.</description> 782 <value>1</value> 783 </enumeratedValue> 784 </enumeratedValues> 785 </field> 786 <field> 787 <name>ADDR_ACK</name> 788 <description>Received Address ACK from Slave Interrupt.</description> 789 <bitRange>[7:7]</bitRange> 790 <enumeratedValues> 791 <enumeratedValue> 792 <name>dis</name> 793 <description>Interrupt disabled.</description> 794 <value>0</value> 795 </enumeratedValue> 796 <enumeratedValue> 797 <name>en</name> 798 <description>Interrupt enabled.</description> 799 <value>1</value> 800 </enumeratedValue> 801 </enumeratedValues> 802 </field> 803 <field> 804 <name>ARB_ERR</name> 805 <description>Master Mode Arbitration Lost Interrupt.</description> 806 <bitRange>[8:8]</bitRange> 807 <enumeratedValues> 808 <enumeratedValue> 809 <name>dis</name> 810 <description>Interrupt disabled.</description> 811 <value>0</value> 812 </enumeratedValue> 813 <enumeratedValue> 814 <name>en</name> 815 <description>Interrupt enabled.</description> 816 <value>1</value> 817 </enumeratedValue> 818 </enumeratedValues> 819 </field> 820 <field> 821 <name>TO_ERR</name> 822 <description>Timeout Error Interrupt Enable.</description> 823 <bitRange>[9:9]</bitRange> 824 <enumeratedValues> 825 <enumeratedValue> 826 <name>dis</name> 827 <description>Interrupt disabled.</description> 828 <value>0</value> 829 </enumeratedValue> 830 <enumeratedValue> 831 <name>en</name> 832 <description>Interrupt enabled.</description> 833 <value>1</value> 834 </enumeratedValue> 835 </enumeratedValues> 836 </field> 837 <field> 838 <name>ADDR_NACK_ERR</name> 839 <description>Master Mode Address NACK Received Interrupt.</description> 840 <bitRange>[10:10]</bitRange> 841 <enumeratedValues> 842 <enumeratedValue> 843 <name>dis</name> 844 <description>Interrupt disabled.</description> 845 <value>0</value> 846 </enumeratedValue> 847 <enumeratedValue> 848 <name>en</name> 849 <description>Interrupt enabled.</description> 850 <value>1</value> 851 </enumeratedValue> 852 </enumeratedValues> 853 </field> 854 <field> 855 <name>DATA_ERR</name> 856 <description>Master Mode Data NACK Received Interrupt.</description> 857 <bitRange>[11:11]</bitRange> 858 <enumeratedValues> 859 <enumeratedValue> 860 <name>dis</name> 861 <description>Interrupt disabled.</description> 862 <value>0</value> 863 </enumeratedValue> 864 <enumeratedValue> 865 <name>en</name> 866 <description>Interrupt enabled.</description> 867 <value>1</value> 868 </enumeratedValue> 869 </enumeratedValues> 870 </field> 871 <field> 872 <name>DNR_ERR</name> 873 <description>Slave Mode Do Not Respond Interrupt.</description> 874 <bitRange>[12:12]</bitRange> 875 <enumeratedValues> 876 <enumeratedValue> 877 <name>dis</name> 878 <description>Interrupt disabled.</description> 879 <value>0</value> 880 </enumeratedValue> 881 <enumeratedValue> 882 <name>en</name> 883 <description>Interrupt enabled.</description> 884 <value>1</value> 885 </enumeratedValue> 886 </enumeratedValues> 887 </field> 888 <field> 889 <name>START_ERR</name> 890 <description>Out of Sequence START condition detected interrupt.</description> 891 <bitRange>[13:13]</bitRange> 892 <enumeratedValues> 893 <enumeratedValue> 894 <name>dis</name> 895 <description>Interrupt disabled.</description> 896 <value>0</value> 897 </enumeratedValue> 898 <enumeratedValue> 899 <name>en</name> 900 <description>Interrupt enabled.</description> 901 <value>1</value> 902 </enumeratedValue> 903 </enumeratedValues> 904 </field> 905 <field> 906 <name>STOP_ERR</name> 907 <description>Out of Sequence STOP condition detected interrupt.</description> 908 <bitRange>[14:14]</bitRange> 909 <enumeratedValues> 910 <enumeratedValue> 911 <name>dis</name> 912 <description>Interrupt disabled.</description> 913 <value>0</value> 914 </enumeratedValue> 915 <enumeratedValue> 916 <name>en</name> 917 <description>Interrupt enabled.</description> 918 <value>1</value> 919 </enumeratedValue> 920 </enumeratedValues> 921 </field> 922 <field> 923 <name>TX_LOCKOUT</name> 924 <description>TX FIFO Locked Out Interrupt.</description> 925 <bitRange>[15:15]</bitRange> 926 </field> 927 <field> 928 <name>MAMI</name> 929 <description>Multiple Address Match Interrupt</description> 930 <bitRange>[21:16]</bitRange> 931 </field> 932 <field> 933 <name>RD_ADDR_MATCH</name> 934 <description>Slave Read Address Match Interrupt</description> 935 <bitRange>[22:22]</bitRange> 936 </field> 937 <field> 938 <name>WR_ADDR_MATCH</name> 939 <description>Slave Write Address Match Interrupt</description> 940 <bitRange>[23:23]</bitRange> 941 </field> 942 </fields> 943 </register> 944 <register> 945 <name>INTFL1</name> 946 <description>Interrupt Status Register 1.</description> 947 <addressOffset>0x10</addressOffset> 948 <fields> 949 <field> 950 <name>RX_OV</name> 951 <description>Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.</description> 952 <bitRange>[0:0]</bitRange> 953 <enumeratedValues> 954 <enumeratedValue> 955 <name>inactive</name> 956 <description>No Interrupt is Pending.</description> 957 <value>0</value> 958 </enumeratedValue> 959 <enumeratedValue> 960 <name>pending</name> 961 <description>An interrupt is pending.</description> 962 <value>1</value> 963 </enumeratedValue> 964 </enumeratedValues> 965 </field> 966 <field> 967 <name>TX_UN</name> 968 <description>Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).</description> 969 <bitRange>[1:1]</bitRange> 970 <enumeratedValues> 971 <enumeratedValue> 972 <name>inactive</name> 973 <description>No Interrupt is Pending.</description> 974 <value>0</value> 975 </enumeratedValue> 976 <enumeratedValue> 977 <name>pending</name> 978 <description>An interrupt is pending.</description> 979 <value>1</value> 980 </enumeratedValue> 981 </enumeratedValues> 982 </field> 983 <field> 984 <name>START</name> 985 <description>START Condition Status Flag.</description> 986 <bitRange>[2:2]</bitRange> 987 </field> 988 </fields> 989 </register> 990 <register> 991 <name>INTEN1</name> 992 <description>Interrupt Staus Register 1.</description> 993 <addressOffset>0x14</addressOffset> 994 <access>read-write</access> 995 <fields> 996 <field> 997 <name>RX_OV</name> 998 <description>Receiver Overflow Interrupt Enable.</description> 999 <bitRange>[0:0]</bitRange> 1000 <enumeratedValues> 1001 <enumeratedValue> 1002 <name>dis</name> 1003 <description>No Interrupt is Pending.</description> 1004 <value>0</value> 1005 </enumeratedValue> 1006 <enumeratedValue> 1007 <name>en</name> 1008 <description>An interrupt is pending.</description> 1009 <value>1</value> 1010 </enumeratedValue> 1011 </enumeratedValues> 1012 </field> 1013 <field> 1014 <name>TX_UN</name> 1015 <description>Transmit Underflow Interrupt Enable.</description> 1016 <bitRange>[1:1]</bitRange> 1017 <enumeratedValues> 1018 <enumeratedValue> 1019 <name>dis</name> 1020 <description>No Interrupt is Pending.</description> 1021 <value>0</value> 1022 </enumeratedValue> 1023 <enumeratedValue> 1024 <name>en</name> 1025 <description>An interrupt is pending.</description> 1026 <value>1</value> 1027 </enumeratedValue> 1028 </enumeratedValues> 1029 </field> 1030 <field> 1031 <name>START</name> 1032 <description>START Condition Interrupt Enable.</description> 1033 <bitRange>[2:2]</bitRange> 1034 </field> 1035 </fields> 1036 </register> 1037 <register> 1038 <name>FIFOLEN</name> 1039 <description>FIFO Configuration Register.</description> 1040 <addressOffset>0x18</addressOffset> 1041 <fields> 1042 <field> 1043 <name>RX_DEPTH</name> 1044 <description>Receive FIFO Length.</description> 1045 <bitRange>[7:0]</bitRange> 1046 <access>read-only</access> 1047 </field> 1048 <field> 1049 <name>TX_DEPTH</name> 1050 <description>Transmit FIFO Length.</description> 1051 <bitRange>[15:8]</bitRange> 1052 <access>read-only</access> 1053 </field> 1054 </fields> 1055 </register> 1056 <register> 1057 <name>RXCTRL0</name> 1058 <description>Receive Control Register 0.</description> 1059 <addressOffset>0x1C</addressOffset> 1060 <fields> 1061 <field> 1062 <name>DNR</name> 1063 <description>Do Not Respond.</description> 1064 <bitRange>[0:0]</bitRange> 1065 <enumeratedValues> 1066 <enumeratedValue> 1067 <name>respond</name> 1068 <description>Always respond to address match.</description> 1069 <value>0</value> 1070 </enumeratedValue> 1071 <enumeratedValue> 1072 <name>not_respond_rx_fifo_empty</name> 1073 <description>Do not respond to address match when RX_FIFO is not empty.</description> 1074 <value>1</value> 1075 </enumeratedValue> 1076 </enumeratedValues> 1077 </field> 1078 <field> 1079 <name>FLUSH</name> 1080 <description>Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.</description> 1081 <bitRange>[7:7]</bitRange> 1082 <enumeratedValues> 1083 <enumeratedValue> 1084 <name>not_flushed</name> 1085 <description>FIFO not flushed.</description> 1086 <value>0</value> 1087 </enumeratedValue> 1088 <enumeratedValue> 1089 <name>flush</name> 1090 <description>Flush RX_FIFO.</description> 1091 <value>1</value> 1092 </enumeratedValue> 1093 </enumeratedValues> 1094 </field> 1095 <field> 1096 <name>THD_LVL</name> 1097 <description>Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.</description> 1098 <bitRange>[11:8]</bitRange> 1099 </field> 1100 </fields> 1101 </register> 1102 <register> 1103 <name>RXCTRL1</name> 1104 <description>Receive Control Register 1.</description> 1105 <addressOffset>0x20</addressOffset> 1106 <fields> 1107 <field> 1108 <name>CNT</name> 1109 <description>Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction.</description> 1110 <bitRange>[7:0]</bitRange> 1111 </field> 1112 <field> 1113 <name>LVL</name> 1114 <description>Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0.</description> 1115 <bitRange>[11:8]</bitRange> 1116 <access>read-only</access> 1117 </field> 1118 </fields> 1119 </register> 1120 <register> 1121 <name>TXCTRL0</name> 1122 <description>Transmit Control Register 0.</description> 1123 <addressOffset>0x24</addressOffset> 1124 <fields> 1125 <field> 1126 <name>PRELOAD_MODE</name> 1127 <description>Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match.</description> 1128 <bitRange>[0:0]</bitRange> 1129 </field> 1130 <field> 1131 <name>TX_READY_MODE</name> 1132 <description>Transmit FIFO Ready Manual Mode.</description> 1133 <bitRange>[1:1]</bitRange> 1134 <enumeratedValues> 1135 <enumeratedValue> 1136 <name>en</name> 1137 <description>HW control of I2CTXRDY enabled.</description> 1138 <value>0</value> 1139 </enumeratedValue> 1140 <enumeratedValue> 1141 <name>dis</name> 1142 <description>HW control of I2CTXRDY disabled.</description> 1143 <value>1</value> 1144 </enumeratedValue> 1145 </enumeratedValues> 1146 </field> 1147 <field> 1148 <name>GC_ADDR_FLUSH_DIS</name> 1149 <description>TX FIFO General Call Address Match Auto Flush Disable.</description> 1150 <bitRange>[2:2]</bitRange> 1151 <enumeratedValues> 1152 <enumeratedValue> 1153 <name>en</name> 1154 <description>Enabled.</description> 1155 <value>0</value> 1156 </enumeratedValue> 1157 <enumeratedValue> 1158 <name>dis</name> 1159 <description>Disabled.</description> 1160 <value>1</value> 1161 </enumeratedValue> 1162 </enumeratedValues> 1163 </field> 1164 <field> 1165 <name>WR_ADDR_FLUSH_DIS</name> 1166 <description>TX FIFO Slave Address Match Write Auto Flush Disable.</description> 1167 <bitRange>[3:3]</bitRange> 1168 <enumeratedValues> 1169 <enumeratedValue> 1170 <name>en</name> 1171 <description>Enabled.</description> 1172 <value>0</value> 1173 </enumeratedValue> 1174 <enumeratedValue> 1175 <name>dis</name> 1176 <description>Disabled.</description> 1177 <value>1</value> 1178 </enumeratedValue> 1179 </enumeratedValues> 1180 </field> 1181 <field> 1182 <name>RD_ADDR_FLUSH_DIS</name> 1183 <description>TX FIFO Slave Address Match Read Auto Flush Disable.</description> 1184 <bitRange>[4:4]</bitRange> 1185 <enumeratedValues> 1186 <enumeratedValue> 1187 <name>en</name> 1188 <description>Enabled.</description> 1189 <value>0</value> 1190 </enumeratedValue> 1191 <enumeratedValue> 1192 <name>dis</name> 1193 <description>Disabled.</description> 1194 <value>1</value> 1195 </enumeratedValue> 1196 </enumeratedValues> 1197 </field> 1198 <field> 1199 <name>NACK_FLUSH_DIS</name> 1200 <description>TX FIFO received NACK Auto Flush Disable.</description> 1201 <bitRange>[5:5]</bitRange> 1202 <enumeratedValues> 1203 <enumeratedValue> 1204 <name>en</name> 1205 <description>Enabled.</description> 1206 <value>0</value> 1207 </enumeratedValue> 1208 <enumeratedValue> 1209 <name>dis</name> 1210 <description>Disabled.</description> 1211 <value>1</value> 1212 </enumeratedValue> 1213 </enumeratedValues> 1214 </field> 1215 <field> 1216 <name>FLUSH</name> 1217 <description>Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.</description> 1218 <bitRange>[7:7]</bitRange> 1219 <enumeratedValues> 1220 <enumeratedValue> 1221 <name>not_flushed</name> 1222 <description>FIFO not flushed.</description> 1223 <value>0</value> 1224 </enumeratedValue> 1225 <enumeratedValue> 1226 <name>flush</name> 1227 <description>Flush TX_FIFO.</description> 1228 <value>1</value> 1229 </enumeratedValue> 1230 </enumeratedValues> 1231 </field> 1232 <field> 1233 <name>THD_VAL</name> 1234 <description>Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold.</description> 1235 <bitRange>[11:8]</bitRange> 1236 </field> 1237 </fields> 1238 </register> 1239 <register> 1240 <name>TXCTRL1</name> 1241 <description>Transmit Control Register 1.</description> 1242 <addressOffset>0x28</addressOffset> 1243 <fields> 1244 <field> 1245 <name>PRELOAD_RDY</name> 1246 <description>Transmit FIFO Preload Ready.</description> 1247 <bitRange>[0:0]</bitRange> 1248 </field> 1249 <field> 1250 <name>LAST</name> 1251 <description>Transmit Last.</description> 1252 <bitRange>[1:1]</bitRange> 1253 </field> 1254 <field> 1255 <name>LVL</name> 1256 <description>Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO.</description> 1257 <bitRange>[11:8]</bitRange> 1258 <access>read-only</access> 1259 </field> 1260 </fields> 1261 </register> 1262 <register> 1263 <name>FIFO</name> 1264 <description>Data Register.</description> 1265 <addressOffset>0x2C</addressOffset> 1266 <fields> 1267 <field> 1268 <name>DATA</name> 1269 <description>Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location.</description> 1270 <bitOffset>0</bitOffset> 1271 <bitWidth>8</bitWidth> 1272 </field> 1273 </fields> 1274 </register> 1275 <register> 1276 <name>MSTCTRL</name> 1277 <description>Master Control Register.</description> 1278 <addressOffset>0x30</addressOffset> 1279 <fields> 1280 <field> 1281 <name>START</name> 1282 <description>Setting this bit to 1 will start a master transfer.</description> 1283 <bitRange>[0:0]</bitRange> 1284 </field> 1285 <field> 1286 <name>RESTART</name> 1287 <description>Setting this bit to 1 will generate a repeated START.</description> 1288 <bitRange>[1:1]</bitRange> 1289 </field> 1290 <field> 1291 <name>STOP</name> 1292 <description>Setting this bit to 1 will generate a STOP condition.</description> 1293 <bitRange>[2:2]</bitRange> 1294 </field> 1295 <field> 1296 <name>EX_ADDR_EN</name> 1297 <description>Slave Extend Address Select.</description> 1298 <bitRange>[7:7]</bitRange> 1299 <enumeratedValues> 1300 <enumeratedValue> 1301 <name>7_bits_address</name> 1302 <description>7-bit address.</description> 1303 <value>0</value> 1304 </enumeratedValue> 1305 <enumeratedValue> 1306 <name>10_bits_address</name> 1307 <description>10-bit address.</description> 1308 <value>1</value> 1309 </enumeratedValue> 1310 </enumeratedValues> 1311 </field> 1312 <field> 1313 <name>CODE</name> 1314 <description>Master Code.</description> 1315 <bitRange>[10:8]</bitRange> 1316 </field> 1317 <field> 1318 <name>IGN_ACK</name> 1319 <description>Master Ignore Acknowledge.</description> 1320 <bitRange>[12:12]</bitRange> 1321 </field> 1322 </fields> 1323 </register> 1324 <register> 1325 <name>CLKLO</name> 1326 <description>Clock Low Register.</description> 1327 <addressOffset>0x34</addressOffset> 1328 <fields> 1329 <field> 1330 <name>LO</name> 1331 <description>Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.</description> 1332 <bitRange>[8:0]</bitRange> 1333 </field> 1334 </fields> 1335 </register> 1336 <register> 1337 <name>CLKHI</name> 1338 <description>Clock high Register.</description> 1339 <addressOffset>0x38</addressOffset> 1340 <fields> 1341 <field> 1342 <name>HI</name> 1343 <description>Clock High. In master mode, these bits define the SCL high period.</description> 1344 <bitRange>[8:0]</bitRange> 1345 </field> 1346 </fields> 1347 </register> 1348 <register> 1349 <name>HSCLK</name> 1350 <description>Clock high Register.</description> 1351 <addressOffset>0x3C</addressOffset> 1352 <fields> 1353 <field> 1354 <name>LO</name> 1355 <description>Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA.</description> 1356 <bitRange>[7:0]</bitRange> 1357 </field> 1358 <field> 1359 <name>HI</name> 1360 <description>Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA</description> 1361 <bitRange>[15:8]</bitRange> 1362 </field> 1363 </fields> 1364 </register> 1365 <register> 1366 <name>TIMEOUT</name> 1367 <description>Timeout Register</description> 1368 <addressOffset>0x40</addressOffset> 1369 <fields> 1370 <field> 1371 <name>SCL_TO_VAL</name> 1372 <description>Timeout</description> 1373 <bitRange>[15:0]</bitRange> 1374 </field> 1375 </fields> 1376 </register> 1377 <register> 1378 <name>DMA</name> 1379 <description>DMA Register.</description> 1380 <addressOffset>0x48</addressOffset> 1381 <fields> 1382 <field> 1383 <name>TX_EN</name> 1384 <description>TX channel enable.</description> 1385 <bitRange>[0:0]</bitRange> 1386 <enumeratedValues> 1387 <enumeratedValue> 1388 <name>dis</name> 1389 <description>Disable.</description> 1390 <value>0</value> 1391 </enumeratedValue> 1392 <enumeratedValue> 1393 <name>en</name> 1394 <description>Enable.</description> 1395 <value>1</value> 1396 </enumeratedValue> 1397 </enumeratedValues> 1398 </field> 1399 <field> 1400 <name>RX_EN</name> 1401 <description>RX channel enable.</description> 1402 <bitRange>[1:1]</bitRange> 1403 <enumeratedValues> 1404 <enumeratedValue> 1405 <name>dis</name> 1406 <description>Disable.</description> 1407 <value>0</value> 1408 </enumeratedValue> 1409 <enumeratedValue> 1410 <name>en</name> 1411 <description>Enable.</description> 1412 <value>1</value> 1413 </enumeratedValue> 1414 </enumeratedValues> 1415 </field> 1416 </fields> 1417 </register> 1418 <register> 1419 <dim>4</dim> 1420 <dimIncrement>4</dimIncrement> 1421 <name>SLAVE_MULTI[%s]</name> 1422 <description>Slave Address Register.</description> 1423 <alternateRegister>SLAVE0</alternateRegister> 1424 <addressOffset>0x4C</addressOffset> 1425 <size>32</size> 1426 <access>read-write</access> 1427 <fields> 1428 <field> 1429 <name>ADDR</name> 1430 <description>Slave Address.</description> 1431 <bitRange>[9:0]</bitRange> 1432 </field> 1433 <field> 1434 <name>DIS</name> 1435 <description>Slave Disable.</description> 1436 <bitRange>[10:10]</bitRange> 1437 </field> 1438 <field> 1439 <name>EXT_ADDR_EN</name> 1440 <description>Extended Address Select.</description> 1441 <bitRange>[15:15]</bitRange> 1442 <enumeratedValues> 1443 <enumeratedValue> 1444 <name>7_bits_address</name> 1445 <description>7-bit address.</description> 1446 <value>0</value> 1447 </enumeratedValue> 1448 <enumeratedValue> 1449 <name>10_bits_address</name> 1450 <description>10-bit address.</description> 1451 <value>1</value> 1452 </enumeratedValue> 1453 </enumeratedValues> 1454 </field> 1455 </fields> 1456 </register> 1457 <register> 1458 <name>SLAVE0</name> 1459 <description>Slave Address Register.</description> 1460 <addressOffset>0x4C</addressOffset> 1461 </register> 1462 <register> 1463 <name>SLAVE1</name> 1464 <description>Slave Address Register.</description> 1465 <addressOffset>0x50</addressOffset> 1466 </register> 1467 <register> 1468 <name>SLAVE2</name> 1469 <description>Slave Address Register.</description> 1470 <addressOffset>0x54</addressOffset> 1471 </register> 1472 <register> 1473 <name>SLAVE3</name> 1474 <description>Slave Address Register.</description> 1475 <addressOffset>0x58</addressOffset> 1476 </register> 1477 </registers> 1478 </peripheral> 1479 <!-- I2C1: Inter-Intergrated Circuit 1 --> 1480</device>
