1<?xml version="1.0" encoding="utf-8" standalone="no"?>
2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd">
3 <peripheral>
4  <name>HTMR</name>
5  <description>High Speed Timer Module.</description>
6  <baseAddress>0x4001B000</baseAddress>
7  <addressBlock>
8   <offset>0x00</offset>
9   <size>0xFFF</size>
10   <usage>registers</usage>
11  </addressBlock>
12  <interrupt>
13   <name>HTimer</name>
14   <description>HTimer interrupt.</description>
15   <value>93</value>
16  </interrupt>
17  <registers>
18   <register>
19    <name>SEC</name>
20    <description>HTimer Long-Interval Counter. This register contains the 32 most significant bits of the counter.</description>
21    <addressOffset>0x00</addressOffset>
22    <resetMask>0x00000000</resetMask>
23   </register>
24   <register>
25    <name>SSEC</name>
26    <description>HTimer Short Interval Counter. This counter ticks ever t_htclk (16.48uS). HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00.</description>
27    <addressOffset>0x04</addressOffset>
28    <resetMask>0x00000000</resetMask>
29    <fields>
30     <field>
31      <name>RTSS</name>
32      <description>HTimer Short Interval Counter.</description>
33      <bitOffset>0</bitOffset>
34      <bitWidth>8</bitWidth>
35     </field>
36    </fields>
37   </register>
38   <register>
39    <name>RAS</name>
40    <description>Long Interval Alarm.</description>
41    <addressOffset>0x08</addressOffset>
42    <resetMask>0x00000000</resetMask>
43    <fields>
44     <field>
45      <name>RAS</name>
46      <description>HTimer Long Interval Alarm. An Alarm is triggered when this value matches HTIMER_SEC[19:0]</description>
47      <bitOffset>0</bitOffset>
48      <bitWidth>20</bitWidth>
49     </field>
50    </fields>
51   </register>
52   <register>
53    <name>RSSA</name>
54    <description>HTimer Short Interval Alarm. This register contains the reload value for the short interval alarm, HTIMER_CTRL.alarm_ss_fl is raised on rollover.</description>
55    <addressOffset>0x0C</addressOffset>
56    <resetMask>0x00000000</resetMask>
57    <fields>
58     <field>
59      <name>RSSA</name>
60      <description>This register contains the reload value for the short interval alarm.</description>
61      <bitOffset>0</bitOffset>
62      <bitWidth>32</bitWidth>
63     </field>
64    </fields>
65   </register>
66   <register>
67    <name>CTRL</name>
68    <description>HTimer Control Register.</description>
69    <addressOffset>0x10</addressOffset>
70    <resetValue>0x00000008</resetValue>
71    <resetMask>0xFFFFFF38</resetMask>
72    <fields>
73     <field>
74      <name>HTEN</name>
75      <description>HTimer Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description>
76      <bitOffset>0</bitOffset>
77      <bitWidth>1</bitWidth>
78      <enumeratedValues>
79       <enumeratedValue>
80        <name>dis</name>
81        <description>Disable.</description>
82        <value>0</value>
83       </enumeratedValue>
84       <enumeratedValue>
85        <name>en</name>
86        <description>Enable.</description>
87        <value>1</value>
88       </enumeratedValue>
89      </enumeratedValues>
90     </field>
91     <field>
92      <name>ADE</name>
93      <description>Long Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description>
94      <bitOffset>1</bitOffset>
95      <bitWidth>1</bitWidth>
96      <enumeratedValues>
97       <enumeratedValue>
98        <name>dis</name>
99        <description>Disable.</description>
100        <value>0</value>
101       </enumeratedValue>
102       <enumeratedValue>
103        <name>en</name>
104        <description>Enable.</description>
105        <value>1</value>
106       </enumeratedValue>
107      </enumeratedValues>
108     </field>
109     <field>
110      <name>ASE</name>
111      <description>Short Interval Alarm Interrupt Enable.  Change to this bit is effective only after BUSY is cleared from 1 to 0.</description>
112      <bitOffset>2</bitOffset>
113      <bitWidth>1</bitWidth>
114      <enumeratedValues>
115       <enumeratedValue>
116        <name>dis</name>
117        <description>Disable.</description>
118        <value>0</value>
119       </enumeratedValue>
120       <enumeratedValue>
121        <name>en</name>
122        <description>Enable.</description>
123        <value>1</value>
124       </enumeratedValue>
125      </enumeratedValues>
126     </field>
127     <field>
128      <name>BUSY</name>
129      <description>HTimer Busy. This bit is set to 1 by hardware when changes to HTimer registers required a synchronized version of the register to be in place.  This bit is automatically cleared by hardware.</description>
130      <bitOffset>3</bitOffset>
131      <bitWidth>1</bitWidth>
132      <access>read-only</access>
133      <enumeratedValues>
134       <enumeratedValue>
135        <name>idle</name>
136        <description>Idle.</description>
137        <value>0</value>
138       </enumeratedValue>
139       <enumeratedValue>
140        <name>busy</name>
141        <description>Busy.</description>
142        <value>1</value>
143       </enumeratedValue>
144      </enumeratedValues>
145     </field>
146     <field>
147      <name>RDY</name>
148      <description>HTimer Ready. This bit is set to 1 by hardware when the HTimer count registers update.  It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the HTimer count register.</description>
149      <bitOffset>4</bitOffset>
150      <bitWidth>1</bitWidth>
151      <enumeratedValues>
152       <enumeratedValue>
153        <name>busy</name>
154        <description>Register has not updated.</description>
155        <value>0</value>
156       </enumeratedValue>
157       <enumeratedValue>
158        <name>ready</name>
159        <description>Ready.</description>
160        <value>1</value>
161       </enumeratedValue>
162      </enumeratedValues>
163     </field>
164     <field>
165      <name>RDYE</name>
166      <description>HTimer Ready Interrupt Enable.</description>
167      <bitOffset>5</bitOffset>
168      <bitWidth>1</bitWidth>
169      <enumeratedValues>
170       <enumeratedValue>
171        <name>dis</name>
172        <description>Disable.</description>
173        <value>0</value>
174       </enumeratedValue>
175       <enumeratedValue>
176        <name>en</name>
177        <description>Enable.</description>
178        <value>1</value>
179       </enumeratedValue>
180      </enumeratedValues>
181     </field>
182     <field>
183      <name>ALDF</name>
184      <description>Long Interval Alarm Interrupt Flag.  This alarm is qualified as wake-up source to the processor.</description>
185      <bitOffset>6</bitOffset>
186      <bitWidth>1</bitWidth>
187      <access>read-only</access>
188      <enumeratedValues>
189       <enumeratedValue>
190        <name>inactive</name>
191        <description>Not active</description>
192        <value>0</value>
193       </enumeratedValue>
194       <enumeratedValue>
195        <name>pending</name>
196        <description>Active</description>
197        <value>1</value>
198       </enumeratedValue>
199      </enumeratedValues>
200     </field>
201     <field>
202      <name>ALSF</name>
203      <description>Short Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description>
204      <bitOffset>7</bitOffset>
205      <bitWidth>1</bitWidth>
206      <access>read-only</access>
207      <enumeratedValues>
208       <enumeratedValue>
209        <name>inactive</name>
210        <description>Not active</description>
211        <value>0</value>
212       </enumeratedValue>
213       <enumeratedValue>
214        <name>Pending</name>
215        <description>Active</description>
216        <value>1</value>
217       </enumeratedValue>
218      </enumeratedValues>
219     </field>
220     <field>
221      <name>ACRE</name>
222      <description>Asynchronous Counter Read Enable, allows direct read access to sec and ssec counters regardless of the ready flag.</description>
223      <bitOffset>14</bitOffset>
224      <bitWidth>1</bitWidth>
225      <access>read-only</access>
226      <enumeratedValues>
227       <enumeratedValue>
228        <name>disabled</name>
229        <description>Not allowed</description>
230        <value>0</value>
231       </enumeratedValue>
232       <enumeratedValue>
233        <name>enabled</name>
234        <description>Allowed</description>
235        <value>1</value>
236       </enumeratedValue>
237      </enumeratedValues>
238     </field>
239     <field>
240      <name>WE</name>
241      <description>Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical HTimer bits.</description>
242      <bitOffset>15</bitOffset>
243      <bitWidth>1</bitWidth>
244      <enumeratedValues>
245       <enumeratedValue>
246        <name>dis</name>
247        <description>Not active</description>
248        <value>0</value>
249       </enumeratedValue>
250       <enumeratedValue>
251        <name>en</name>
252        <description>Active</description>
253        <value>1</value>
254       </enumeratedValue>
255      </enumeratedValues>
256     </field>
257    </fields>
258   </register>
259  </registers>
260 </peripheral>
261<!-- HTIMER :
262                                                 High Speed Timer and Alarm-->
263</device>
264