1 /** 2 * @file hpb_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the HPB_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_HPB_HPB_REVA_REGS_H_ 27 #define LIBRARIES_PERIPHDRIVERS_SOURCE_HPB_HPB_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup hpb_reva 65 * @defgroup hpb_reva_registers HPB_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the HPB_REVA Peripheral Module. 67 * @details HyperBus Memory Controller Registers 68 */ 69 70 /** 71 * @ingroup hpb_reva_registers 72 * Structure type to access the HPB_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t stat; /**< <tt>\b 0x0000:</tt> HPB_REVA STAT Register */ 76 __IO uint32_t inten; /**< <tt>\b 0x0004:</tt> HPB_REVA INTEN Register */ 77 __IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> HPB_REVA INTFL Register */ 78 __R uint32_t rsv_0xc; 79 __IO uint32_t membaddr[2]; /**< <tt>\b 0x0010:</tt> HPB_REVA MEMBADDR Register */ 80 __R uint32_t rsv_0x18_0x1f[2]; 81 __IO uint32_t memctrl[2]; /**< <tt>\b 0x0020:</tt> HPB_REVA MEMCTRL Register */ 82 __R uint32_t rsv_0x28_0x2f[2]; 83 __IO uint32_t memtim[2]; /**< <tt>\b 0x0030:</tt> HPB_REVA MEMTIM Register */ 84 } mxc_hpb_reva_regs_t; 85 86 /* Register offsets for module HPB_REVA */ 87 /** 88 * @ingroup hpb_reva_registers 89 * @defgroup HPB_REVA_Register_Offsets Register Offsets 90 * @brief HPB_REVA Peripheral Register Offsets from the HPB_REVA Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_HPB_REVA_STAT ((uint32_t)0x00000000UL) /**< Offset from HPB_REVA Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_HPB_REVA_INTEN ((uint32_t)0x00000004UL) /**< Offset from HPB_REVA Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_HPB_REVA_INTFL ((uint32_t)0x00000008UL) /**< Offset from HPB_REVA Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_HPB_REVA_MEMBADDR ((uint32_t)0x00000010UL) /**< Offset from HPB_REVA Base Address: <tt> 0x0010</tt> */ 97 #define MXC_R_HPB_REVA_MEMCTRL ((uint32_t)0x00000020UL) /**< Offset from HPB_REVA Base Address: <tt> 0x0020</tt> */ 98 #define MXC_R_HPB_REVA_MEMTIM ((uint32_t)0x00000030UL) /**< Offset from HPB_REVA Base Address: <tt> 0x0030</tt> */ 99 /**@} end of group hpb_reva_registers */ 100 101 /** 102 * @ingroup hpb_reva_registers 103 * @defgroup HPB_REVA_STAT HPB_REVA_STAT 104 * @brief HPB Status Register. 105 * @{ 106 */ 107 #define MXC_F_HPB_REVA_STAT_RDTXN_POS 0 /**< STAT_RDTXN Position */ 108 #define MXC_F_HPB_REVA_STAT_RDTXN ((uint32_t)(0x1UL << MXC_F_HPB_REVA_STAT_RDTXN_POS)) /**< STAT_RDTXN Mask */ 109 110 #define MXC_F_HPB_REVA_STAT_RDADDRERR_POS 8 /**< STAT_RDADDRERR Position */ 111 #define MXC_F_HPB_REVA_STAT_RDADDRERR ((uint32_t)(0x1UL << MXC_F_HPB_REVA_STAT_RDADDRERR_POS)) /**< STAT_RDADDRERR Mask */ 112 113 #define MXC_F_HPB_REVA_STAT_RDSLVST_POS 9 /**< STAT_RDSLVST Position */ 114 #define MXC_F_HPB_REVA_STAT_RDSLVST ((uint32_t)(0x1UL << MXC_F_HPB_REVA_STAT_RDSLVST_POS)) /**< STAT_RDSLVST Mask */ 115 116 #define MXC_F_HPB_REVA_STAT_RDRSTERR_POS 10 /**< STAT_RDRSTERR Position */ 117 #define MXC_F_HPB_REVA_STAT_RDRSTERR ((uint32_t)(0x1UL << MXC_F_HPB_REVA_STAT_RDRSTERR_POS)) /**< STAT_RDRSTERR Mask */ 118 119 #define MXC_F_HPB_REVA_STAT_RDSTALL_POS 11 /**< STAT_RDSTALL Position */ 120 #define MXC_F_HPB_REVA_STAT_RDSTALL ((uint32_t)(0x1UL << MXC_F_HPB_REVA_STAT_RDSTALL_POS)) /**< STAT_RDSTALL Mask */ 121 122 #define MXC_F_HPB_REVA_STAT_WRTXN_POS 16 /**< STAT_WRTXN Position */ 123 #define MXC_F_HPB_REVA_STAT_WRTXN ((uint32_t)(0x1UL << MXC_F_HPB_REVA_STAT_WRTXN_POS)) /**< STAT_WRTXN Mask */ 124 125 #define MXC_F_HPB_REVA_STAT_WRADDRERR_POS 24 /**< STAT_WRADDRERR Position */ 126 #define MXC_F_HPB_REVA_STAT_WRADDRERR ((uint32_t)(0x1UL << MXC_F_HPB_REVA_STAT_WRADDRERR_POS)) /**< STAT_WRADDRERR Mask */ 127 128 #define MXC_F_HPB_REVA_STAT_WRRSTERR_POS 26 /**< STAT_WRRSTERR Position */ 129 #define MXC_F_HPB_REVA_STAT_WRRSTERR ((uint32_t)(0x1UL << MXC_F_HPB_REVA_STAT_WRRSTERR_POS)) /**< STAT_WRRSTERR Mask */ 130 131 /**@} end of group HPB_REVA_STAT_Register */ 132 133 /** 134 * @ingroup hpb_reva_registers 135 * @defgroup HPB_REVA_INTEN HPB_REVA_INTEN 136 * @brief HPB INTEN Register. 137 * @{ 138 */ 139 #define MXC_F_HPB_REVA_INTEN_MEM_POS 0 /**< INTEN_MEM Position */ 140 #define MXC_F_HPB_REVA_INTEN_MEM ((uint32_t)(0x1UL << MXC_F_HPB_REVA_INTEN_MEM_POS)) /**< INTEN_MEM Mask */ 141 142 #define MXC_F_HPB_REVA_INTEN_ERR_POS 1 /**< INTEN_ERR Position */ 143 #define MXC_F_HPB_REVA_INTEN_ERR ((uint32_t)(0x1UL << MXC_F_HPB_REVA_INTEN_ERR_POS)) /**< INTEN_ERR Mask */ 144 145 /**@} end of group HPB_REVA_INTEN_Register */ 146 147 /** 148 * @ingroup hpb_reva_registers 149 * @defgroup HPB_REVA_INTFL HPB_REVA_INTFL 150 * @brief HPB INTFL Register. 151 * @{ 152 */ 153 #define MXC_F_HPB_REVA_INTFL_MEM_POS 0 /**< INTFL_MEM Position */ 154 #define MXC_F_HPB_REVA_INTFL_MEM ((uint32_t)(0x1UL << MXC_F_HPB_REVA_INTFL_MEM_POS)) /**< INTFL_MEM Mask */ 155 156 #define MXC_F_HPB_REVA_INTFL_ERR_POS 1 /**< INTFL_ERR Position */ 157 #define MXC_F_HPB_REVA_INTFL_ERR ((uint32_t)(0x1UL << MXC_F_HPB_REVA_INTFL_ERR_POS)) /**< INTFL_ERR Mask */ 158 159 /**@} end of group HPB_REVA_INTFL_Register */ 160 161 /** 162 * @ingroup hpb_reva_registers 163 * @defgroup HPB_REVA_MEMBADDR HPB_REVA_MEMBADDR 164 * @brief Memory Base Address register. This is the base address of the addressable memory 165 * region in this microcontroller’s RAM. Because the addressable memory is mapped 166 * in 16M boundaries, the lower 24 bits are fixed to 0. 167 * @{ 168 */ 169 #define MXC_F_HPB_REVA_MEMBADDR_ADDR_POS 0 /**< MEMBADDR_ADDR Position */ 170 #define MXC_F_HPB_REVA_MEMBADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_HPB_REVA_MEMBADDR_ADDR_POS)) /**< MEMBADDR_ADDR Mask */ 171 172 /**@} end of group HPB_REVA_MEMBADDR_Register */ 173 174 /** 175 * @ingroup hpb_reva_registers 176 * @defgroup HPB_REVA_MEMCTRL HPB_REVA_MEMCTRL 177 * @brief Memory Control Register. 178 * @{ 179 */ 180 #define MXC_F_HPB_REVA_MEMCTRL_WRAPSIZE_POS 0 /**< MEMCTRL_WRAPSIZE Position */ 181 #define MXC_F_HPB_REVA_MEMCTRL_WRAPSIZE ((uint32_t)(0x3UL << MXC_F_HPB_REVA_MEMCTRL_WRAPSIZE_POS)) /**< MEMCTRL_WRAPSIZE Mask */ 182 #define MXC_V_HPB_REVA_MEMCTRL_WRAPSIZE_64B ((uint32_t)0x1UL) /**< MEMCTRL_WRAPSIZE_64B Value */ 183 #define MXC_S_HPB_REVA_MEMCTRL_WRAPSIZE_64B (MXC_V_HPB_REVA_MEMCTRL_WRAPSIZE_64B << MXC_F_HPB_REVA_MEMCTRL_WRAPSIZE_POS) /**< MEMCTRL_WRAPSIZE_64B Setting */ 184 #define MXC_V_HPB_REVA_MEMCTRL_WRAPSIZE_16B ((uint32_t)0x2UL) /**< MEMCTRL_WRAPSIZE_16B Value */ 185 #define MXC_S_HPB_REVA_MEMCTRL_WRAPSIZE_16B (MXC_V_HPB_REVA_MEMCTRL_WRAPSIZE_16B << MXC_F_HPB_REVA_MEMCTRL_WRAPSIZE_POS) /**< MEMCTRL_WRAPSIZE_16B Setting */ 186 #define MXC_V_HPB_REVA_MEMCTRL_WRAPSIZE_32B ((uint32_t)0x3UL) /**< MEMCTRL_WRAPSIZE_32B Value */ 187 #define MXC_S_HPB_REVA_MEMCTRL_WRAPSIZE_32B (MXC_V_HPB_REVA_MEMCTRL_WRAPSIZE_32B << MXC_F_HPB_REVA_MEMCTRL_WRAPSIZE_POS) /**< MEMCTRL_WRAPSIZE_32B Setting */ 188 189 #define MXC_F_HPB_REVA_MEMCTRL_DEVTYPE_POS 3 /**< MEMCTRL_DEVTYPE Position */ 190 #define MXC_F_HPB_REVA_MEMCTRL_DEVTYPE ((uint32_t)(0x3UL << MXC_F_HPB_REVA_MEMCTRL_DEVTYPE_POS)) /**< MEMCTRL_DEVTYPE Mask */ 191 #define MXC_V_HPB_REVA_MEMCTRL_DEVTYPE_HYPERFLASH ((uint32_t)0x0UL) /**< MEMCTRL_DEVTYPE_HYPERFLASH Value */ 192 #define MXC_S_HPB_REVA_MEMCTRL_DEVTYPE_HYPERFLASH (MXC_V_HPB_REVA_MEMCTRL_DEVTYPE_HYPERFLASH << MXC_F_HPB_REVA_MEMCTRL_DEVTYPE_POS) /**< MEMCTRL_DEVTYPE_HYPERFLASH Setting */ 193 #define MXC_V_HPB_REVA_MEMCTRL_DEVTYPE_XCCELA_PSRAM ((uint32_t)0x1UL) /**< MEMCTRL_DEVTYPE_XCCELA_PSRAM Value */ 194 #define MXC_S_HPB_REVA_MEMCTRL_DEVTYPE_XCCELA_PSRAM (MXC_V_HPB_REVA_MEMCTRL_DEVTYPE_XCCELA_PSRAM << MXC_F_HPB_REVA_MEMCTRL_DEVTYPE_POS) /**< MEMCTRL_DEVTYPE_XCCELA_PSRAM Setting */ 195 #define MXC_V_HPB_REVA_MEMCTRL_DEVTYPE_HYPERRAM ((uint32_t)0x2UL) /**< MEMCTRL_DEVTYPE_HYPERRAM Value */ 196 #define MXC_S_HPB_REVA_MEMCTRL_DEVTYPE_HYPERRAM (MXC_V_HPB_REVA_MEMCTRL_DEVTYPE_HYPERRAM << MXC_F_HPB_REVA_MEMCTRL_DEVTYPE_POS) /**< MEMCTRL_DEVTYPE_HYPERRAM Setting */ 197 198 #define MXC_F_HPB_REVA_MEMCTRL_CRT_POS 5 /**< MEMCTRL_CRT Position */ 199 #define MXC_F_HPB_REVA_MEMCTRL_CRT ((uint32_t)(0x1UL << MXC_F_HPB_REVA_MEMCTRL_CRT_POS)) /**< MEMCTRL_CRT Mask */ 200 201 #define MXC_F_HPB_REVA_MEMCTRL_RDLAT_EN_POS 6 /**< MEMCTRL_RDLAT_EN Position */ 202 #define MXC_F_HPB_REVA_MEMCTRL_RDLAT_EN ((uint32_t)(0x1UL << MXC_F_HPB_REVA_MEMCTRL_RDLAT_EN_POS)) /**< MEMCTRL_RDLAT_EN Mask */ 203 204 #define MXC_F_HPB_REVA_MEMCTRL_HSE_POS 7 /**< MEMCTRL_HSE Position */ 205 #define MXC_F_HPB_REVA_MEMCTRL_HSE ((uint32_t)(0x1UL << MXC_F_HPB_REVA_MEMCTRL_HSE_POS)) /**< MEMCTRL_HSE Mask */ 206 207 #define MXC_F_HPB_REVA_MEMCTRL_MAXLEN_POS 18 /**< MEMCTRL_MAXLEN Position */ 208 #define MXC_F_HPB_REVA_MEMCTRL_MAXLEN ((uint32_t)(0x1FFUL << MXC_F_HPB_REVA_MEMCTRL_MAXLEN_POS)) /**< MEMCTRL_MAXLEN Mask */ 209 210 #define MXC_F_HPB_REVA_MEMCTRL_MAX_EN_POS 31 /**< MEMCTRL_MAX_EN Position */ 211 #define MXC_F_HPB_REVA_MEMCTRL_MAX_EN ((uint32_t)(0x1UL << MXC_F_HPB_REVA_MEMCTRL_MAX_EN_POS)) /**< MEMCTRL_MAX_EN Mask */ 212 213 /**@} end of group HPB_REVA_MEMCTRL_Register */ 214 215 /** 216 * @ingroup hpb_reva_registers 217 * @defgroup HPB_REVA_MEMTIM HPB_REVA_MEMTIM 218 * @brief Memory timing register. 219 * @{ 220 */ 221 #define MXC_F_HPB_REVA_MEMTIM_LAT_POS 0 /**< MEMTIM_LAT Position */ 222 #define MXC_F_HPB_REVA_MEMTIM_LAT ((uint32_t)(0xFUL << MXC_F_HPB_REVA_MEMTIM_LAT_POS)) /**< MEMTIM_LAT Mask */ 223 #define MXC_V_HPB_REVA_MEMTIM_LAT_5CLK ((uint32_t)0x0UL) /**< MEMTIM_LAT_5CLK Value */ 224 #define MXC_S_HPB_REVA_MEMTIM_LAT_5CLK (MXC_V_HPB_REVA_MEMTIM_LAT_5CLK << MXC_F_HPB_REVA_MEMTIM_LAT_POS) /**< MEMTIM_LAT_5CLK Setting */ 225 #define MXC_V_HPB_REVA_MEMTIM_LAT_6CLK ((uint32_t)0x1UL) /**< MEMTIM_LAT_6CLK Value */ 226 #define MXC_S_HPB_REVA_MEMTIM_LAT_6CLK (MXC_V_HPB_REVA_MEMTIM_LAT_6CLK << MXC_F_HPB_REVA_MEMTIM_LAT_POS) /**< MEMTIM_LAT_6CLK Setting */ 227 #define MXC_V_HPB_REVA_MEMTIM_LAT_3CLK ((uint32_t)0xEUL) /**< MEMTIM_LAT_3CLK Value */ 228 #define MXC_S_HPB_REVA_MEMTIM_LAT_3CLK (MXC_V_HPB_REVA_MEMTIM_LAT_3CLK << MXC_F_HPB_REVA_MEMTIM_LAT_POS) /**< MEMTIM_LAT_3CLK Setting */ 229 #define MXC_V_HPB_REVA_MEMTIM_LAT_4CLK ((uint32_t)0xFUL) /**< MEMTIM_LAT_4CLK Value */ 230 #define MXC_S_HPB_REVA_MEMTIM_LAT_4CLK (MXC_V_HPB_REVA_MEMTIM_LAT_4CLK << MXC_F_HPB_REVA_MEMTIM_LAT_POS) /**< MEMTIM_LAT_4CLK Setting */ 231 232 #define MXC_F_HPB_REVA_MEMTIM_WRCSHD_POS 8 /**< MEMTIM_WRCSHD Position */ 233 #define MXC_F_HPB_REVA_MEMTIM_WRCSHD ((uint32_t)(0xFUL << MXC_F_HPB_REVA_MEMTIM_WRCSHD_POS)) /**< MEMTIM_WRCSHD Mask */ 234 235 #define MXC_F_HPB_REVA_MEMTIM_RDCSHD_POS 12 /**< MEMTIM_RDCSHD Position */ 236 #define MXC_F_HPB_REVA_MEMTIM_RDCSHD ((uint32_t)(0xFUL << MXC_F_HPB_REVA_MEMTIM_RDCSHD_POS)) /**< MEMTIM_RDCSHD Mask */ 237 238 #define MXC_F_HPB_REVA_MEMTIM_WRCSST_POS 16 /**< MEMTIM_WRCSST Position */ 239 #define MXC_F_HPB_REVA_MEMTIM_WRCSST ((uint32_t)(0xFUL << MXC_F_HPB_REVA_MEMTIM_WRCSST_POS)) /**< MEMTIM_WRCSST Mask */ 240 241 #define MXC_F_HPB_REVA_MEMTIM_RDCSST_POS 20 /**< MEMTIM_RDCSST Position */ 242 #define MXC_F_HPB_REVA_MEMTIM_RDCSST ((uint32_t)(0xFUL << MXC_F_HPB_REVA_MEMTIM_RDCSST_POS)) /**< MEMTIM_RDCSST Mask */ 243 244 #define MXC_F_HPB_REVA_MEMTIM_WRCSHI_POS 24 /**< MEMTIM_WRCSHI Position */ 245 #define MXC_F_HPB_REVA_MEMTIM_WRCSHI ((uint32_t)(0xFUL << MXC_F_HPB_REVA_MEMTIM_WRCSHI_POS)) /**< MEMTIM_WRCSHI Mask */ 246 247 #define MXC_F_HPB_REVA_MEMTIM_RDCSHI_POS 28 /**< MEMTIM_RDCSHI Position */ 248 #define MXC_F_HPB_REVA_MEMTIM_RDCSHI ((uint32_t)(0xFUL << MXC_F_HPB_REVA_MEMTIM_RDCSHI_POS)) /**< MEMTIM_RDCSHI Mask */ 249 250 /**@} end of group HPB_REVA_MEMTIM_Register */ 251 252 #ifdef __cplusplus 253 } 254 #endif 255 256 #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_HPB_HPB_REVA_REGS_H_ 257 258
