1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>GPIO0</name> 5 <description>Individual I/O for each GPIO</description> 6 <groupName>GPIO</groupName> 7 <baseAddress>0x40008000</baseAddress> 8 <addressBlock> 9 <offset>0x00</offset> 10 <size>0x1000</size> 11 <usage>registers</usage> 12 </addressBlock> 13 <interrupt> 14 <name>GPIO0</name> 15 <description>GPIO0 interrupt.</description> 16 <value>24</value> 17 </interrupt> 18 <registers> 19 <register> 20 <name>EN0</name> 21 <description>GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.</description> 22 <addressOffset>0x00</addressOffset> 23 <fields> 24 <field> 25 <name>GPIO_EN</name> 26 <description>Mask of all of the pins on the port.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 <enumeratedValues> 30 <enumeratedValue> 31 <name>ALTERNATE</name> 32 <description>Alternate function enabled.</description> 33 <value>0</value> 34 </enumeratedValue> 35 <enumeratedValue> 36 <name>GPIO</name> 37 <description>GPIO function is enabled.</description> 38 <value>1</value> 39 </enumeratedValue> 40 </enumeratedValues> 41 </field> 42 </fields> 43 </register> 44 <register> 45 <name>EN0_SET</name> 46 <description>GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.</description> 47 <addressOffset>0x04</addressOffset> 48 <fields> 49 <field> 50 <name>ALL</name> 51 <description>Mask of all of the pins on the port.</description> 52 <bitOffset>0</bitOffset> 53 <bitWidth>32</bitWidth> 54 </field> 55 </fields> 56 </register> 57 <register> 58 <name>EN0_CLR</name> 59 <description>GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.</description> 60 <addressOffset>0x08</addressOffset> 61 <fields> 62 <field> 63 <name>ALL</name> 64 <description>Mask of all of the pins on the port.</description> 65 <bitOffset>0</bitOffset> 66 <bitWidth>32</bitWidth> 67 </field> 68 </fields> 69 </register> 70 <register> 71 <name>OUTEN</name> 72 <description>GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.</description> 73 <addressOffset>0x0C</addressOffset> 74 <fields> 75 <field> 76 <name>EN</name> 77 <description>Mask of all of the pins on the port.</description> 78 <bitOffset>0</bitOffset> 79 <bitWidth>32</bitWidth> 80 <enumeratedValues> 81 <enumeratedValue> 82 <name>dis</name> 83 <description>GPIO Output Disable</description> 84 <value>0</value> 85 </enumeratedValue> 86 <enumeratedValue> 87 <name>en</name> 88 <description>GPIO Output Enable</description> 89 <value>1</value> 90 </enumeratedValue> 91 </enumeratedValues> 92 </field> 93 </fields> 94 </register> 95 <register> 96 <name>OUTEN_SET</name> 97 <description>GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.</description> 98 <addressOffset>0x10</addressOffset> 99 <fields> 100 <field> 101 <name>ALL</name> 102 <description>Mask of all of the pins on the port.</description> 103 <bitOffset>0</bitOffset> 104 <bitWidth>32</bitWidth> 105 </field> 106 </fields> 107 </register> 108 <register> 109 <name>OUTEN_CLR</name> 110 <description>GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.</description> 111 <addressOffset>0x14</addressOffset> 112 <fields> 113 <field> 114 <name>ALL</name> 115 <description>Mask of all of the pins on the port.</description> 116 <bitOffset>0</bitOffset> 117 <bitWidth>32</bitWidth> 118 </field> 119 </fields> 120 </register> 121 <register> 122 <name>OUT</name> 123 <description>GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.</description> 124 <addressOffset>0x18</addressOffset> 125 <fields> 126 <field> 127 <name>GPIO_OUT</name> 128 <description>Mask of all of the pins on the port.</description> 129 <bitOffset>0</bitOffset> 130 <bitWidth>32</bitWidth> 131 <enumeratedValues> 132 <enumeratedValue> 133 <name>low</name> 134 <description>Drive Logic 0 (low) on GPIO output.</description> 135 <value>0</value> 136 </enumeratedValue> 137 <enumeratedValue> 138 <name>high</name> 139 <description>Drive logic 1 (high) on GPIO output.</description> 140 <value>1</value> 141 </enumeratedValue> 142 </enumeratedValues> 143 </field> 144 </fields> 145 </register> 146 <register> 147 <name>OUT_SET</name> 148 <description>GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.</description> 149 <addressOffset>0x1C</addressOffset> 150 <access>write-only</access> 151 <fields> 152 <field> 153 <name>GPIO_OUT_SET</name> 154 <description>Mask of all of the pins on the port.</description> 155 <bitOffset>0</bitOffset> 156 <bitWidth>32</bitWidth> 157 <enumeratedValues> 158 <enumeratedValue> 159 <name>no</name> 160 <description>No Effect.</description> 161 <value>0</value> 162 </enumeratedValue> 163 <enumeratedValue> 164 <name>set</name> 165 <description>Set GPIO_OUT bit in this position to '1'</description> 166 <value>1</value> 167 </enumeratedValue> 168 </enumeratedValues> 169 </field> 170 </fields> 171 </register> 172 <register> 173 <name>OUT_CLR</name> 174 <description>GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.</description> 175 <addressOffset>0x20</addressOffset> 176 <access>write-only</access> 177 <fields> 178 <field> 179 <name>GPIO_OUT_CLR</name> 180 <description>Mask of all of the pins on the port.</description> 181 <bitOffset>0</bitOffset> 182 <bitWidth>32</bitWidth> 183 </field> 184 </fields> 185 </register> 186 <register> 187 <name>IN</name> 188 <description>GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.</description> 189 <addressOffset>0x24</addressOffset> 190 <access>read-only</access> 191 <fields> 192 <field> 193 <name>GPIO_IN</name> 194 <description>Mask of all of the pins on the port.</description> 195 <bitOffset>0</bitOffset> 196 <bitWidth>32</bitWidth> 197 </field> 198 </fields> 199 </register> 200 <register> 201 <name>INTMODE</name> 202 <description>GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.</description> 203 <addressOffset>0x28</addressOffset> 204 <fields> 205 <field> 206 <name>GPIO_INTMODE</name> 207 <description>Mask of all of the pins on the port.</description> 208 <bitOffset>0</bitOffset> 209 <bitWidth>32</bitWidth> 210 <enumeratedValues> 211 <enumeratedValue> 212 <name>level</name> 213 <description>Interrupts for this pin are level triggered.</description> 214 <value>0</value> 215 </enumeratedValue> 216 <enumeratedValue> 217 <name>edge</name> 218 <description>Interrupts for this pin are edge triggered.</description> 219 <value>1</value> 220 </enumeratedValue> 221 </enumeratedValues> 222 </field> 223 </fields> 224 </register> 225 <register> 226 <name>INTPOL</name> 227 <description>GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.</description> 228 <addressOffset>0x2C</addressOffset> 229 <fields> 230 <field> 231 <name>GPIO_INTPOL</name> 232 <description>Mask of all of the pins on the port.</description> 233 <bitOffset>0</bitOffset> 234 <bitWidth>32</bitWidth> 235 <enumeratedValues> 236 <enumeratedValue> 237 <name>falling</name> 238 <description>Interrupts are latched on a falling edge or low level condition for this pin.</description> 239 <value>0</value> 240 </enumeratedValue> 241 <enumeratedValue> 242 <name>rising</name> 243 <description>Interrupts are latched on a rising edge or high condition for this pin.</description> 244 <value>1</value> 245 </enumeratedValue> 246 </enumeratedValues> 247 </field> 248 </fields> 249 </register> 250 <register> 251 <name>INEN</name> 252 <description>GPIO Input Enable</description> 253 <addressOffset>0x30</addressOffset> 254 </register> 255 <register> 256 <name>INTEN</name> 257 <description>GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.</description> 258 <addressOffset>0x34</addressOffset> 259 <fields> 260 <field> 261 <name>GPIO_INTEN</name> 262 <description>Mask of all of the pins on the port.</description> 263 <bitOffset>0</bitOffset> 264 <bitWidth>32</bitWidth> 265 <enumeratedValues> 266 <enumeratedValue> 267 <name>dis</name> 268 <description>Interrupts are disabled for this GPIO pin.</description> 269 <value>0</value> 270 </enumeratedValue> 271 <enumeratedValue> 272 <name>en</name> 273 <description>Interrupts are enabled for this GPIO pin.</description> 274 <value>1</value> 275 </enumeratedValue> 276 </enumeratedValues> 277 </field> 278 </fields> 279 </register> 280 <register> 281 <name>INTEN_SET</name> 282 <description>GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.</description> 283 <addressOffset>0x38</addressOffset> 284 <fields> 285 <field> 286 <name>GPIO_INTEN_SET</name> 287 <description>Mask of all of the pins on the port.</description> 288 <bitOffset>0</bitOffset> 289 <bitWidth>32</bitWidth> 290 <enumeratedValues> 291 <enumeratedValue> 292 <name>no</name> 293 <description>No effect.</description> 294 <value>0</value> 295 </enumeratedValue> 296 <enumeratedValue> 297 <name>set</name> 298 <description>Set GPIO_INT_EN bit in this position to '1'</description> 299 <value>1</value> 300 </enumeratedValue> 301 </enumeratedValues> 302 </field> 303 </fields> 304 </register> 305 <register> 306 <name>INTEN_CLR</name> 307 <description>GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.</description> 308 <addressOffset>0x3C</addressOffset> 309 <fields> 310 <field> 311 <name>GPIO_INTEN_CLR</name> 312 <description>Mask of all of the pins on the port.</description> 313 <bitOffset>0</bitOffset> 314 <bitWidth>32</bitWidth> 315 <enumeratedValues> 316 <enumeratedValue> 317 <name>no</name> 318 <description>No Effect.</description> 319 <value>0</value> 320 </enumeratedValue> 321 <enumeratedValue> 322 <name>clear</name> 323 <description>Clear GPIO_INT_EN bit in this position to '0'</description> 324 <value>1</value> 325 </enumeratedValue> 326 </enumeratedValues> 327 </field> 328 </fields> 329 </register> 330 <register> 331 <name>INTFL</name> 332 <description>GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.</description> 333 <addressOffset>0x40</addressOffset> 334 <access>read-only</access> 335 <fields> 336 <field> 337 <name>GPIO_INTFL</name> 338 <description>Mask of all of the pins on the port.</description> 339 <bitOffset>0</bitOffset> 340 <bitWidth>32</bitWidth> 341 <enumeratedValues> 342 <enumeratedValue> 343 <name>no</name> 344 <description>No Interrupt is pending on this GPIO pin.</description> 345 <value>0</value> 346 </enumeratedValue> 347 <enumeratedValue> 348 <name>pending</name> 349 <description>An Interrupt is pending on this GPIO pin.</description> 350 <value>1</value> 351 </enumeratedValue> 352 </enumeratedValues> 353 </field> 354 </fields> 355 </register> 356 <register> 357 <name>INTFL_CLR</name> 358 <description>GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.</description> 359 <addressOffset>0x48</addressOffset> 360 <fields> 361 <field> 362 <name>ALL</name> 363 <description>Mask of all of the pins on the port.</description> 364 <bitOffset>0</bitOffset> 365 <bitWidth>32</bitWidth> 366 </field> 367 </fields> 368 </register> 369 <register> 370 <name>WKEN</name> 371 <description>GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.</description> 372 <addressOffset>0x4C</addressOffset> 373 <fields> 374 <field> 375 <name>GPIO_WKEN</name> 376 <description>Mask of all of the pins on the port.</description> 377 <bitOffset>0</bitOffset> 378 <bitWidth>32</bitWidth> 379 <enumeratedValues> 380 <enumeratedValue> 381 <name>dis</name> 382 <description>PMU wakeup for this GPIO is disabled.</description> 383 <value>0</value> 384 </enumeratedValue> 385 <enumeratedValue> 386 <name>en</name> 387 <description>PMU wakeup for this GPIO is enabled.</description> 388 <value>1</value> 389 </enumeratedValue> 390 </enumeratedValues> 391 </field> 392 </fields> 393 </register> 394 <register> 395 <name>WKEN_SET</name> 396 <description>GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.</description> 397 <addressOffset>0x50</addressOffset> 398 <fields> 399 <field> 400 <name>ALL</name> 401 <description>Mask of all of the pins on the port.</description> 402 <bitOffset>0</bitOffset> 403 <bitWidth>32</bitWidth> 404 </field> 405 </fields> 406 </register> 407 <register> 408 <name>WKEN_CLR</name> 409 <description>GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.</description> 410 <addressOffset>0x54</addressOffset> 411 <fields> 412 <field> 413 <name>ALL</name> 414 <description>Mask of all of the pins on the port.</description> 415 <bitOffset>0</bitOffset> 416 <bitWidth>32</bitWidth> 417 </field> 418 </fields> 419 </register> 420 <register> 421 <name>DUALEDGE</name> 422 <description>GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.</description> 423 <addressOffset>0x5C</addressOffset> 424 <fields> 425 <field> 426 <name>GPIO_DUALEDGE</name> 427 <description>Mask of all of the pins on the port.</description> 428 <bitOffset>0</bitOffset> 429 <bitWidth>32</bitWidth> 430 <enumeratedValues> 431 <enumeratedValue> 432 <name>no</name> 433 <description>No Effect.</description> 434 <value>0</value> 435 </enumeratedValue> 436 <enumeratedValue> 437 <name>en</name> 438 <description>Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.</description> 439 <value>1</value> 440 </enumeratedValue> 441 </enumeratedValues> 442 </field> 443 </fields> 444 </register> 445 <register> 446 <name>PADCTRL0</name> 447 <description>GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 448 <addressOffset>0x60</addressOffset> 449 <fields> 450 <field> 451 <name>GPIO_PADCTRL0</name> 452 <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 453 <bitOffset>0</bitOffset> 454 <bitWidth>32</bitWidth> 455 <enumeratedValues> 456 <enumeratedValue> 457 <name>impedance</name> 458 <description>High Impedance.</description> 459 <value>0</value> 460 </enumeratedValue> 461 <enumeratedValue> 462 <name>pu</name> 463 <description>Weak pull-up mode.</description> 464 <value>1</value> 465 </enumeratedValue> 466 <enumeratedValue> 467 <name>pd</name> 468 <description>weak pull-down mode.</description> 469 <value>2</value> 470 </enumeratedValue> 471 </enumeratedValues> 472 </field> 473 </fields> 474 </register> 475 <register> 476 <name>PADCTRL1</name> 477 <description>GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 478 <addressOffset>0x64</addressOffset> 479 <fields> 480 <field> 481 <name>GPIO_PADCTRL1</name> 482 <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 483 <bitOffset>0</bitOffset> 484 <bitWidth>32</bitWidth> 485 <enumeratedValues> 486 <enumeratedValue> 487 <name>impedance</name> 488 <description>High Impedance.</description> 489 <value>0</value> 490 </enumeratedValue> 491 <enumeratedValue> 492 <name>pu</name> 493 <description>Weak pull-up mode.</description> 494 <value>1</value> 495 </enumeratedValue> 496 <enumeratedValue> 497 <name>pd</name> 498 <description>weak pull-down mode.</description> 499 <value>2</value> 500 </enumeratedValue> 501 </enumeratedValues> 502 </field> 503 </fields> 504 </register> 505 <register> 506 <name>EN1</name> 507 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 508 <addressOffset>0x68</addressOffset> 509 <fields> 510 <field> 511 <name>GPIO_EN1</name> 512 <description>Mask of all of the pins on the port.</description> 513 <bitOffset>0</bitOffset> 514 <bitWidth>32</bitWidth> 515 <enumeratedValues> 516 <enumeratedValue> 517 <name>primary</name> 518 <description>Primary function selected.</description> 519 <value>0</value> 520 </enumeratedValue> 521 <enumeratedValue> 522 <name>secondary</name> 523 <description>Secondary function selected.</description> 524 <value>1</value> 525 </enumeratedValue> 526 </enumeratedValues> 527 </field> 528 </fields> 529 </register> 530 <register> 531 <name>EN1_SET</name> 532 <description>GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.</description> 533 <addressOffset>0x6C</addressOffset> 534 <fields> 535 <field> 536 <name>ALL</name> 537 <description>Mask of all of the pins on the port.</description> 538 <bitOffset>0</bitOffset> 539 <bitWidth>32</bitWidth> 540 </field> 541 </fields> 542 </register> 543 <register> 544 <name>EN1_CLR</name> 545 <description>GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.</description> 546 <addressOffset>0x70</addressOffset> 547 <fields> 548 <field> 549 <name>ALL</name> 550 <description>Mask of all of the pins on the port.</description> 551 <bitOffset>0</bitOffset> 552 <bitWidth>32</bitWidth> 553 </field> 554 </fields> 555 </register> 556 <register> 557 <name>EN2</name> 558 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 559 <addressOffset>0x74</addressOffset> 560 <fields> 561 <field> 562 <name>GPIO_EN2</name> 563 <description>Mask of all of the pins on the port.</description> 564 <bitOffset>0</bitOffset> 565 <bitWidth>32</bitWidth> 566 <enumeratedValues> 567 <enumeratedValue> 568 <name>primary</name> 569 <description>Primary function selected.</description> 570 <value>0</value> 571 </enumeratedValue> 572 <enumeratedValue> 573 <name>secondary</name> 574 <description>Secondary function selected.</description> 575 <value>1</value> 576 </enumeratedValue> 577 </enumeratedValues> 578 </field> 579 </fields> 580 </register> 581 <register> 582 <name>EN2_SET</name> 583 <description>GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.</description> 584 <addressOffset>0x78</addressOffset> 585 <fields> 586 <field> 587 <name>ALL</name> 588 <description>Mask of all of the pins on the port.</description> 589 <bitOffset>0</bitOffset> 590 <bitWidth>32</bitWidth> 591 </field> 592 </fields> 593 </register> 594 <register> 595 <name>EN2_CLR</name> 596 <description>GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.</description> 597 <addressOffset>0x7C</addressOffset> 598 <fields> 599 <field> 600 <name>ALL</name> 601 <description>Mask of all of the pins on the port.</description> 602 <bitOffset>0</bitOffset> 603 <bitWidth>32</bitWidth> 604 </field> 605 </fields> 606 </register> 607 <register> 608 <name>HYSEN</name> 609 <description>GPIO Input Hysteresis Enable.</description> 610 <addressOffset>0xA8</addressOffset> 611 <fields> 612 <field> 613 <name>GPIO_HYSEN</name> 614 <description>Mask of all of the pins on the port.</description> 615 <bitOffset>0</bitOffset> 616 <bitWidth>32</bitWidth> 617 </field> 618 </fields> 619 </register> 620 <register> 621 <name>SRSEL</name> 622 <description>GPIO Slew Rate Enable Register.</description> 623 <addressOffset>0xAC</addressOffset> 624 <fields> 625 <field> 626 <name>GPIO_SRSEL</name> 627 <description>Mask of all of the pins on the port.</description> 628 <bitOffset>0</bitOffset> 629 <bitWidth>32</bitWidth> 630 <enumeratedValues> 631 <enumeratedValue> 632 <name>FAST</name> 633 <description>Fast Slew Rate selected.</description> 634 <value>0</value> 635 </enumeratedValue> 636 <enumeratedValue> 637 <name>SLOW</name> 638 <description>Slow Slew Rate selected.</description> 639 <value>1</value> 640 </enumeratedValue> 641 </enumeratedValues> 642 </field> 643 </fields> 644 </register> 645 <register> 646 <name>DS0</name> 647 <description>GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 648 <addressOffset>0xB0</addressOffset> 649 <fields> 650 <field> 651 <name>GPIO_DS0</name> 652 <description>Mask of all of the pins on the port.</description> 653 <bitOffset>0</bitOffset> 654 <bitWidth>32</bitWidth> 655 <enumeratedValues> 656 <enumeratedValue> 657 <name>ld</name> 658 <description>GPIO port pin is in low-drive mode.</description> 659 <value>0</value> 660 </enumeratedValue> 661 <enumeratedValue> 662 <name>hd</name> 663 <description>GPIO port pin is in high-drive mode.</description> 664 <value>1</value> 665 </enumeratedValue> 666 </enumeratedValues> 667 </field> 668 </fields> 669 </register> 670 <register> 671 <name>DS1</name> 672 <description>GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 673 <addressOffset>0xB4</addressOffset> 674 <fields> 675 <field> 676 <name>GPIO_DS1</name> 677 <description>Mask of all of the pins on the port.</description> 678 <bitOffset>0</bitOffset> 679 <bitWidth>32</bitWidth> 680 </field> 681 </fields> 682 </register> 683 <register> 684 <name>PS</name> 685 <description>GPIO Pull Select Mode.</description> 686 <addressOffset>0xB8</addressOffset> 687 <fields> 688 <field> 689 <name>ALL</name> 690 <description>Mask of all of the pins on the port.</description> 691 <bitOffset>0</bitOffset> 692 <bitWidth>32</bitWidth> 693 </field> 694 </fields> 695 </register> 696 </registers> 697 </peripheral> 698 <!-- GPIO0: Individual I/O for Port 0 --> 699</device>
