1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>GPIO0</name> 5 <description>Individual I/O for each GPIO</description> 6 <groupName>GPIO</groupName> 7 <baseAddress>0x40008000</baseAddress> 8 <addressBlock> 9 <offset>0x00</offset> 10 <size>0x1000</size> 11 <usage>registers</usage> 12 </addressBlock> 13 <interrupt> 14 <name>GPIO0</name> 15 <description>GPIO0 interrupt.</description> 16 <value>24</value> 17 </interrupt> 18 <registers> 19 <register> 20 <name>EN</name> 21 <description>GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.</description> 22 <addressOffset>0x00</addressOffset> 23 <fields> 24 <field> 25 <name>GPIO_EN</name> 26 <description>Mask of all of the pins on the port.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 <enumeratedValues> 30 <enumeratedValue> 31 <name>alternate</name> 32 <description>Alternate function enabled.</description> 33 <value>0</value> 34 </enumeratedValue> 35 <enumeratedValue> 36 <name>GPIO</name> 37 <description>GPIO function is enabled.</description> 38 <value>1</value> 39 </enumeratedValue> 40 </enumeratedValues> 41 </field> 42 </fields> 43 </register> 44 <register> 45 <name>EN_SET</name> 46 <description>GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.</description> 47 <addressOffset>0x04</addressOffset> 48 <fields> 49 <field> 50 <name>ALL</name> 51 <description>Mask of all of the pins on the port.</description> 52 <bitOffset>0</bitOffset> 53 <bitWidth>32</bitWidth> 54 </field> 55 </fields> 56 </register> 57 <register> 58 <name>EN_CLR</name> 59 <description>GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.</description> 60 <addressOffset>0x08</addressOffset> 61 <fields> 62 <field> 63 <name>ALL</name> 64 <description>Mask of all of the pins on the port.</description> 65 <bitOffset>0</bitOffset> 66 <bitWidth>32</bitWidth> 67 </field> 68 </fields> 69 </register> 70 <register> 71 <name>OUT_EN</name> 72 <description>GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.</description> 73 <addressOffset>0x0C</addressOffset> 74 <fields> 75 <field> 76 <name>GPIO_OUT_EN</name> 77 <description>Mask of all of the pins on the port.</description> 78 <bitOffset>0</bitOffset> 79 <bitWidth>32</bitWidth> 80 <enumeratedValues> 81 <enumeratedValue> 82 <name>dis</name> 83 <description>GPIO Output Disable</description> 84 <value>0</value> 85 </enumeratedValue> 86 <enumeratedValue> 87 <name>en</name> 88 <description>GPIO Output Enable</description> 89 <value>1</value> 90 </enumeratedValue> 91 </enumeratedValues> 92 </field> 93 </fields> 94 </register> 95 <register> 96 <name>OUT_EN_SET</name> 97 <description>GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.</description> 98 <addressOffset>0x10</addressOffset> 99 <fields> 100 <field> 101 <name>ALL</name> 102 <description>Mask of all of the pins on the port.</description> 103 <bitOffset>0</bitOffset> 104 <bitWidth>32</bitWidth> 105 </field> 106 </fields> 107 </register> 108 <register> 109 <name>OUT_EN_CLR</name> 110 <description>GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.</description> 111 <addressOffset>0x14</addressOffset> 112 <fields> 113 <field> 114 <name>ALL</name> 115 <description>Mask of all of the pins on the port.</description> 116 <bitOffset>0</bitOffset> 117 <bitWidth>32</bitWidth> 118 </field> 119 </fields> 120 </register> 121 <register> 122 <name>OUT</name> 123 <description>GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.</description> 124 <addressOffset>0x18</addressOffset> 125 <fields> 126 <field> 127 <name>GPIO_OUT</name> 128 <description>Mask of all of the pins on the port.</description> 129 <bitOffset>0</bitOffset> 130 <bitWidth>32</bitWidth> 131 <enumeratedValues> 132 <enumeratedValue> 133 <name>low</name> 134 <description>Drive Logic 0 (low) on GPIO output.</description> 135 <value>0</value> 136 </enumeratedValue> 137 <enumeratedValue> 138 <name>high</name> 139 <description>Drive logic 1 (high) on GPIO output.</description> 140 <value>1</value> 141 </enumeratedValue> 142 </enumeratedValues> 143 </field> 144 </fields> 145 </register> 146 <register> 147 <name>OUT_SET</name> 148 <description>GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.</description> 149 <addressOffset>0x1C</addressOffset> 150 <access>write-only</access> 151 <fields> 152 <field> 153 <name>GPIO_OUT_SET</name> 154 <description>Mask of all of the pins on the port.</description> 155 <bitOffset>0</bitOffset> 156 <bitWidth>32</bitWidth> 157 <enumeratedValues> 158 <enumeratedValue> 159 <name>no</name> 160 <description>No Effect.</description> 161 <value>0</value> 162 </enumeratedValue> 163 <enumeratedValue> 164 <name>set</name> 165 <description>Set GPIO_OUT bit in this position to '1'</description> 166 <value>1</value> 167 </enumeratedValue> 168 </enumeratedValues> 169 </field> 170 </fields> 171 </register> 172 <register> 173 <name>OUT_CLR</name> 174 <description>GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.</description> 175 <addressOffset>0x20</addressOffset> 176 <access>write-only</access> 177 <fields> 178 <field> 179 <name>GPIO_OUT_CLR</name> 180 <description>Mask of all of the pins on the port.</description> 181 <bitOffset>0</bitOffset> 182 <bitWidth>32</bitWidth> 183 </field> 184 </fields> 185 </register> 186 <register> 187 <name>IN</name> 188 <description>GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.</description> 189 <addressOffset>0x24</addressOffset> 190 <access>read-only</access> 191 <fields> 192 <field> 193 <name>GPIO_IN</name> 194 <description>Mask of all of the pins on the port.</description> 195 <bitOffset>0</bitOffset> 196 <bitWidth>32</bitWidth> 197 </field> 198 </fields> 199 </register> 200 <register> 201 <name>INT_MOD</name> 202 <description>GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.</description> 203 <addressOffset>0x28</addressOffset> 204 <fields> 205 <field> 206 <name>GPIO_INT_MOD</name> 207 <description>Mask of all of the pins on the port.</description> 208 <bitOffset>0</bitOffset> 209 <bitWidth>32</bitWidth> 210 <enumeratedValues> 211 <enumeratedValue> 212 <name>level</name> 213 <description>Interrupts for this pin are level triggered.</description> 214 <value>0</value> 215 </enumeratedValue> 216 <enumeratedValue> 217 <name>edge</name> 218 <description>Interrupts for this pin are edge triggered.</description> 219 <value>1</value> 220 </enumeratedValue> 221 </enumeratedValues> 222 </field> 223 </fields> 224 </register> 225 <register> 226 <name>INT_POL</name> 227 <description>GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.</description> 228 <addressOffset>0x2C</addressOffset> 229 <fields> 230 <field> 231 <name>GPIO_INT_POL</name> 232 <description>Mask of all of the pins on the port.</description> 233 <bitOffset>0</bitOffset> 234 <bitWidth>32</bitWidth> 235 <enumeratedValues> 236 <enumeratedValue> 237 <name>falling</name> 238 <description>Interrupts are latched on a falling edge or low level condition for this pin.</description> 239 <value>0</value> 240 </enumeratedValue> 241 <enumeratedValue> 242 <name>rising</name> 243 <description>Interrupts are latched on a rising edge or high condition for this pin.</description> 244 <value>1</value> 245 </enumeratedValue> 246 </enumeratedValues> 247 </field> 248 </fields> 249 </register> 250 <register> 251 <name>IN_EN</name> 252 <description>GPIO Port Input Enable.</description> 253 <addressOffset>0x30</addressOffset> 254 <fields> 255 <field> 256 <name>GPIO_IN_EN</name> 257 <description>Mask of all of the pins on the port.</description> 258 <bitOffset>0</bitOffset> 259 <bitWidth>32</bitWidth> 260 <enumeratedValues> 261 <enumeratedValue> 262 <name>dis</name> 263 <description>GPIO Input Disable</description> 264 <value>0</value> 265 </enumeratedValue> 266 <enumeratedValue> 267 <name>en</name> 268 <description>GPIO Input Enable</description> 269 <value>1</value> 270 </enumeratedValue> 271 </enumeratedValues> 272 </field> 273 </fields> 274 </register> 275 <register> 276 <name>INT_EN</name> 277 <description>GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.</description> 278 <addressOffset>0x34</addressOffset> 279 <fields> 280 <field> 281 <name>GPIO_INT_EN</name> 282 <description>Mask of all of the pins on the port.</description> 283 <bitOffset>0</bitOffset> 284 <bitWidth>32</bitWidth> 285 <enumeratedValues> 286 <enumeratedValue> 287 <name>dis</name> 288 <description>Interrupts are disabled for this GPIO pin.</description> 289 <value>0</value> 290 </enumeratedValue> 291 <enumeratedValue> 292 <name>en</name> 293 <description>Interrupts are enabled for this GPIO pin.</description> 294 <value>1</value> 295 </enumeratedValue> 296 </enumeratedValues> 297 </field> 298 </fields> 299 </register> 300 <register> 301 <name>INT_EN_SET</name> 302 <description>GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.</description> 303 <addressOffset>0x38</addressOffset> 304 <fields> 305 <field> 306 <name>GPIO_INT_EN_SET</name> 307 <description>Mask of all of the pins on the port.</description> 308 <bitOffset>0</bitOffset> 309 <bitWidth>32</bitWidth> 310 <enumeratedValues> 311 <enumeratedValue> 312 <name>no</name> 313 <description>No effect.</description> 314 <value>0</value> 315 </enumeratedValue> 316 <enumeratedValue> 317 <name>set</name> 318 <description>Set GPIO_INT_EN bit in this position to '1'</description> 319 <value>1</value> 320 </enumeratedValue> 321 </enumeratedValues> 322 </field> 323 </fields> 324 </register> 325 <register> 326 <name>INT_EN_CLR</name> 327 <description>GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.</description> 328 <addressOffset>0x3C</addressOffset> 329 <fields> 330 <field> 331 <name>GPIO_INT_EN_CLR</name> 332 <description>Mask of all of the pins on the port.</description> 333 <bitOffset>0</bitOffset> 334 <bitWidth>32</bitWidth> 335 <enumeratedValues> 336 <enumeratedValue> 337 <name>no</name> 338 <description>No Effect.</description> 339 <value>0</value> 340 </enumeratedValue> 341 <enumeratedValue> 342 <name>clear</name> 343 <description>Clear GPIO_INT_EN bit in this position to '0'</description> 344 <value>1</value> 345 </enumeratedValue> 346 </enumeratedValues> 347 </field> 348 </fields> 349 </register> 350 <register> 351 <name>INT_STAT</name> 352 <description>GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.</description> 353 <addressOffset>0x40</addressOffset> 354 <access>read-only</access> 355 <fields> 356 <field> 357 <name>GPIO_INT_STAT</name> 358 <description>Mask of all of the pins on the port.</description> 359 <bitOffset>0</bitOffset> 360 <bitWidth>32</bitWidth> 361 <enumeratedValues> 362 <enumeratedValue> 363 <name>no</name> 364 <description>No Interrupt is pending on this GPIO pin.</description> 365 <value>0</value> 366 </enumeratedValue> 367 <enumeratedValue> 368 <name>pending</name> 369 <description>An Interrupt is pending on this GPIO pin.</description> 370 <value>1</value> 371 </enumeratedValue> 372 </enumeratedValues> 373 </field> 374 </fields> 375 </register> 376 <register> 377 <name>INT_CLR</name> 378 <description>GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.</description> 379 <addressOffset>0x48</addressOffset> 380 <fields> 381 <field> 382 <name>ALL</name> 383 <description>Mask of all of the pins on the port.</description> 384 <bitOffset>0</bitOffset> 385 <bitWidth>32</bitWidth> 386 </field> 387 </fields> 388 </register> 389 <register> 390 <name>WAKE_EN</name> 391 <description>GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.</description> 392 <addressOffset>0x4C</addressOffset> 393 <fields> 394 <field> 395 <name>GPIO_WAKE_EN</name> 396 <description>Mask of all of the pins on the port.</description> 397 <bitOffset>0</bitOffset> 398 <bitWidth>32</bitWidth> 399 <enumeratedValues> 400 <enumeratedValue> 401 <name>dis</name> 402 <description>PMU wakeup for this GPIO is disabled.</description> 403 <value>0</value> 404 </enumeratedValue> 405 <enumeratedValue> 406 <name>en</name> 407 <description>PMU wakeup for this GPIO is enabled.</description> 408 <value>1</value> 409 </enumeratedValue> 410 </enumeratedValues> 411 </field> 412 </fields> 413 </register> 414 <register> 415 <name>WAKE_EN_SET</name> 416 <description>GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.</description> 417 <addressOffset>0x50</addressOffset> 418 <fields> 419 <field> 420 <name>ALL</name> 421 <description>Mask of all of the pins on the port.</description> 422 <bitOffset>0</bitOffset> 423 <bitWidth>32</bitWidth> 424 </field> 425 </fields> 426 </register> 427 <register> 428 <name>WAKE_EN_CLR</name> 429 <description>GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.</description> 430 <addressOffset>0x54</addressOffset> 431 <fields> 432 <field> 433 <name>ALL</name> 434 <description>Mask of all of the pins on the port.</description> 435 <bitOffset>0</bitOffset> 436 <bitWidth>32</bitWidth> 437 </field> 438 </fields> 439 </register> 440 <register> 441 <name>INT_DUAL_EDGE</name> 442 <description>GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.</description> 443 <addressOffset>0x5C</addressOffset> 444 <fields> 445 <field> 446 <name>GPIO_INT_DUAL_EDGE</name> 447 <description>Mask of all of the pins on the port.</description> 448 <bitOffset>0</bitOffset> 449 <bitWidth>32</bitWidth> 450 <enumeratedValues> 451 <enumeratedValue> 452 <name>no</name> 453 <description>No Effect.</description> 454 <value>0</value> 455 </enumeratedValue> 456 <enumeratedValue> 457 <name>en</name> 458 <description>Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.</description> 459 <value>1</value> 460 </enumeratedValue> 461 </enumeratedValues> 462 </field> 463 </fields> 464 </register> 465 <register> 466 <name>PAD_CFG1</name> 467 <description>GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 468 <addressOffset>0x60</addressOffset> 469 <fields> 470 <field> 471 <name>GPIO_PAD_CFG1</name> 472 <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 473 <bitOffset>0</bitOffset> 474 <bitWidth>32</bitWidth> 475 <enumeratedValues> 476 <enumeratedValue> 477 <name>impedance</name> 478 <description>High Impedance.</description> 479 <value>0</value> 480 </enumeratedValue> 481 <enumeratedValue> 482 <name>pu</name> 483 <description>Weak pull-up mode.</description> 484 <value>1</value> 485 </enumeratedValue> 486 <enumeratedValue> 487 <name>pd</name> 488 <description>weak pull-down mode.</description> 489 <value>2</value> 490 </enumeratedValue> 491 </enumeratedValues> 492 </field> 493 </fields> 494 </register> 495 <register> 496 <name>PAD_CFG2</name> 497 <description>GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 498 <addressOffset>0x64</addressOffset> 499 <fields> 500 <field> 501 <name>GPIO_PAD_CFG2</name> 502 <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 503 <bitOffset>0</bitOffset> 504 <bitWidth>32</bitWidth> 505 <enumeratedValues> 506 <enumeratedValue> 507 <name>impedance</name> 508 <description>High Impedance.</description> 509 <value>0</value> 510 </enumeratedValue> 511 <enumeratedValue> 512 <name>pu</name> 513 <description>Weak pull-up mode.</description> 514 <value>1</value> 515 </enumeratedValue> 516 <enumeratedValue> 517 <name>pd</name> 518 <description>weak pull-down mode.</description> 519 <value>2</value> 520 </enumeratedValue> 521 </enumeratedValues> 522 </field> 523 </fields> 524 </register> 525 <register> 526 <name>EN1</name> 527 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 528 <addressOffset>0x68</addressOffset> 529 <fields> 530 <field> 531 <name>GPIO_EN1</name> 532 <description>Mask of all of the pins on the port.</description> 533 <bitOffset>0</bitOffset> 534 <bitWidth>32</bitWidth> 535 <enumeratedValues> 536 <enumeratedValue> 537 <name>primary</name> 538 <description>Primary function selected.</description> 539 <value>0</value> 540 </enumeratedValue> 541 <enumeratedValue> 542 <name>secondary</name> 543 <description>Secondary function selected.</description> 544 <value>1</value> 545 </enumeratedValue> 546 </enumeratedValues> 547 </field> 548 </fields> 549 </register> 550 <register> 551 <name>EN1_SET</name> 552 <description>GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.</description> 553 <addressOffset>0x6C</addressOffset> 554 <fields> 555 <field> 556 <name>ALL</name> 557 <description>Mask of all of the pins on the port.</description> 558 <bitOffset>0</bitOffset> 559 <bitWidth>32</bitWidth> 560 </field> 561 </fields> 562 </register> 563 <register> 564 <name>EN1_CLR</name> 565 <description>GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.</description> 566 <addressOffset>0x70</addressOffset> 567 <fields> 568 <field> 569 <name>ALL</name> 570 <description>Mask of all of the pins on the port.</description> 571 <bitOffset>0</bitOffset> 572 <bitWidth>32</bitWidth> 573 </field> 574 </fields> 575 </register> 576 <register> 577 <name>EN2</name> 578 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 579 <addressOffset>0x74</addressOffset> 580 <fields> 581 <field> 582 <name>GPIO_EN2</name> 583 <description>Mask of all of the pins on the port.</description> 584 <bitOffset>0</bitOffset> 585 <bitWidth>32</bitWidth> 586 <enumeratedValues> 587 <enumeratedValue> 588 <name>primary</name> 589 <description>Primary function selected.</description> 590 <value>0</value> 591 </enumeratedValue> 592 <enumeratedValue> 593 <name>secondary</name> 594 <description>Secondary function selected.</description> 595 <value>1</value> 596 </enumeratedValue> 597 </enumeratedValues> 598 </field> 599 </fields> 600 </register> 601 <register> 602 <name>EN2_SET</name> 603 <description>GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.</description> 604 <addressOffset>0x78</addressOffset> 605 <fields> 606 <field> 607 <name>ALL</name> 608 <description>Mask of all of the pins on the port.</description> 609 <bitOffset>0</bitOffset> 610 <bitWidth>32</bitWidth> 611 </field> 612 </fields> 613 </register> 614 <register> 615 <name>EN2_CLR</name> 616 <description>GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.</description> 617 <addressOffset>0x7C</addressOffset> 618 <fields> 619 <field> 620 <name>ALL</name> 621 <description>Mask of all of the pins on the port.</description> 622 <bitOffset>0</bitOffset> 623 <bitWidth>32</bitWidth> 624 </field> 625 </fields> 626 </register> 627 <register> 628 <name>DS0</name> 629 <description>GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 630 <addressOffset>0xB0</addressOffset> 631 <fields> 632 <field> 633 <name>ALL</name> 634 <description>Mask of all of the pins on the port.</description> 635 <bitOffset>0</bitOffset> 636 <bitWidth>32</bitWidth> 637 <enumeratedValues> 638 <enumeratedValue> 639 <name>ld</name> 640 <description>GPIO port pin is in low-drive mode.</description> 641 <value>0</value> 642 </enumeratedValue> 643 <enumeratedValue> 644 <name>hd</name> 645 <description>GPIO port pin is in high-drive mode.</description> 646 <value>1</value> 647 </enumeratedValue> 648 </enumeratedValues> 649 </field> 650 </fields> 651 </register> 652 <register> 653 <name>DS1</name> 654 <description>GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 655 <addressOffset>0xB4</addressOffset> 656 <fields> 657 <field> 658 <name>ALL</name> 659 <description>Mask of all of the pins on the port.</description> 660 <bitOffset>0</bitOffset> 661 <bitWidth>32</bitWidth> 662 </field> 663 </fields> 664 </register> 665 <register> 666 <name>PS</name> 667 <description>GPIO Pull Select Mode.</description> 668 <addressOffset>0xB8</addressOffset> 669 <fields> 670 <field> 671 <name>ALL</name> 672 <description>Mask of all of the pins on the port.</description> 673 <bitOffset>0</bitOffset> 674 <bitWidth>32</bitWidth> 675 </field> 676 </fields> 677 </register> 678 <register> 679 <name>VSSEL</name> 680 <description>GPIO Voltage Select.</description> 681 <addressOffset>0xC0</addressOffset> 682 <fields> 683 <field> 684 <name>ALL</name> 685 <description>Mask of all of the pins on the port.</description> 686 <bitOffset>0</bitOffset> 687 <bitWidth>32</bitWidth> 688 </field> 689 </fields> 690 </register> 691 </registers> 692 </peripheral> 693 <!-- GPIO0: Individual I/O for Port 0 --> 694</device>
