1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>FLC</name> 5 <description>Flash Memory Control.</description> 6 <prependToName>FLSH_</prependToName> 7 <baseAddress>0x40029000</baseAddress> 8 <addressBlock> 9 <offset>0x00</offset> 10 <size>0x1000</size> 11 <usage>registers</usage> 12 </addressBlock> 13 <interrupt> 14 <name>Flash_Controller</name> 15 <description>Flash Controller interrupt.</description> 16 <value>23</value> 17 </interrupt> 18 <registers> 19 <register> 20 <name>ADDR</name> 21 <description>Flash Write Address.</description> 22 <addressOffset>0x00</addressOffset> 23 <fields> 24 <field> 25 <name>ADDR</name> 26 <description>Address for next operation.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <name>CLKDIV</name> 34 <description>Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.</description> 35 <addressOffset>0x04</addressOffset> 36 <resetValue>0x00000064</resetValue> 37 <fields> 38 <field> 39 <name>CLKDIV</name> 40 <description>Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.</description> 41 <bitOffset>0</bitOffset> 42 <bitWidth>8</bitWidth> 43 </field> 44 </fields> 45 </register> 46 <register> 47 <name>CTRL</name> 48 <description>Flash Control Register.</description> 49 <addressOffset>0x08</addressOffset> 50 <fields> 51 <field> 52 <name>WR</name> 53 <description>Write. This bit is automatically cleared after the operation.</description> 54 <bitOffset>0</bitOffset> 55 <bitWidth>1</bitWidth> 56 <enumeratedValues> 57 <enumeratedValue> 58 <name>complete</name> 59 <description>No operation/complete.</description> 60 <value>0</value> 61 </enumeratedValue> 62 <enumeratedValue> 63 <name>start</name> 64 <description>Start operation.</description> 65 <value>1</value> 66 </enumeratedValue> 67 </enumeratedValues> 68 </field> 69 <field derivedFrom="WR"> 70 <name>ME</name> 71 <description>Mass Erase. This bit is automatically cleared after the operation.</description> 72 <bitOffset>1</bitOffset> 73 <bitWidth>1</bitWidth> 74 </field> 75 <field derivedFrom="WR"> 76 <name>PGE</name> 77 <description>Page Erase. This bit is automatically cleared after the operation.</description> 78 <bitOffset>2</bitOffset> 79 <bitWidth>1</bitWidth> 80 </field> 81 <field> 82 <name>WDTH</name> 83 <description>TBD</description> 84 <bitOffset>4</bitOffset> 85 <bitWidth>1</bitWidth> 86 </field> 87 <field> 88 <name>ERASE_CODE</name> 89 <description>Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.</description> 90 <bitOffset>8</bitOffset> 91 <bitWidth>8</bitWidth> 92 <enumeratedValues> 93 <enumeratedValue> 94 <name>nop</name> 95 <description>No operation.</description> 96 <value>0</value> 97 </enumeratedValue> 98 <enumeratedValue> 99 <name>erasePage</name> 100 <description>Enable Page Erase.</description> 101 <value>0x55</value> 102 </enumeratedValue> 103 <enumeratedValue> 104 <name>eraseAll</name> 105 <description>Enable Mass Erase. The debug port must be enabled.</description> 106 <value>0xAA</value> 107 </enumeratedValue> 108 </enumeratedValues> 109 </field> 110 <field> 111 <name>PEND</name> 112 <description>Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.</description> 113 <bitOffset>24</bitOffset> 114 <bitWidth>1</bitWidth> 115 <access>read-only</access> 116 <enumeratedValues> 117 <enumeratedValue> 118 <name>idle</name> 119 <description>Idle.</description> 120 <value>0</value> 121 </enumeratedValue> 122 <enumeratedValue> 123 <name>busy</name> 124 <description>Busy.</description> 125 <value>1</value> 126 </enumeratedValue> 127 </enumeratedValues> 128 </field> 129 <field> 130 <name>LVE</name> 131 <description>Low Voltage enable.</description> 132 <bitOffset>25</bitOffset> 133 <bitWidth>1</bitWidth> 134 </field> 135 <field> 136 <name>UNLOCK</name> 137 <description>Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.</description> 138 <bitOffset>28</bitOffset> 139 <bitWidth>4</bitWidth> 140 <enumeratedValues> 141 <enumeratedValue> 142 <name>unlocked</name> 143 <description>Flash Unlocked.</description> 144 <value>2</value> 145 </enumeratedValue> 146 <enumeratedValue> 147 <name>locked</name> 148 <description>Flash Locked.</description> 149 <value>3</value> 150 </enumeratedValue> 151 </enumeratedValues> 152 </field> 153 </fields> 154 </register> 155 <register> 156 <name>INTR</name> 157 <description>Flash Interrupt Register.</description> 158 <addressOffset>0x024</addressOffset> 159 <fields> 160 <field> 161 <name>DONE_IF</name> 162 <description>Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion.</description> 163 <bitOffset>0</bitOffset> 164 <bitWidth>1</bitWidth> 165 <enumeratedValues> 166 <enumeratedValue> 167 <name>inactive</name> 168 <description>No interrupt is pending.</description> 169 <value>0</value> 170 </enumeratedValue> 171 <enumeratedValue> 172 <name>pending</name> 173 <description>An interrupt is pending.</description> 174 <value>1</value> 175 </enumeratedValue> 176 </enumeratedValues> 177 </field> 178 <field> 179 <name>AF_IF</name> 180 <description>Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.</description> 181 <bitOffset>1</bitOffset> 182 <bitWidth>1</bitWidth> 183 <enumeratedValues> 184 <enumeratedValue> 185 <name>noerr</name> 186 <description>No Failure.</description> 187 <value>0</value> 188 </enumeratedValue> 189 <enumeratedValue> 190 <name>error</name> 191 <description>Failure occurs.</description> 192 <value>1</value> 193 </enumeratedValue> 194 </enumeratedValues> 195 </field> 196 <field> 197 <name>PROG_PROT_ERR_IF</name> 198 <description>Program Protection Error.</description> 199 <bitOffset>2</bitOffset> 200 <bitWidth>1</bitWidth> 201 <enumeratedValues> 202 <enumeratedValue> 203 <name>noerr</name> 204 <description>No Failure.</description> 205 <value>0</value> 206 </enumeratedValue> 207 <enumeratedValue> 208 <name>error</name> 209 <description>Failure occurs.</description> 210 <value>1</value> 211 </enumeratedValue> 212 </enumeratedValues> 213 </field> 214 <field> 215 <name>MASS_ER_PROT_ERR_IF</name> 216 <description>TBD</description> 217 <bitOffset>3</bitOffset> 218 <bitWidth>1</bitWidth> 219 <enumeratedValues> 220 <enumeratedValue> 221 <name>noerr</name> 222 <description>No Failure.</description> 223 <value>0</value> 224 </enumeratedValue> 225 <enumeratedValue> 226 <name>error</name> 227 <description>Failure occurs.</description> 228 <value>1</value> 229 </enumeratedValue> 230 </enumeratedValues> 231 </field> 232 <field> 233 <name>PAGE_ER_PROT_ERR_IF</name> 234 <description>TBD</description> 235 <bitOffset>4</bitOffset> 236 <bitWidth>1</bitWidth> 237 <enumeratedValues> 238 <enumeratedValue> 239 <name>noerr</name> 240 <description>No Failure.</description> 241 <value>0</value> 242 </enumeratedValue> 243 <enumeratedValue> 244 <name>error</name> 245 <description>Failure occurs.</description> 246 <value>1</value> 247 </enumeratedValue> 248 </enumeratedValues> 249 </field> 250 <field> 251 <name>PROT_AREA_PROT_ERR_IF</name> 252 <description>TBD</description> 253 <bitOffset>5</bitOffset> 254 <bitWidth>1</bitWidth> 255 <enumeratedValues> 256 <enumeratedValue> 257 <name>noerr</name> 258 <description>No Failure.</description> 259 <value>0</value> 260 </enumeratedValue> 261 <enumeratedValue> 262 <name>error</name> 263 <description>Failure occurs.</description> 264 <value>1</value> 265 </enumeratedValue> 266 </enumeratedValues> 267 </field> 268 <field> 269 <name>DONE_IE</name> 270 <description>Flash Done Interrupt Enable.</description> 271 <bitOffset>8</bitOffset> 272 <bitWidth>1</bitWidth> 273 <enumeratedValues> 274 <enumeratedValue> 275 <name>dis</name> 276 <description>Disable.</description> 277 <value>0</value> 278 </enumeratedValue> 279 <enumeratedValue> 280 <name>en</name> 281 <description>Enable.</description> 282 <value>1</value> 283 </enumeratedValue> 284 </enumeratedValues> 285 </field> 286 <field> 287 <name>AF_IE</name> 288 <bitOffset>9</bitOffset> 289 <bitWidth>1</bitWidth> 290 <enumeratedValues> 291 <enumeratedValue> 292 <name>dis</name> 293 <description>Disable.</description> 294 <value>0</value> 295 </enumeratedValue> 296 <enumeratedValue> 297 <name>en</name> 298 <description>Enable.</description> 299 <value>1</value> 300 </enumeratedValue> 301 </enumeratedValues> 302 </field> 303 <field> 304 <name>PROT_IE</name> 305 <bitOffset>10</bitOffset> 306 <bitWidth>1</bitWidth> 307 <enumeratedValues> 308 <enumeratedValue> 309 <name>dis</name> 310 <description>Disable.</description> 311 <value>0</value> 312 </enumeratedValue> 313 <enumeratedValue> 314 <name>en</name> 315 <description>Enable.</description> 316 <value>1</value> 317 </enumeratedValue> 318 </enumeratedValues> 319 </field> 320 </fields> 321 </register> 322 <register> 323 <dim>4</dim> 324 <dimIncrement>4</dimIncrement> 325 <name>DATA[%s]</name> 326 <description>Flash Write Data.</description> 327 <addressOffset>0x30</addressOffset> 328 <fields> 329 <field> 330 <name>DATA</name> 331 <description>Data next operation.</description> 332 <bitOffset>0</bitOffset> 333 <bitWidth>32</bitWidth> 334 </field> 335 </fields> 336 </register> 337 <register> 338 <name>ACTRL</name> 339 <description>Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.</description> 340 <addressOffset>0x40</addressOffset> 341 <access>write-only</access> 342 <fields> 343 <field> 344 <name>ACTRL</name> 345 <description>Access control.</description> 346 <bitOffset>0</bitOffset> 347 <bitWidth>32</bitWidth> 348 </field> 349 </fields> 350 </register> 351 <register> 352 <name>WELR0</name> 353 <description>Access control.</description> 354 <addressOffset>0x80</addressOffset> 355 <access>read-write</access> 356 <fields> 357 <field> 358 <name>WELR0</name> 359 <description>TBD</description> 360 <bitOffset>0</bitOffset> 361 <bitWidth>32</bitWidth> 362 </field> 363 </fields> 364 </register> 365 <register> 366 <name>RLR0</name> 367 <description>Access control.</description> 368 <addressOffset>0x84</addressOffset> 369 <access>read-write</access> 370 <fields> 371 <field> 372 <name>RLR0</name> 373 <description>TBD</description> 374 <bitOffset>0</bitOffset> 375 <bitWidth>32</bitWidth> 376 </field> 377 </fields> 378 </register> 379 <register> 380 <name>WELR1</name> 381 <description>Access control.</description> 382 <addressOffset>0x88</addressOffset> 383 <access>read-write</access> 384 <fields> 385 <field> 386 <name>WELR1</name> 387 <description>TBD</description> 388 <bitOffset>0</bitOffset> 389 <bitWidth>32</bitWidth> 390 </field> 391 </fields> 392 </register> 393 <register> 394 <name>RLR1</name> 395 <description>Access control.</description> 396 <addressOffset>0x8C</addressOffset> 397 <access>read-write</access> 398 <fields> 399 <field> 400 <name>RLR1</name> 401 <description>TBD</description> 402 <bitOffset>0</bitOffset> 403 <bitWidth>32</bitWidth> 404 </field> 405 </fields> 406 </register> 407 <register> 408 <name>WELR2</name> 409 <description>Access control.</description> 410 <addressOffset>0x90</addressOffset> 411 <access>read-write</access> 412 <fields> 413 <field> 414 <name>WELR2</name> 415 <description>TBD</description> 416 <bitOffset>0</bitOffset> 417 <bitWidth>32</bitWidth> 418 </field> 419 </fields> 420 </register> 421 <register> 422 <name>RLR2</name> 423 <description>Access control.</description> 424 <addressOffset>0x94</addressOffset> 425 <access>read-write</access> 426 <fields> 427 <field> 428 <name>RLR2</name> 429 <description>TBD</description> 430 <bitOffset>0</bitOffset> 431 <bitWidth>32</bitWidth> 432 </field> 433 </fields> 434 </register> 435 <register> 436 <name>WELR3</name> 437 <description>Access control.</description> 438 <addressOffset>0x98</addressOffset> 439 <access>read-write</access> 440 <fields> 441 <field> 442 <name>WELR3</name> 443 <description>TBD</description> 444 <bitOffset>0</bitOffset> 445 <bitWidth>32</bitWidth> 446 </field> 447 </fields> 448 </register> 449 <register> 450 <name>RLR3</name> 451 <description>Access control.</description> 452 <addressOffset>0x9C</addressOffset> 453 <access>read-write</access> 454 <fields> 455 <field> 456 <name>RLR3</name> 457 <description>TBD</description> 458 <bitOffset>0</bitOffset> 459 <bitWidth>32</bitWidth> 460 </field> 461 </fields> 462 </register> 463 <register> 464 <name>WELR4</name> 465 <description>Access control.</description> 466 <addressOffset>0xA0</addressOffset> 467 <access>read-write</access> 468 <fields> 469 <field> 470 <name>WELR4</name> 471 <description>TBD</description> 472 <bitOffset>0</bitOffset> 473 <bitWidth>32</bitWidth> 474 </field> 475 </fields> 476 </register> 477 <register> 478 <name>RLR4</name> 479 <description>Access control.</description> 480 <addressOffset>0xA4</addressOffset> 481 <access>read-write</access> 482 <fields> 483 <field> 484 <name>RLR4</name> 485 <description>TBD</description> 486 <bitOffset>0</bitOffset> 487 <bitWidth>32</bitWidth> 488 </field> 489 </fields> 490 </register> 491 <register> 492 <name>WELR5</name> 493 <description>Access control.</description> 494 <addressOffset>0xA8</addressOffset> 495 <access>read-write</access> 496 <fields> 497 <field> 498 <name>WELR5</name> 499 <description>TBD</description> 500 <bitOffset>0</bitOffset> 501 <bitWidth>32</bitWidth> 502 </field> 503 </fields> 504 </register> 505 <register> 506 <name>RLR5</name> 507 <description>Access control.</description> 508 <addressOffset>0xAC</addressOffset> 509 <access>read-write</access> 510 <fields> 511 <field> 512 <name>RLR5</name> 513 <description>TBD</description> 514 <bitOffset>0</bitOffset> 515 <bitWidth>32</bitWidth> 516 </field> 517 </fields> 518 </register> 519 </registers> 520 </peripheral> 521 <!-- FC: Flash Memory Control --> 522</device>
