1<?xml version="1.0" encoding="utf-8" standalone="no"?>
2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd">
3 <peripheral>
4  <name>EMCC</name>
5  <description>External Memory Cache Controller Registers.</description>
6  <baseAddress>0x40033000</baseAddress>
7  <addressBlock>
8   <offset>0x00</offset>
9   <size>0x1000</size>
10   <usage>registers</usage>
11  </addressBlock>
12  <registers>
13   <register>
14    <name>CACHE_ID</name>
15    <description>Cache ID Register.</description>
16    <addressOffset>0x0000</addressOffset>
17    <access>read-only</access>
18    <fields>
19     <field>
20      <name>RELNUM</name>
21      <description>Release Number. Identifies the RTL release version.</description>
22      <bitOffset>0</bitOffset>
23      <bitWidth>6</bitWidth>
24     </field>
25     <field>
26      <name>PARTNUM</name>
27      <description>Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.</description>
28      <bitOffset>6</bitOffset>
29      <bitWidth>4</bitWidth>
30     </field>
31     <field>
32      <name>CCHID</name>
33      <description>Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.</description>
34      <bitOffset>10</bitOffset>
35      <bitWidth>6</bitWidth>
36     </field>
37    </fields>
38   </register>
39   <register>
40    <name>MEM_SIZE</name>
41    <description>Memory Configuration Register.</description>
42    <addressOffset>0x0004</addressOffset>
43    <access>read-only</access>
44    <resetValue>0x00080008</resetValue>
45    <fields>
46     <field>
47      <name>CCHSZ</name>
48      <description>Cache Size. Indicates total size in Kbytes of cache.</description>
49      <bitOffset>0</bitOffset>
50      <bitWidth>16</bitWidth>
51     </field>
52     <field>
53      <name>MEMSZ</name>
54      <description>Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.</description>
55      <bitOffset>16</bitOffset>
56      <bitWidth>16</bitWidth>
57     </field>
58    </fields>
59   </register>
60   <register>
61    <name>CACHE_CTRL</name>
62    <description>Cache Control and Status Register.</description>
63    <addressOffset>0x0100</addressOffset>
64    <fields>
65     <field>
66      <name>ENABLE</name>
67      <description>Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.</description>
68      <bitOffset>0</bitOffset>
69      <bitWidth>1</bitWidth>
70      <enumeratedValues>
71       <enumeratedValue>
72        <name>dis</name>
73        <description>Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.</description>
74        <value>0</value>
75       </enumeratedValue>
76       <enumeratedValue>
77        <name>en</name>
78        <description>Cache Enabled.</description>
79        <value>1</value>
80       </enumeratedValue>
81      </enumeratedValues>
82     </field>
83     <field>
84      <name>WRITE_ALLOC</name>
85      <description>Write Allocate Enable. This bit only writable while the cache is disabled.</description>
86      <bitOffset>1</bitOffset>
87      <bitWidth>1</bitWidth>
88      <enumeratedValues>
89       <enumeratedValue>
90        <name>dis</name>
91        <description>Write-no-allocate.</description>
92        <value>0</value>
93       </enumeratedValue>
94       <enumeratedValue>
95        <name>en</name>
96        <description>Write-allocate enabled.</description>
97        <value>1</value>
98       </enumeratedValue>
99      </enumeratedValues>
100     </field>
101     <field>
102      <name>CWFST_DIS</name>
103      <description>Critical word first and streaming disable. This bit only writeable while the cache is disabled.</description>
104      <bitOffset>2</bitOffset>
105      <bitWidth>1</bitWidth>
106      <enumeratedValues>
107       <enumeratedValue>
108        <name>dis</name>
109        <description>Critical word first and streaming disabled.</description>
110        <value>1</value>
111       </enumeratedValue>
112       <enumeratedValue>
113        <name>en</name>
114        <description>Critical word first and streaming enabled.</description>
115        <value>0</value>
116       </enumeratedValue>
117      </enumeratedValues>
118     </field>
119     <field>
120      <name>READY</name>
121      <description>Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.</description>
122      <bitOffset>16</bitOffset>
123      <bitWidth>1</bitWidth>
124      <enumeratedValues>
125       <enumeratedValue>
126        <name>notReady</name>
127        <description>Not Ready.</description>
128        <value>0</value>
129       </enumeratedValue>
130       <enumeratedValue>
131        <name>ready</name>
132        <description>Ready.</description>
133        <value>1</value>
134       </enumeratedValue>
135      </enumeratedValues>
136     </field>
137    </fields>
138   </register>
139   <register>
140    <name>INVALIDATE</name>
141    <description>Invalidate All Cache Contents. Any time this register location is written (regardless of the data value), the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the invalidate operation is complete. System software can examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the invalidate operation is complete. Note that it is not necessary to disable the cache controller prior to beginning this operation. Reads from this register always return 0.</description>
142    <addressOffset>0x0700</addressOffset>
143    <fields>
144     <field>
145      <name>IA</name>
146      <description>Invalidate all cache contents.</description>
147      <bitOffset>0</bitOffset>
148      <bitWidth>32</bitWidth>
149     </field>
150    </fields>
151   </register>
152  </registers>
153 </peripheral>
154<!-- DCC:
155                                                     Data Cache Controller Registers       -->
156</device>
157