1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 /* **** Includes **** */
22 #include "emcc.h"
23 #include "srcc_reva.h"
24
25 /* ************************************************************************** */
MXC_EMCC_ID(mxc_emcc_cache_id_t id)26 uint32_t MXC_EMCC_ID(mxc_emcc_cache_id_t id)
27 {
28 switch (id) {
29 case MXC_EMCC_CACHE_ID_RELNUM:
30 return ((MXC_EMCC->cache_id) & MXC_F_EMCC_CACHE_ID_RELNUM) >>
31 MXC_F_EMCC_CACHE_ID_RELNUM_POS;
32 case MXC_EMCC_CACHE_ID_PARTNUM:
33 return ((MXC_EMCC->cache_id) & MXC_F_EMCC_CACHE_ID_PARTNUM) >>
34 MXC_F_EMCC_CACHE_ID_PARTNUM_POS;
35 case MXC_EMCC_CACHE_ID_CCHID:
36 return ((MXC_EMCC->cache_id) & MXC_F_EMCC_CACHE_ID_CCHID) >> MXC_F_EMCC_CACHE_ID_CCHID_POS;
37 default:
38 return E_BAD_PARAM;
39 }
40 }
41
42 /* ************************************************************************** */
MXC_EMCC_CacheSize(void)43 uint32_t MXC_EMCC_CacheSize(void)
44 {
45 return MXC_SRCC_RevA_CacheSize((mxc_srcc_reva_regs_t *)MXC_EMCC);
46 }
47
48 /* ************************************************************************** */
MXC_EMCC_MemSize(void)49 uint32_t MXC_EMCC_MemSize(void)
50 {
51 return MXC_SRCC_RevA_MemSize((mxc_srcc_reva_regs_t *)MXC_EMCC);
52 }
53
54 /* ************************************************************************** */
MXC_EMCC_Enable(void)55 void MXC_EMCC_Enable(void)
56 {
57 MXC_SRCC_RevA_Enable((mxc_srcc_reva_regs_t *)MXC_EMCC);
58 }
59
60 /* ************************************************************************** */
MXC_EMCC_Disable(void)61 void MXC_EMCC_Disable(void)
62 {
63 MXC_SRCC_RevA_Disable((mxc_srcc_reva_regs_t *)MXC_EMCC);
64 }
65
66 /* ************************************************************************** */
MXC_EMCC_Flush(void)67 void MXC_EMCC_Flush(void)
68 {
69 MXC_EMCC_Disable();
70 MXC_EMCC_Enable();
71 }
72
73 /* ************************************************************************** */
MXC_EMCC_WriteAllocEnable(void)74 void MXC_EMCC_WriteAllocEnable(void)
75 {
76 /* When a cache line is allocated on write operations, this is called
77 "write-allocate". However, there can be performance problems with
78 "write-allocate" because software frequently operates memset() on large
79 portions of memory. This can "pollute" the cache with unwanted cache lines.
80 To avoid this issue, the write-allocate feature is disable by default. The
81 write- allocate enable bit is in CACHE_CTRL[1]. */
82 MXC_SRCC_RevA_WriteAllocateEnable((mxc_srcc_reva_regs_t *)MXC_EMCC);
83 }
84
85 /* ************************************************************************** */
MXC_EMCC_WriteAllocDisable(void)86 void MXC_EMCC_WriteAllocDisable(void)
87 {
88 MXC_SRCC_RevA_WriteAllocateDisable((mxc_srcc_reva_regs_t *)MXC_EMCC);
89 }
90
91 /* ************************************************************************** */
MXC_EMCC_CriticalWordFirstEnable(void)92 void MXC_EMCC_CriticalWordFirstEnable(void)
93 {
94 if (!(MXC_EMCC->cache_ctrl &
95 MXC_F_EMCC_CACHE_CTRL_ENABLE)) { //CWFST_DIS field only writable when cache disabled
96 MXC_EMCC->cache_ctrl &= ~MXC_F_EMCC_CACHE_CTRL_CWFST_DIS;
97 }
98 }
99
100 /* ************************************************************************** */
MXC_EMCC_CriticalWordFirstDisable(void)101 void MXC_EMCC_CriticalWordFirstDisable(void)
102 {
103 if (!(MXC_EMCC->cache_ctrl &
104 MXC_F_EMCC_CACHE_CTRL_ENABLE)) { //CWFST_DIS field only writable when cache disabled
105 MXC_EMCC->cache_ctrl |= MXC_F_EMCC_CACHE_CTRL_CWFST_DIS;
106 }
107 }
108
109 /* ************************************************************************** */
MXC_EMCC_Ready(void)110 uint32_t MXC_EMCC_Ready(void)
111 {
112 /* Cache Ready flag. Cleared by hardware when at any time the cache as a
113 whole is invalidated ( including a system reset). When this bit is 0, the
114 cache is effectively in bypass mode (data fetches will come from main memory
115 or from the line fill buffer). Set by hardware when the invalidate operation
116 is complete and the cache is ready. */
117 return MXC_SRCC_RevA_Ready((mxc_srcc_reva_regs_t *)MXC_EMCC);
118 }
119
120 /* ************************************************************************** */
MXC_EMCC_Invalidate_All(void)121 void MXC_EMCC_Invalidate_All(void)
122 {
123 /* Invalidate All Cache Contents. Any time this register location is written
124 (regardless of the data value), the cache controller immediately begins
125 invalidating the entire contents of the cache memory. The cache will be in
126 bypass mode until the invalidate operation is complete. System software can
127 examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the
128 invalidate operation is complete. Note that it is not necessary to disable
129 the cache controller prior to beginning this operation. Reads from this
130 register always return 0. */
131 MXC_EMCC->invalidate |= MXC_F_EMCC_INVALIDATE_IA;
132 }
133
