1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>EMAC</name> 5 <description>10/100 Ethernet MAC.</description> 6 <baseAddress>0x4004F000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>EMAC</name> 14 <description>EMAC IRQ</description> 15 <value>64</value> 16 </interrupt> 17 <registers> 18 <register> 19 <name>CN</name> 20 <description>Network Control Register.</description> 21 <addressOffset>0x00</addressOffset> 22 <resetValue>0x00</resetValue> 23 <fields> 24 <field> 25 <name>LB</name> 26 <description>Loopback.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>1</bitWidth> 29 <access>read-write</access> 30 </field> 31 <field> 32 <name>LBL</name> 33 <description>Loopback local.</description> 34 <bitOffset>1</bitOffset> 35 <bitWidth>1</bitWidth> 36 <access>read-write</access> 37 </field> 38 <field> 39 <name>RXEN</name> 40 <description>Receive Enable.</description> 41 <bitOffset>2</bitOffset> 42 <bitWidth>1</bitWidth> 43 <access>read-write</access> 44 </field> 45 <field> 46 <name>TXEN</name> 47 <description>Transmit Enable.</description> 48 <bitOffset>3</bitOffset> 49 <bitWidth>1</bitWidth> 50 <access>read-write</access> 51 </field> 52 <field> 53 <name>MPEN</name> 54 <description>Management Port Enable.</description> 55 <bitOffset>4</bitOffset> 56 <bitWidth>1</bitWidth> 57 <access>read-write</access> 58 </field> 59 <field> 60 <name>CLST</name> 61 <description>Clear Statistics.</description> 62 <bitOffset>5</bitOffset> 63 <bitWidth>1</bitWidth> 64 <access>write-only</access> 65 </field> 66 <field> 67 <name>INCST</name> 68 <description>Increment Statistics.</description> 69 <bitOffset>6</bitOffset> 70 <bitWidth>1</bitWidth> 71 <access>write-only</access> 72 </field> 73 <field> 74 <name>WREN</name> 75 <description>Write enable for statistics registers.</description> 76 <bitOffset>7</bitOffset> 77 <bitWidth>1</bitWidth> 78 <access>read-write</access> 79 </field> 80 <field> 81 <name>BP</name> 82 <description>Back pressure.</description> 83 <bitOffset>8</bitOffset> 84 <bitWidth>1</bitWidth> 85 <access>read-write</access> 86 </field> 87 <field> 88 <name>TXSTART</name> 89 <description>Transmission start.</description> 90 <bitOffset>9</bitOffset> 91 <bitWidth>1</bitWidth> 92 <access>write-only</access> 93 </field> 94 <field> 95 <name>TXHALT</name> 96 <description>Transmit halt.</description> 97 <bitOffset>10</bitOffset> 98 <bitWidth>1</bitWidth> 99 <access>write-only</access> 100 </field> 101 <field> 102 <name>TXPF</name> 103 <description>Transmit pause frame.</description> 104 <bitOffset>11</bitOffset> 105 <bitWidth>1</bitWidth> 106 <access>write-only</access> 107 </field> 108 <field> 109 <name>TXZQPF</name> 110 <description>Transmit zero quantum pause frame.</description> 111 <bitOffset>12</bitOffset> 112 <bitWidth>1</bitWidth> 113 <access>write-only</access> 114 </field> 115 </fields> 116 </register> 117 <register> 118 <name>CFG</name> 119 <description>Network Configuration Register.</description> 120 <addressOffset>0x04</addressOffset> 121 <fields> 122 <field> 123 <name>SPEED</name> 124 <description>Speed Select.</description> 125 <bitOffset>0</bitOffset> 126 <bitWidth>1</bitWidth> 127 <access>read-write</access> 128 </field> 129 <field> 130 <name>FULLDPLX</name> 131 <description>Full Duplex. If set to 1 the transmit block ignores the state of collision and carrier sense and allows Rx while transmitting.</description> 132 <bitOffset>1</bitOffset> 133 <bitWidth>1</bitWidth> 134 <access>read-write</access> 135 </field> 136 <field> 137 <name>BITRATE</name> 138 <description>Bit Rate. Writing 1 to this bit configures the interface for serial operation. </description> 139 <bitOffset>2</bitOffset> 140 <bitWidth>1</bitWidth> 141 <access>read-write</access> 142 </field> 143 <field> 144 <name>JUMBOFR</name> 145 <description>Jumbo Frames. Writing 1 to this bit enables jumbo frames of up to 10,240 bytes to be accepted.</description> 146 <bitOffset>3</bitOffset> 147 <bitWidth>1</bitWidth> 148 <access>read-write</access> 149 </field> 150 <field> 151 <name>COPYAF</name> 152 <description>Copy All Frames. If 1, all valid frames will be received.</description> 153 <bitOffset>4</bitOffset> 154 <bitWidth>1</bitWidth> 155 <access>read-write</access> 156 </field> 157 <field> 158 <name>NOBC</name> 159 <description>No Broadcast. If 1, frames addressed to the broadcast address of all ones will not be received.</description> 160 <bitOffset>5</bitOffset> 161 <bitWidth>1</bitWidth> 162 <access>write-only</access> 163 </field> 164 <field> 165 <name>MHEN</name> 166 <description>Multicast Hash Enable. If 1, multicast frames will be received when the 6 bit hash function of the destination address points to a bit that is set in the hash register.</description> 167 <bitOffset>6</bitOffset> 168 <bitWidth>1</bitWidth> 169 <access>write-only</access> 170 </field> 171 <field> 172 <name>UHEN</name> 173 <description>Unicast Hash Enable. If 1, unicast frames will be received when the 6 bit hash function of the destination address points to a bit that is set in the hash register.</description> 174 <bitOffset>7</bitOffset> 175 <bitWidth>1</bitWidth> 176 <access>read-write</access> 177 </field> 178 <field> 179 <name>RXFR</name> 180 <description>Receive 1536 Byte Frames. Writing 1 to this bit means the MAC receives packets up to 1536 bytes in length. Normally the MAC rejects any packet above 1518 bytes</description> 181 <bitOffset>8</bitOffset> 182 <bitWidth>1</bitWidth> 183 <access>read-write</access> 184 </field> 185 <field> 186 <name>MDCCLK</name> 187 <description>MDC Frequency. Set according to PCLK speed. This field determines by what number PCLK is divided to generate MDC.</description> 188 <bitOffset>10</bitOffset> 189 <bitWidth>2</bitWidth> 190 <access>write-only</access> 191 <enumeratedValues> 192 <enumeratedValue> 193 <name>div8</name> 194 <description>PCLK up to 20MHz</description> 195 <value>0</value> 196 </enumeratedValue> 197 <enumeratedValue> 198 <name>div16</name> 199 <description>PCLK up to 40MHz</description> 200 <value>1</value> 201 </enumeratedValue> 202 <enumeratedValue> 203 <name>div32</name> 204 <description>PCLK up to 80MHz</description> 205 <value>2</value> 206 </enumeratedValue> 207 <enumeratedValue> 208 <name>div64</name> 209 <description>PCLK up to 160MHz</description> 210 <value>3</value> 211 </enumeratedValue> 212 </enumeratedValues> 213 </field> 214 <field> 215 <name>RTTST</name> 216 <description>Retry Test. Must be set to zero for normal operation. If set to 1, the back-off between collisions is always one slot time.</description> 217 <bitOffset>12</bitOffset> 218 <bitWidth>1</bitWidth> 219 <access>write-only</access> 220 </field> 221 <field> 222 <name>PAUSEEN</name> 223 <description>Pause Enable. If 1, Ethernet packet transmission pauses when a valid pause packet is received.</description> 224 <bitOffset>13</bitOffset> 225 <bitWidth>1</bitWidth> 226 <access>write-only</access> 227 </field> 228 <field> 229 <name>RXBUFFOFS</name> 230 <description>Receive buffer offset. These bits indicate the number of bytes by which the received data is offset from the start of the first receive buffer.</description> 231 <bitOffset>14</bitOffset> 232 <bitWidth>2</bitWidth> 233 <access>write-only</access> 234 </field> 235 <field> 236 <name>RXLFCEN</name> 237 <description>Receive length field checking enable. If 1, packets with measured lengths shorter than their length fields are discarded. Packets containing a type ID in bytes 13 and 14 (length/type field >=0600) are not counted as length errors.</description> 238 <bitOffset>16</bitOffset> 239 <bitWidth>1</bitWidth> 240 <access>write-only</access> 241 </field> 242 <field> 243 <name>DCRXFCS</name> 244 <description>Discard receive FCS. If 1, the FCS field of received frames will not be copied to memory.</description> 245 <bitOffset>17</bitOffset> 246 <bitWidth>1</bitWidth> 247 <access>write-only</access> 248 </field> 249 <field> 250 <name>HDPLXRXEN</name> 251 <description>Enable packets to be received in half-duplex mode while transmitting.</description> 252 <bitOffset>18</bitOffset> 253 <bitWidth>1</bitWidth> 254 <access>write-only</access> 255 </field> 256 <field> 257 <name>IGNRXFCS</name> 258 <description>Ignore RX FCS. If 1, packets with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit must be set to 0.</description> 259 <bitOffset>19</bitOffset> 260 <bitWidth>1</bitWidth> 261 <access>write-only</access> 262 </field> 263 </fields> 264 </register> 265 <register> 266 <name>STATUS</name> 267 <description>Network Status Register.</description> 268 <addressOffset>0x08</addressOffset> 269 <access>read-only</access> 270 <fields> 271 <field> 272 <name>LINK</name> 273 <description>LINK pin status. Returns status of EMAC_LINK pin.</description> 274 <bitOffset>0</bitOffset> 275 <bitWidth>1</bitWidth> 276 <access>read-only</access> 277 </field> 278 <field> 279 <name>MDIO</name> 280 <description>MDIO pin status. Returns status of the EMAC_MDIO pin. Use the PHY maintenance register for reading managed frames rather than this bit.</description> 281 <bitOffset>1</bitOffset> 282 <bitWidth>1</bitWidth> 283 <access>read-only</access> 284 </field> 285 <field> 286 <name>IDLE</name> 287 <description>PHY management logic status.</description> 288 <bitOffset>2</bitOffset> 289 <bitWidth>1</bitWidth> 290 <access>read-only</access> 291 </field> 292 </fields> 293 </register> 294 <register> 295 <name>TX_ST</name> 296 <description>Transmit Status Register.</description> 297 <addressOffset>0x14</addressOffset> 298 <fields> 299 <field> 300 <name>UBR</name> 301 <description>Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Write 1 to clear this bit.</description> 302 <bitOffset>0</bitOffset> 303 <bitWidth>1</bitWidth> 304 <access>read-write</access> 305 </field> 306 <field> 307 <name>COLS</name> 308 <description>Collision Occurred. Set when a collision occurs. Write 1 to clear this bit.</description> 309 <bitOffset>1</bitOffset> 310 <bitWidth>1</bitWidth> 311 <access>read-write</access> 312 </field> 313 <field> 314 <name>RTYLIM</name> 315 <description>Retry Limit Exceeded. Set when the retry limit has been exceeded. Write 1 to clear this bit. </description> 316 <bitOffset>2</bitOffset> 317 <bitWidth>1</bitWidth> 318 <access>read-write</access> 319 </field> 320 <field> 321 <name>TXGO</name> 322 <description>Transmit Go. If 1, transmit is active.</description> 323 <bitOffset>3</bitOffset> 324 <bitWidth>1</bitWidth> 325 <access>read-write</access> 326 </field> 327 <field> 328 <name>BEMF</name> 329 <description>Buffers Exhausted Mid Frame. If the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and EMAC_TXER asserted. Write 1 to clear this bit.</description> 330 <bitOffset>4</bitOffset> 331 <bitWidth>1</bitWidth> 332 <access>read-write</access> 333 </field> 334 <field> 335 <name>TXCMPL</name> 336 <description>Transmit Complete. Set when a frame has been transmitted. Write 1 to clear this bit.</description> 337 <bitOffset>5</bitOffset> 338 <bitWidth>1</bitWidth> 339 <access>read-write</access> 340 </field> 341 <field> 342 <name>TXUR</name> 343 <description>Transmit Underrun. Set when the MAC transmit FIFO was read while was empty. If this happens the transmitter forces bad. Write 1 to clear this bit.</description> 344 <bitOffset>6</bitOffset> 345 <bitWidth>1</bitWidth> 346 <access>read-write</access> 347 </field> 348 </fields> 349 </register> 350 <register> 351 <name>RXBUF_PTR</name> 352 <description>Receive Buffer Queue Pointer Register.</description> 353 <addressOffset>0x18</addressOffset> 354 <fields> 355 <field> 356 <name>RXBUF</name> 357 <description>Receive buffer queue pointer. Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used.</description> 358 <bitOffset>2</bitOffset> 359 <bitWidth>30</bitWidth> 360 <access>read-write</access> 361 </field> 362 </fields> 363 </register> 364 <register> 365 <name>TXBUF_PTR</name> 366 <description>Transmit Buffer Queue Pointer Register.</description> 367 <addressOffset>0x1C</addressOffset> 368 <fields> 369 <field> 370 <name>TXBUF</name> 371 <description>Transmit buffer queue pointer. Written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmitted or about to be transmitted.</description> 372 <bitOffset>2</bitOffset> 373 <bitWidth>30</bitWidth> 374 <access>read-write</access> 375 </field> 376 </fields> 377 </register> 378 <register> 379 <name>RX_ST</name> 380 <description>Receive Status Register.</description> 381 <addressOffset>0x20</addressOffset> 382 <fields> 383 <field> 384 <name>BNA</name> 385 <description>Buffer Not Available. An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time a new frame starts until a valid pointer is found. This bit will be set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Write 1 to clear this bit.</description> 386 <bitOffset>0</bitOffset> 387 <bitWidth>1</bitWidth> 388 <access>read-write</access> 389 </field> 390 <field> 391 <name>FR</name> 392 <description>Frame Received. One or more frames have been received and placed in memory. Write 1 to clear this bit.</description> 393 <bitOffset>1</bitOffset> 394 <bitWidth>1</bitWidth> 395 <access>read-write</access> 396 </field> 397 <field> 398 <name>RXOR</name> 399 <description>Receive Overrun. The DMA block was unable to store the receive frame to memory. Either because the AHB bus was not granted in time or because a not OK hresp was returned. The buffer will be recovered if this happens. Write 1 to clear this bit.</description> 400 <bitOffset>2</bitOffset> 401 <bitWidth>1</bitWidth> 402 <access>read-write</access> 403 </field> 404 </fields> 405 </register> 406 <register> 407 <name>INT_ST</name> 408 <description>Interrupt Status Register.</description> 409 <addressOffset>0x24</addressOffset> 410 <fields> 411 <field> 412 <name>MPS</name> 413 <description>Management Packet Sent Interrupt Status. The PHY maintenance register has completed its operation. Cleared when read.</description> 414 <bitOffset>0</bitOffset> 415 <bitWidth>1</bitWidth> 416 <access>read-write</access> 417 </field> 418 <field> 419 <name>RXCMPL</name> 420 <description>Receive Complete Interrupt Status. Set when a frame has been stored in memory. Cleared when read.</description> 421 <bitOffset>1</bitOffset> 422 <bitWidth>1</bitWidth> 423 <access>read-write</access> 424 </field> 425 <field> 426 <name>RXUBR</name> 427 <description>RX Used Bit Read Interrupt Status. Set when a receive buffer descriptor is read with its used bit set. Cleared when read.</description> 428 <bitOffset>2</bitOffset> 429 <bitWidth>1</bitWidth> 430 <access>read-write</access> 431 </field> 432 <field> 433 <name>TXUBR</name> 434 <description>TX Used Bit Read Interrupt Status. Set when a transmit buffer descriptor is read with its used bit set. Cleared when read</description> 435 <bitOffset>3</bitOffset> 436 <bitWidth>1</bitWidth> 437 <access>read-write</access> 438 </field> 439 <field> 440 <name>TXUR</name> 441 <description>Ethernet Transmit Underrun Interrupt Status. Set when the MAC transmit FIFO was read while was empty. If this happens the transmitter forces bad CRC and forces EMAC_TXER high. Cleared when read.</description> 442 <bitOffset>4</bitOffset> 443 <bitWidth>1</bitWidth> 444 <access>read-write</access> 445 </field> 446 <field> 447 <name>RLE</name> 448 <description>Retry Limit Exceeded Interrupt Status. Transmit error. Cleared when read.</description> 449 <bitOffset>5</bitOffset> 450 <bitWidth>1</bitWidth> 451 <access>read-write</access> 452 </field> 453 <field> 454 <name>TXERR</name> 455 <description>Transmit Buffers Exhausted In Mid-frame Interrupt Status. Transmit error. Cleared when read.</description> 456 <bitOffset>6</bitOffset> 457 <bitWidth>1</bitWidth> 458 <access>read-write</access> 459 </field> 460 <field> 461 <name>TXCMPL</name> 462 <description>Transmit Complete Interrupt Status. Set when a frame has been transmitted. Cleared when read.</description> 463 <bitOffset>7</bitOffset> 464 <bitWidth>1</bitWidth> 465 <access>read-write</access> 466 </field> 467 <field> 468 <name>LC</name> 469 <description>Link Change Interrupt Status. Set when the external link signal changes. Cleared when read.</description> 470 <bitOffset>9</bitOffset> 471 <bitWidth>1</bitWidth> 472 <access>read-write</access> 473 </field> 474 <field> 475 <name>RXOR</name> 476 <description>Receive Overrun Interrupt Status. Set when the receive overrun status bit gets set. Cleared when read.</description> 477 <bitOffset>10</bitOffset> 478 <bitWidth>1</bitWidth> 479 <access>read-write</access> 480 </field> 481 <field> 482 <name>HRESPNO</name> 483 <description>hresp not OK Interrupt Status. Set when the DMA block sees hresp not OK. Cleared when read.</description> 484 <bitOffset>11</bitOffset> 485 <bitWidth>1</bitWidth> 486 <access>read-write</access> 487 </field> 488 <field> 489 <name>PPR</name> 490 <description>Pause Packet Received Interrupt Status. Indicates a valid pause packet has been received. Cleared when read.</description> 491 <bitOffset>12</bitOffset> 492 <bitWidth>1</bitWidth> 493 <access>read-write</access> 494 </field> 495 <field> 496 <name>PTZ</name> 497 <description>Pause Time Zero Interrupt Status. Set when the MAC Pause Time register (MAC_PT) decrements to zero. Cleared when read.</description> 498 <bitOffset>13</bitOffset> 499 <bitWidth>1</bitWidth> 500 <access>read-write</access> 501 </field> 502 </fields> 503 </register> 504 <register> 505 <name>INT_EN</name> 506 <description>Interrupt Enable Register.</description> 507 <addressOffset>0x28</addressOffset> 508 <access>write-only</access> 509 <fields> 510 <field> 511 <name>MPS</name> 512 <description>Management Packet Sent Interrupt Enable</description> 513 <bitOffset>0</bitOffset> 514 <bitWidth>1</bitWidth> 515 <access>write-only</access> 516 </field> 517 <field> 518 <name>RXCMPL</name> 519 <description>Receive Complete Interrupt Enable</description> 520 <bitOffset>1</bitOffset> 521 <bitWidth>1</bitWidth> 522 <access>write-only</access> 523 </field> 524 <field> 525 <name>RXUBR</name> 526 <description>RX Used Bit Read Interrupt Enable</description> 527 <bitOffset>2</bitOffset> 528 <bitWidth>1</bitWidth> 529 <access>write-only</access> 530 </field> 531 <field> 532 <name>TXUBR</name> 533 <description>TX Used Bit Read Interrupt Enable</description> 534 <bitOffset>3</bitOffset> 535 <bitWidth>1</bitWidth> 536 <access>write-only</access> 537 </field> 538 <field> 539 <name>TXUR</name> 540 <description>Ethernet Transmit Underrun Interrupt Enable</description> 541 <bitOffset>4</bitOffset> 542 <bitWidth>1</bitWidth> 543 <access>write-only</access> 544 </field> 545 <field> 546 <name>RLE</name> 547 <description>Retry Limit Exceeded Interrupt Enable</description> 548 <bitOffset>5</bitOffset> 549 <bitWidth>1</bitWidth> 550 <access>write-only</access> 551 </field> 552 <field> 553 <name>TXERR</name> 554 <description>Transmit Buffers Exhausted In Mid-frame Interrupt Enable</description> 555 <bitOffset>6</bitOffset> 556 <bitWidth>1</bitWidth> 557 <access>write-only</access> 558 </field> 559 <field> 560 <name>TXCMPL</name> 561 <description>Transmit Complete Interrupt Enable</description> 562 <bitOffset>7</bitOffset> 563 <bitWidth>1</bitWidth> 564 <access>write-only</access> 565 </field> 566 <field> 567 <name>LC</name> 568 <description>Link Change Interrupt Enable</description> 569 <bitOffset>9</bitOffset> 570 <bitWidth>1</bitWidth> 571 <access>write-only</access> 572 </field> 573 <field> 574 <name>RXOR</name> 575 <description>Receive Overrun Interrupt Enable</description> 576 <bitOffset>10</bitOffset> 577 <bitWidth>1</bitWidth> 578 <access>write-only</access> 579 </field> 580 <field> 581 <name>HRESPNO</name> 582 <description>hresp not OK Interrupt Enable</description> 583 <bitOffset>11</bitOffset> 584 <bitWidth>1</bitWidth> 585 <access>write-only</access> 586 </field> 587 <field> 588 <name>PPR</name> 589 <description>Pause Packet Received Interrupt Enable</description> 590 <bitOffset>12</bitOffset> 591 <bitWidth>1</bitWidth> 592 <access>write-only</access> 593 </field> 594 <field> 595 <name>PTZ</name> 596 <description>Pause Time Zero Interrupt Enable</description> 597 <bitOffset>13</bitOffset> 598 <bitWidth>1</bitWidth> 599 <access>write-only</access> 600 </field> 601 </fields> 602 </register> 603 <register> 604 <name>INT_DIS</name> 605 <description>Interrupt Disable Register.</description> 606 <addressOffset>0x2C</addressOffset> 607 <access>write-only</access> 608 <fields> 609 <field> 610 <name>MPS</name> 611 <description>Management Packet Sent Interrupt Disable</description> 612 <bitOffset>0</bitOffset> 613 <bitWidth>1</bitWidth> 614 <access>write-only</access> 615 </field> 616 <field> 617 <name>RXCMPL</name> 618 <description>Receive Complete Interrupt Disable</description> 619 <bitOffset>1</bitOffset> 620 <bitWidth>1</bitWidth> 621 <access>write-only</access> 622 </field> 623 <field> 624 <name>RXUBR</name> 625 <description>RX Used Bit Read Interrupt Disable</description> 626 <bitOffset>2</bitOffset> 627 <bitWidth>1</bitWidth> 628 <access>write-only</access> 629 </field> 630 <field> 631 <name>TXUBR</name> 632 <description>TX Used Bit Read Interrupt Disable</description> 633 <bitOffset>3</bitOffset> 634 <bitWidth>1</bitWidth> 635 <access>write-only</access> 636 </field> 637 <field> 638 <name>TXUR</name> 639 <description>Ethernet Transmit Underrun Interrupt Disable</description> 640 <bitOffset>4</bitOffset> 641 <bitWidth>1</bitWidth> 642 <access>write-only</access> 643 </field> 644 <field> 645 <name>RLE</name> 646 <description>Retry Limit Exceeded Interrupt Disable</description> 647 <bitOffset>5</bitOffset> 648 <bitWidth>1</bitWidth> 649 <access>write-only</access> 650 </field> 651 <field> 652 <name>TXERR</name> 653 <description>Transmit Buffers Exhausted In Mid-frame Interrupt Disable</description> 654 <bitOffset>6</bitOffset> 655 <bitWidth>1</bitWidth> 656 <access>write-only</access> 657 </field> 658 <field> 659 <name>TXCMPL</name> 660 <description>Transmit Complete Interrupt Disable</description> 661 <bitOffset>7</bitOffset> 662 <bitWidth>1</bitWidth> 663 <access>write-only</access> 664 </field> 665 <field> 666 <name>LC</name> 667 <description>Link Change Interrupt Disable</description> 668 <bitOffset>9</bitOffset> 669 <bitWidth>1</bitWidth> 670 <access>write-only</access> 671 </field> 672 <field> 673 <name>RXOR</name> 674 <description>Receive Overrun Interrupt Disable</description> 675 <bitOffset>10</bitOffset> 676 <bitWidth>1</bitWidth> 677 <access>write-only</access> 678 </field> 679 <field> 680 <name>HRESPNO</name> 681 <description>hresp not OK Interrupt Disable</description> 682 <bitOffset>11</bitOffset> 683 <bitWidth>1</bitWidth> 684 <access>write-only</access> 685 </field> 686 <field> 687 <name>PPR</name> 688 <description>Pause Packet Received Interrupt Disable</description> 689 <bitOffset>12</bitOffset> 690 <bitWidth>1</bitWidth> 691 <access>write-only</access> 692 </field> 693 <field> 694 <name>PTZ</name> 695 <description>Pause Time Zero Interrupt Disable</description> 696 <bitOffset>13</bitOffset> 697 <bitWidth>1</bitWidth> 698 <access>write-only</access> 699 </field> 700 </fields> 701 </register> 702 <register> 703 <name>INT_MASK</name> 704 <description>Interrupt Mask Register.</description> 705 <addressOffset>0x30</addressOffset> 706 <access>read-only</access> 707 <fields> 708 <field> 709 <name>MPS</name> 710 <description>Management Packet Sent Interrupt Mask</description> 711 <bitOffset>0</bitOffset> 712 <bitWidth>1</bitWidth> 713 <access>read-only</access> 714 </field> 715 <field> 716 <name>RXCMPL</name> 717 <description>Receive Complete Interrupt Mask</description> 718 <bitOffset>1</bitOffset> 719 <bitWidth>1</bitWidth> 720 <access>read-only</access> 721 </field> 722 <field> 723 <name>RXUBR</name> 724 <description>RX Used Bit Read Interrupt Mask</description> 725 <bitOffset>2</bitOffset> 726 <bitWidth>1</bitWidth> 727 <access>read-only</access> 728 </field> 729 <field> 730 <name>TXUBR</name> 731 <description>TX Used Bit Read Interrupt Mask</description> 732 <bitOffset>3</bitOffset> 733 <bitWidth>1</bitWidth> 734 <access>read-only</access> 735 </field> 736 <field> 737 <name>TXUR</name> 738 <description>Ethernet Transmit Underrun Interrupt Mask</description> 739 <bitOffset>4</bitOffset> 740 <bitWidth>1</bitWidth> 741 <access>read-only</access> 742 </field> 743 <field> 744 <name>RLE</name> 745 <description>Retry Limit Exceeded Interrupt Mask</description> 746 <bitOffset>5</bitOffset> 747 <bitWidth>1</bitWidth> 748 <access>read-only</access> 749 </field> 750 <field> 751 <name>TXERR</name> 752 <description>Transmit Buffers Exhausted In Mid-frame Interrupt Mask</description> 753 <bitOffset>6</bitOffset> 754 <bitWidth>1</bitWidth> 755 <access>read-only</access> 756 </field> 757 <field> 758 <name>TXCMPL</name> 759 <description>Transmit Complete Interrupt Mask</description> 760 <bitOffset>7</bitOffset> 761 <bitWidth>1</bitWidth> 762 <access>read-only</access> 763 </field> 764 <field> 765 <name>LC</name> 766 <description>Link Change Interrupt Mask</description> 767 <bitOffset>9</bitOffset> 768 <bitWidth>1</bitWidth> 769 <access>read-only</access> 770 </field> 771 <field> 772 <name>RXOR</name> 773 <description>Receive Overrun Interrupt Mask</description> 774 <bitOffset>10</bitOffset> 775 <bitWidth>1</bitWidth> 776 <access>read-only</access> 777 </field> 778 <field> 779 <name>HRESPNO</name> 780 <description>hresp not OK Interrupt Mask</description> 781 <bitOffset>11</bitOffset> 782 <bitWidth>1</bitWidth> 783 <access>read-only</access> 784 </field> 785 <field> 786 <name>PPR</name> 787 <description>Pause Packet Received Interrupt Mask</description> 788 <bitOffset>12</bitOffset> 789 <bitWidth>1</bitWidth> 790 <access>read-only</access> 791 </field> 792 <field> 793 <name>PTZ</name> 794 <description>Pause Time Zero Interrupt Mask</description> 795 <bitOffset>13</bitOffset> 796 <bitWidth>1</bitWidth> 797 <access>read-only</access> 798 </field> 799 </fields> 800 </register> 801 <register> 802 <name>PHY_MT</name> 803 <description>PHY Maintenance Register.</description> 804 <addressOffset>0x34</addressOffset> 805 <fields> 806 <field> 807 <name>DATA</name> 808 <description>PHY Data. For a write operation this field is the data to be written to the PHY. </description> 809 <bitOffset>0</bitOffset> 810 <bitWidth>16</bitWidth> 811 <access>read-write</access> 812 </field> 813 <field> 814 <name>REGADDR</name> 815 <description>Register Address. Specifies the register in the PHY to access.</description> 816 <bitOffset>18</bitOffset> 817 <bitWidth>5</bitWidth> 818 <access>read-write</access> 819 </field> 820 <field> 821 <name>PHYADDR</name> 822 <description>PHY Address. Specifies the PHY to access.</description> 823 <bitOffset>23</bitOffset> 824 <bitWidth>5</bitWidth> 825 <access>read-write</access> 826 </field> 827 <field> 828 <name>OP</name> 829 <description>Operation</description> 830 <bitOffset>28</bitOffset> 831 <bitWidth>2</bitWidth> 832 <access>read-write</access> 833 <enumeratedValues> 834 <enumeratedValue> 835 <name>write</name> 836 <description>Write</description> 837 <value>1</value> 838 </enumeratedValue> 839 <enumeratedValue> 840 <name>read</name> 841 <description>Read</description> 842 <value>2</value> 843 </enumeratedValue> 844 </enumeratedValues> 845 </field> 846 <field> 847 <name>SOP</name> 848 <description>TBD </description> 849 <bitOffset>30</bitOffset> 850 <bitWidth>2</bitWidth> 851 <access>read-write</access> 852 </field> 853 </fields> 854 </register> 855 <register> 856 <name>PT</name> 857 <description>Pause Time Register.</description> 858 <addressOffset>0x38</addressOffset> 859 <access>read-only</access> 860 <fields> 861 <field> 862 <name>TIME</name> 863 <description>Pause Time. Stores the current value of the pause time register, which is decremented every 512 bit times.</description> 864 <bitOffset>0</bitOffset> 865 <bitWidth>16</bitWidth> 866 <access>read-only</access> 867 </field> 868 </fields> 869 </register> 870 <register> 871 <name>PFR</name> 872 <description>Pause Frame Received OK.</description> 873 <addressOffset>0x3C</addressOffset> 874 <fields> 875 <field> 876 <name>PFR</name> 877 <description>Pause Frames Received OK. A 16-bit register counting the number of good pause frames received. </description> 878 <bitOffset>0</bitOffset> 879 <bitWidth>16</bitWidth> 880 <access>read-write</access> 881 </field> 882 </fields> 883 </register> 884 <register> 885 <name>FTOK</name> 886 <description>Frames Transmitted OK.</description> 887 <addressOffset>0x40</addressOffset> 888 <fields> 889 <field> 890 <name>FTOK</name> 891 <description>Frames Transmitted OK. A 32-bit register counting the number of frames successfully transmitted, i.e. no underrun and not too many retries.</description> 892 <bitOffset>0</bitOffset> 893 <bitWidth>32</bitWidth> 894 <access>read-write</access> 895 </field> 896 </fields> 897 </register> 898 <register> 899 <name>SCF</name> 900 <description>Single Collision Frames.</description> 901 <addressOffset>0x44</addressOffset> 902 <fields> 903 <field> 904 <name>SCF</name> 905 <description>Single Collision Frames. A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no underrun.</description> 906 <bitOffset>0</bitOffset> 907 <bitWidth>16</bitWidth> 908 <access>read-write</access> 909 </field> 910 </fields> 911 </register> 912 <register> 913 <name>MCF</name> 914 <description>Multiple Collision Frames.</description> 915 <addressOffset>0x48</addressOffset> 916 <fields> 917 <field> 918 <name>MCF</name> 919 <description>Multiple Collision Frames. A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no underrun and not too many retries.</description> 920 <bitOffset>0</bitOffset> 921 <bitWidth>16</bitWidth> 922 <access>read-write</access> 923 </field> 924 </fields> 925 </register> 926 <register> 927 <name>FROK</name> 928 <description>Fames Received OK.</description> 929 <addressOffset>0x4C</addressOffset> 930 <fields> 931 <field> 932 <name>FROK</name> 933 <description>Frames Received OK. A 24-bit register counting the number of good packets received</description> 934 <bitOffset>0</bitOffset> 935 <bitWidth>24</bitWidth> 936 <access>read-write</access> 937 </field> 938 </fields> 939 </register> 940 <register> 941 <name>FCS_ERR</name> 942 <description>Frame Check Sequence Errors.</description> 943 <addressOffset>0x50</addressOffset> 944 <fields> 945 <field> 946 <name>FCSERR</name> 947 <description>Frame Check Sequence Errors.</description> 948 <bitOffset>0</bitOffset> 949 <bitWidth>8</bitWidth> 950 <access>read-write</access> 951 </field> 952 </fields> 953 </register> 954 <register> 955 <name>ALGN_ERR</name> 956 <description>Alignment Errors.</description> 957 <addressOffset>0x54</addressOffset> 958 <fields> 959 <field> 960 <name>ALGNERR</name> 961 <description>Alignment Errors. </description> 962 <bitOffset>0</bitOffset> 963 <bitWidth>8</bitWidth> 964 <access>read-write</access> 965 </field> 966 </fields> 967 </register> 968 <register> 969 <name>DFTXF</name> 970 <description>Deferred Transmission Frames.</description> 971 <addressOffset>0x58</addressOffset> 972 <fields> 973 <field> 974 <name>DFTXF</name> 975 <description>Deferred Transmission Frames. A 16-bit register counting the number of packets experiencing deferral due to carrier sense being active on their first attempt at transmission</description> 976 <bitOffset>0</bitOffset> 977 <bitWidth>16</bitWidth> 978 <access>read-write</access> 979 </field> 980 </fields> 981 </register> 982 <register> 983 <name>LC</name> 984 <description>Late Collisions.</description> 985 <addressOffset>0x5C</addressOffset> 986 <fields> 987 <field> 988 <name>LC</name> 989 <description>Late Collisions. An 8-bit register counting the number of packets that experience a collision after the slot time (512 bits) has expired.</description> 990 <bitOffset>0</bitOffset> 991 <bitWidth>8</bitWidth> 992 <access>read-write</access> 993 </field> 994 </fields> 995 </register> 996 <register> 997 <name>EC</name> 998 <description>Excessive Collisions.</description> 999 <addressOffset>0x60</addressOffset> 1000 <fields> 1001 <field> 1002 <name>EC</name> 1003 <description>Excessive Collisions. An 8-bit register counting the number of packets that failed to be transmitted because they experienced 16 collisions.</description> 1004 <bitOffset>0</bitOffset> 1005 <bitWidth>8</bitWidth> 1006 <access>read-write</access> 1007 </field> 1008 </fields> 1009 </register> 1010 <register> 1011 <name>TUR_ERR</name> 1012 <description>Transmit Underrun Errors.</description> 1013 <addressOffset>0x64</addressOffset> 1014 <fields> 1015 <field> 1016 <name>TURERR</name> 1017 <description>Transmit Underrun Error. An 8-bit register counting the number of packets not transmitted due to a transmit FIFO underrun.</description> 1018 <bitOffset>0</bitOffset> 1019 <bitWidth>8</bitWidth> 1020 <access>read-write</access> 1021 </field> 1022 </fields> 1023 </register> 1024 <register> 1025 <name>CS_ERR</name> 1026 <description>Carrier Sense Errors.</description> 1027 <addressOffset>0x68</addressOffset> 1028 <fields> 1029 <field> 1030 <name>CSERR</name> 1031 <description>An 8-bit register counting the number of packets transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit packet without collision (no underrun).</description> 1032 <bitOffset>0</bitOffset> 1033 <bitWidth>8</bitWidth> 1034 <access>read-write</access> 1035 </field> 1036 </fields> 1037 </register> 1038 <register> 1039 <name>RR_ERR</name> 1040 <description>Receive Resource Errors.</description> 1041 <addressOffset>0x6C</addressOffset> 1042 <fields> 1043 <field> 1044 <name>RRERR</name> 1045 <description>Receive Resource Errors. A 16 bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available.</description> 1046 <bitOffset>0</bitOffset> 1047 <bitWidth>16</bitWidth> 1048 <access>read-write</access> 1049 </field> 1050 </fields> 1051 </register> 1052 <register> 1053 <name>ROR_ERR</name> 1054 <description>Receive Overrun Errors.</description> 1055 <addressOffset>0x70</addressOffset> 1056 <fields> 1057 <field> 1058 <name>RORERR</name> 1059 <description>Receive Overruns. An 8 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun.</description> 1060 <bitOffset>0</bitOffset> 1061 <bitWidth>8</bitWidth> 1062 <access>read-write</access> 1063 </field> 1064 </fields> 1065 </register> 1066 <register> 1067 <name>RS_ERR</name> 1068 <description>Receive Symbol Errors.</description> 1069 <addressOffset>0x74</addressOffset> 1070 <fields> 1071 <field> 1072 <name>RSERR</name> 1073 <description>Receive Symbol Errors. An 8-bit register counting the number of packets that had EMAC_RXER asserted during reception.</description> 1074 <bitOffset>0</bitOffset> 1075 <bitWidth>8</bitWidth> 1076 <access>read-write</access> 1077 </field> 1078 </fields> 1079 </register> 1080 <register> 1081 <name>EL_ERR</name> 1082 <description>Excessive Length Errors.</description> 1083 <addressOffset>0x78</addressOffset> 1084 <fields> 1085 <field> 1086 <name>ELERR</name> 1087 <description>Excessive Length Errors. An 8-bit register counting the number of packets received exceeding 1518 bytes in length (1536 if RXFR is set in the MAC_CFG register;</description> 1088 <bitOffset>0</bitOffset> 1089 <bitWidth>8</bitWidth> 1090 <access>read-write</access> 1091 </field> 1092 </fields> 1093 </register> 1094 <register> 1095 <name>RJ</name> 1096 <description>Receive Jabber.</description> 1097 <addressOffset>0x7C</addressOffset> 1098 <fields> 1099 <field> 1100 <name>RJERR</name> 1101 <description>Receive Jabbers. An 8-bit register counting the number of packets received exceeding 1518 bytes in length (1536 if RXFR is set in the MAC_CFG register; </description> 1102 <bitOffset>0</bitOffset> 1103 <bitWidth>8</bitWidth> 1104 <access>read-write</access> 1105 </field> 1106 </fields> 1107 </register> 1108 <register> 1109 <name>USF</name> 1110 <description>Undersize Frames.</description> 1111 <addressOffset>0x80</addressOffset> 1112 <fields> 1113 <field> 1114 <name>USF</name> 1115 <description>Undersize Frames. An 8-bit register counting the number of packets received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error.</description> 1116 <bitOffset>0</bitOffset> 1117 <bitWidth>8</bitWidth> 1118 <access>read-write</access> 1119 </field> 1120 </fields> 1121 </register> 1122 <register> 1123 <name>SQE_ERR</name> 1124 <description>SQE Test Errors.</description> 1125 <addressOffset>0x84</addressOffset> 1126 <fields> 1127 <field> 1128 <name>SQEERR</name> 1129 <description>SQE Test Errors. An 8-bit register counting the number of packets where collision was not asserted within 96 bit times (an interframe gap) of EMAC_TXEN being deasserted in half duplex mode.</description> 1130 <bitOffset>0</bitOffset> 1131 <bitWidth>8</bitWidth> 1132 <access>read-write</access> 1133 </field> 1134 </fields> 1135 </register> 1136 <register> 1137 <name>RLFM</name> 1138 <description>Received Length Field Mismatch.</description> 1139 <addressOffset>0x88</addressOffset> 1140 <fields> 1141 <field> 1142 <name>RLFM</name> 1143 <description>Receive length field mismatch </description> 1144 <bitOffset>0</bitOffset> 1145 <bitWidth>8</bitWidth> 1146 <access>read-write</access> 1147 </field> 1148 </fields> 1149 </register> 1150 <register> 1151 <name>TPF</name> 1152 <description>Transmitted Pause Frames.</description> 1153 <addressOffset>0x8C</addressOffset> 1154 <fields> 1155 <field> 1156 <name>TPF</name> 1157 <description>Transmitted Pause Frames. A 16-bit register counting the number of pause packets transmitted.</description> 1158 <bitOffset>0</bitOffset> 1159 <bitWidth>16</bitWidth> 1160 <access>read-write</access> 1161 </field> 1162 </fields> 1163 </register> 1164 <register> 1165 <name>HASHL</name> 1166 <description>Hash Register Bottom [31:0].</description> 1167 <addressOffset>0x90</addressOffset> 1168 <fields> 1169 <field> 1170 <name>HASH</name> 1171 <description>Bits 31:0 of the hash address register. See Hash Addressing</description> 1172 <bitOffset>0</bitOffset> 1173 <bitWidth>32</bitWidth> 1174 <access>read-write</access> 1175 </field> 1176 </fields> 1177 </register> 1178 <register> 1179 <name>HASHH</name> 1180 <description>Hash Register top [63:32].</description> 1181 <addressOffset>0x94</addressOffset> 1182 <fields> 1183 <field> 1184 <name>HASH</name> 1185 <description>Bits 63:32 of the hash address register. See Hash Addressing</description> 1186 <bitOffset>0</bitOffset> 1187 <bitWidth>32</bitWidth> 1188 <access>read-write</access> 1189 </field> 1190 </fields> 1191 </register> 1192 <register> 1193 <name>SA1L</name> 1194 <description>Specific Address 1 Bottom.</description> 1195 <addressOffset>0x98</addressOffset> 1196 <fields> 1197 <field> 1198 <name>ADDR</name> 1199 <description>MAC Specific Address 1 [31:0]. Least significant bits of the MAC specific address 1, i.e. bits 31:0. This field is used for transmission of pause packets</description> 1200 <bitOffset>0</bitOffset> 1201 <bitWidth>32</bitWidth> 1202 <access>read-write</access> 1203 </field> 1204 </fields> 1205 </register> 1206 <register> 1207 <name>SA1H</name> 1208 <description>Specific Address 1 Top.</description> 1209 <addressOffset>0x9C</addressOffset> 1210 <fields> 1211 <field> 1212 <name>ADDR</name> 1213 <description>MAC Specific Address 1 [47:32]. Most significant bits of the MAC specific address 1, i.e. bits 47:32.</description> 1214 <bitOffset>0</bitOffset> 1215 <bitWidth>16</bitWidth> 1216 <access>read-write</access> 1217 </field> 1218 </fields> 1219 </register> 1220 <register> 1221 <name>SA2L</name> 1222 <description>Specific Address 2 Bottom.</description> 1223 <addressOffset>0xA0</addressOffset> 1224 <fields> 1225 <field> 1226 <name>ADDR</name> 1227 <description>MAC Specific Address 2 [31:0]. Least significant bits of the MAC specific address 2, i.e. bits 31:0. This field is used for transmission of pause packets</description> 1228 <bitOffset>0</bitOffset> 1229 <bitWidth>32</bitWidth> 1230 <access>read-write</access> 1231 </field> 1232 </fields> 1233 </register> 1234 <register> 1235 <name>SA2H</name> 1236 <description>Specific Address 2 Top.</description> 1237 <addressOffset>0xA4</addressOffset> 1238 <fields> 1239 <field> 1240 <name>ADDR</name> 1241 <description>MAC Specific Address 2 [47:32]. Most significant bits of the MAC specific address 2, i.e. bits 47:32.</description> 1242 <bitOffset>0</bitOffset> 1243 <bitWidth>16</bitWidth> 1244 <access>read-write</access> 1245 </field> 1246 </fields> 1247 </register> 1248 <register> 1249 <name>SA3L</name> 1250 <description>Specific Address 3 Bottom.</description> 1251 <addressOffset>0xA8</addressOffset> 1252 <fields> 1253 <field> 1254 <name>ADDR</name> 1255 <description>MAC Specific Address 3 [31:0]. Least significant bits of the MAC specific address 3, i.e. bits 31:0. This field is used for transmission of pause packets</description> 1256 <bitOffset>0</bitOffset> 1257 <bitWidth>32</bitWidth> 1258 <access>read-write</access> 1259 </field> 1260 </fields> 1261 </register> 1262 <register> 1263 <name>SA3H</name> 1264 <description>Specific Address 3 Top.</description> 1265 <addressOffset>0xAC</addressOffset> 1266 <fields> 1267 <field> 1268 <name>ADDR</name> 1269 <description>MAC Specific Address 3 [47:32]. Most significant bits of the MAC specific address 3, i.e. bits 47:32.</description> 1270 <bitOffset>0</bitOffset> 1271 <bitWidth>16</bitWidth> 1272 <access>read-write</access> 1273 </field> 1274 </fields> 1275 </register> 1276 <register> 1277 <name>SA4L</name> 1278 <description>Specific Address 4 Bottom.</description> 1279 <addressOffset>0xB0</addressOffset> 1280 <fields> 1281 <field> 1282 <name>ADDR</name> 1283 <description>MAC Specific Address 4 [31:0]. Least significant bits of the MAC specific address 4, i.e. bits 31:0. This field is used for transmission of pause packets</description> 1284 <bitOffset>0</bitOffset> 1285 <bitWidth>32</bitWidth> 1286 <access>read-write</access> 1287 </field> 1288 </fields> 1289 </register> 1290 <register> 1291 <name>SA4H</name> 1292 <description>Specific Address 4 Top.</description> 1293 <addressOffset>0xB4</addressOffset> 1294 <fields> 1295 <field> 1296 <name>ADDR</name> 1297 <description>MAC Specific Address 4 [47:32]. Most significant bits of the MAC specific address 4, i.e. bits 47:32.</description> 1298 <bitOffset>0</bitOffset> 1299 <bitWidth>16</bitWidth> 1300 <access>read-write</access> 1301 </field> 1302 </fields> 1303 </register> 1304 <register> 1305 <name>TID_CK</name> 1306 <description>Type ID Checking.</description> 1307 <addressOffset>0xB8</addressOffset> 1308 <fields> 1309 <field> 1310 <name>TID</name> 1311 <description>Type ID Checking. For use in comparisons with received frames TypeID/Length field.</description> 1312 <bitOffset>0</bitOffset> 1313 <bitWidth>16</bitWidth> 1314 <access>read-write</access> 1315 </field> 1316 </fields> 1317 </register> 1318 <register> 1319 <name>TPQ</name> 1320 <description>Transmit Pause Quantum.</description> 1321 <addressOffset>0xBC</addressOffset> 1322 <fields> 1323 <field> 1324 <name>TPQ</name> 1325 <description>Transmit Pause Quantum. Used in hardware generation of transmitted pause packets as value for pause quantum</description> 1326 <bitOffset>0</bitOffset> 1327 <bitWidth>16</bitWidth> 1328 <access>read-write</access> 1329 </field> 1330 </fields> 1331 </register> 1332 <register> 1333 <name>REV</name> 1334 <description>Revision register.</description> 1335 <addressOffset>0xFC</addressOffset> 1336 <access>read-only</access> 1337 <fields> 1338 <field> 1339 <name>REV</name> 1340 <description>Revision Reference. Fixed two byte value specific to revision of design.</description> 1341 <bitOffset>0</bitOffset> 1342 <bitWidth>16</bitWidth> 1343 <access>read-only</access> 1344 </field> 1345 <field> 1346 <name>PART</name> 1347 <description>Part Reference. For Ethernet MAC design, this is fixed at 0x01.</description> 1348 <bitOffset>16</bitOffset> 1349 <bitWidth>16</bitWidth> 1350 <access>read-only</access> 1351 </field> 1352 </fields> 1353 </register> 1354 </registers> 1355 </peripheral> 1356 <!-- EMAC: 10/100 Ethernet MAC --> 1357</device>
