1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>DMA</name> 5 <description>DMA Controller Fully programmable, chaining capable DMA channels.</description> 6 <baseAddress>0x40028000</baseAddress> 7 <size>32</size> 8 <addressBlock> 9 <offset>0x00</offset> 10 <size>0x1000</size> 11 <usage>registers</usage> 12 </addressBlock> 13 <interrupt> 14 <name>DMA0</name> 15 <value>28</value> 16 </interrupt> 17 <interrupt> 18 <name>DMA1</name> 19 <value>29</value> 20 </interrupt> 21 <interrupt> 22 <name>DMA2</name> 23 <value>30</value> 24 </interrupt> 25 <interrupt> 26 <name>DMA3</name> 27 <value>31</value> 28 </interrupt> 29 <registers> 30 <register> 31 <name>INT_EN</name> 32 <description>DMA Control Register.</description> 33 <addressOffset>0x000</addressOffset> 34 <fields> 35 <field> 36 <name>CHIEN</name> 37 <description>Channel Interrupt Enable.</description> 38 <bitOffset>0</bitOffset> 39 <bitWidth>4</bitWidth> 40 <enumeratedValues> 41 <enumeratedValue> 42 <name>dis</name> 43 <description>Disable.</description> 44 <value>0</value> 45 </enumeratedValue> 46 <enumeratedValue> 47 <name>en</name> 48 <description>Enable.</description> 49 <value>1</value> 50 </enumeratedValue> 51 </enumeratedValues> 52 </field> 53 </fields> 54 </register> 55 <register> 56 <name>INT_FL</name> 57 <description>DMA Interrupt Register.</description> 58 <addressOffset>0x004</addressOffset> 59 <access>read-only</access> 60 <fields> 61 <field> 62 <name>IPEND</name> 63 <description>Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.</description> 64 <bitOffset>0</bitOffset> 65 <bitWidth>4</bitWidth> 66 <enumeratedValues> 67 <name>ch_ipend_enum</name> 68 <enumeratedValue> 69 <name>inactive</name> 70 <description>No interrupt is pending.</description> 71 <value>0</value> 72 </enumeratedValue> 73 <enumeratedValue> 74 <name>pending</name> 75 <description>An interrupt is pending.</description> 76 <value>1</value> 77 </enumeratedValue> 78 </enumeratedValues> 79 </field> 80 </fields> 81 </register> 82 <cluster> 83 <dim>4</dim> 84 <dimIncrement>0x20</dimIncrement> 85 <name>CH[%s]</name> 86 <description>DMA Channel registers.</description> 87 <headerStructName>dma_ch</headerStructName> 88 <addressOffset>0x100</addressOffset> 89 <access>read-write</access> 90 <register> 91 <name>CFG</name> 92 <description>DMA Channel Configuration Register.</description> 93 <addressOffset>0x000</addressOffset> 94 <fields> 95 <field> 96 <name>CHEN</name> 97 <description>Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.</description> 98 <bitOffset>0</bitOffset> 99 <bitWidth>1</bitWidth> 100 <enumeratedValues> 101 <enumeratedValue> 102 <name>dis</name> 103 <description>Disable.</description> 104 <value>0</value> 105 </enumeratedValue> 106 <enumeratedValue> 107 <name>en</name> 108 <description>Enable.</description> 109 <value>1</value> 110 </enumeratedValue> 111 </enumeratedValues> 112 </field> 113 <field> 114 <name>RLDEN</name> 115 <description>Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.</description> 116 <bitOffset>1</bitOffset> 117 <bitWidth>1</bitWidth> 118 <enumeratedValues> 119 <enumeratedValue> 120 <name>dis</name> 121 <description>Disable.</description> 122 <value>0</value> 123 </enumeratedValue> 124 <enumeratedValue> 125 <name>en</name> 126 <description>Enable.</description> 127 <value>1</value> 128 </enumeratedValue> 129 </enumeratedValues> 130 </field> 131 <field> 132 <name>PRI</name> 133 <description>DMA Priority.</description> 134 <bitOffset>2</bitOffset> 135 <bitWidth>2</bitWidth> 136 <enumeratedValues> 137 <enumeratedValue> 138 <name>high</name> 139 <description>Highest Priority.</description> 140 <value>0</value> 141 </enumeratedValue> 142 <enumeratedValue> 143 <name>medHigh</name> 144 <description>Medium High Priority.</description> 145 <value>1</value> 146 </enumeratedValue> 147 <enumeratedValue> 148 <name>medLow</name> 149 <description>Medium Low Priority.</description> 150 <value>2</value> 151 </enumeratedValue> 152 <enumeratedValue> 153 <name>low</name> 154 <description>Lowest Priority.</description> 155 <value>3</value> 156 </enumeratedValue> 157 </enumeratedValues> 158 </field> 159 <field> 160 <name>REQSEL</name> 161 <description>Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.</description> 162 <bitOffset>4</bitOffset> 163 <bitWidth>6</bitWidth> 164 <enumeratedValues> 165 <enumeratedValue> 166 <name>MEMTOMEM</name> 167 <description>Memory To Memory</description> 168 <value>0x00</value> 169 </enumeratedValue> 170 <enumeratedValue> 171 <name>SPI0RX</name> 172 <description>SPI0 RX</description> 173 <value>0x01</value> 174 </enumeratedValue> 175 <enumeratedValue> 176 <name>SPI1RX</name> 177 <description>SPI1 RX</description> 178 <value>0x02</value> 179 </enumeratedValue> 180 <enumeratedValue> 181 <name>UART0RX</name> 182 <description>UART0 RX</description> 183 <value>0x04</value> 184 </enumeratedValue> 185 <enumeratedValue> 186 <name>UART1RX</name> 187 <description>UART1 RX</description> 188 <value>0x05</value> 189 </enumeratedValue> 190 <enumeratedValue> 191 <name>I2C0RX</name> 192 <description>I2C0 RX</description> 193 <value>0x07</value> 194 </enumeratedValue> 195 <enumeratedValue> 196 <name>I2C1RX</name> 197 <description>I2C1 RX</description> 198 <value>0x08</value> 199 </enumeratedValue> 200 <enumeratedValue> 201 <name>SPI0TX</name> 202 <description>SPI0 TX</description> 203 <value>0x21</value> 204 </enumeratedValue> 205 <enumeratedValue> 206 <name>SPI1TX</name> 207 <description>SPI1 TX</description> 208 <value>0x22</value> 209 </enumeratedValue> 210 <enumeratedValue> 211 <name>UART0TX</name> 212 <description>UART0 TX</description> 213 <value>0x24</value> 214 </enumeratedValue> 215 <enumeratedValue> 216 <name>UART1TX</name> 217 <description>UART1 TX</description> 218 <value>0x25</value> 219 </enumeratedValue> 220 <enumeratedValue> 221 <name>I2C0TX</name> 222 <description>I2C0 TX</description> 223 <value>0x27</value> 224 </enumeratedValue> 225 <enumeratedValue> 226 <name>I2C1TX</name> 227 <description>I2C1 TX</description> 228 <value>0x28</value> 229 </enumeratedValue> 230 </enumeratedValues> 231 </field> 232 <field> 233 <name>REQWAIT</name> 234 <description>Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.</description> 235 <bitOffset>10</bitOffset> 236 <bitWidth>1</bitWidth> 237 <enumeratedValues> 238 <enumeratedValue> 239 <name>dis</name> 240 <description>Disable.</description> 241 <value>0</value> 242 </enumeratedValue> 243 <enumeratedValue> 244 <name>en</name> 245 <description>Enable.</description> 246 <value>1</value> 247 </enumeratedValue> 248 </enumeratedValues> 249 </field> 250 <field> 251 <name>TOSEL</name> 252 <description>Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.</description> 253 <bitOffset>11</bitOffset> 254 <bitWidth>3</bitWidth> 255 <enumeratedValues> 256 <enumeratedValue> 257 <name>to4</name> 258 <description>Timeout of 3 to 4 prescale clocks.</description> 259 <value>0</value> 260 </enumeratedValue> 261 <enumeratedValue> 262 <name>to8</name> 263 <description>Timeout of 7 to 8 prescale clocks.</description> 264 <value>1</value> 265 </enumeratedValue> 266 <enumeratedValue> 267 <name>to16</name> 268 <description>Timeout of 15 to 16 prescale clocks.</description> 269 <value>2</value> 270 </enumeratedValue> 271 <enumeratedValue> 272 <name>to32</name> 273 <description>Timeout of 31 to 32 prescale clocks.</description> 274 <value>3</value> 275 </enumeratedValue> 276 <enumeratedValue> 277 <name>to64</name> 278 <description>Timeout of 63 to 64 prescale clocks.</description> 279 <value>4</value> 280 </enumeratedValue> 281 <enumeratedValue> 282 <name>to128</name> 283 <description>Timeout of 127 to 128 prescale clocks.</description> 284 <value>5</value> 285 </enumeratedValue> 286 <enumeratedValue> 287 <name>to256</name> 288 <description>Timeout of 255 to 256 prescale clocks.</description> 289 <value>6</value> 290 </enumeratedValue> 291 <enumeratedValue> 292 <name>to512</name> 293 <description>Timeout of 511 to 512 prescale clocks.</description> 294 <value>7</value> 295 </enumeratedValue> 296 </enumeratedValues> 297 </field> 298 <field> 299 <name>PSSEL</name> 300 <description>Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.</description> 301 <bitOffset>14</bitOffset> 302 <bitWidth>2</bitWidth> 303 <enumeratedValues> 304 <enumeratedValue> 305 <name>dis</name> 306 <description>Disable timer.</description> 307 <value>0</value> 308 </enumeratedValue> 309 <enumeratedValue> 310 <name>div256</name> 311 <description>hclk / 256.</description> 312 <value>1</value> 313 </enumeratedValue> 314 <enumeratedValue> 315 <name>div64k</name> 316 <description>hclk / 64k.</description> 317 <value>2</value> 318 </enumeratedValue> 319 <enumeratedValue> 320 <name>div16M</name> 321 <description>hclk / 16M.</description> 322 <value>3</value> 323 </enumeratedValue> 324 </enumeratedValues> 325 </field> 326 <field> 327 <name>SRCWD</name> 328 <description>Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.</description> 329 <bitOffset>16</bitOffset> 330 <bitWidth>2</bitWidth> 331 <enumeratedValues> 332 <enumeratedValue> 333 <name>byte</name> 334 <description>Byte.</description> 335 <value>0</value> 336 </enumeratedValue> 337 <enumeratedValue> 338 <name>halfWord</name> 339 <description>Halfword.</description> 340 <value>1</value> 341 </enumeratedValue> 342 <enumeratedValue> 343 <name>word</name> 344 <description>Word.</description> 345 <value>2</value> 346 </enumeratedValue> 347 </enumeratedValues> 348 </field> 349 <field> 350 <name>SRCINC</name> 351 <description>Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.</description> 352 <bitOffset>18</bitOffset> 353 <bitWidth>1</bitWidth> 354 <enumeratedValues> 355 <enumeratedValue> 356 <name>dis</name> 357 <description>Disable.</description> 358 <value>0</value> 359 </enumeratedValue> 360 <enumeratedValue> 361 <name>en</name> 362 <description>Enable.</description> 363 <value>1</value> 364 </enumeratedValue> 365 </enumeratedValues> 366 </field> 367 <field> 368 <name>DSTWD</name> 369 <description>Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).</description> 370 <bitOffset>20</bitOffset> 371 <bitWidth>2</bitWidth> 372 <enumeratedValues> 373 <enumeratedValue> 374 <name>byte</name> 375 <description>Byte.</description> 376 <value>0</value> 377 </enumeratedValue> 378 <enumeratedValue> 379 <name>halfWord</name> 380 <description>Halfword.</description> 381 <value>1</value> 382 </enumeratedValue> 383 <enumeratedValue> 384 <name>word</name> 385 <description>Word.</description> 386 <value>2</value> 387 </enumeratedValue> 388 </enumeratedValues> 389 </field> 390 <field> 391 <name>DSTINC</name> 392 <description>Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.</description> 393 <bitOffset>22</bitOffset> 394 <bitWidth>1</bitWidth> 395 <enumeratedValues> 396 <enumeratedValue> 397 <name>dis</name> 398 <description>Disable.</description> 399 <value>0</value> 400 </enumeratedValue> 401 <enumeratedValue> 402 <name>en</name> 403 <description>Enable.</description> 404 <value>1</value> 405 </enumeratedValue> 406 </enumeratedValues> 407 </field> 408 <field> 409 <name>BRST</name> 410 <description>Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.</description> 411 <bitOffset>24</bitOffset> 412 <bitWidth>5</bitWidth> 413 </field> 414 <field> 415 <name>CHDIEN</name> 416 <description>Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.</description> 417 <bitOffset>30</bitOffset> 418 <bitWidth>1</bitWidth> 419 <enumeratedValues> 420 <enumeratedValue> 421 <name>dis</name> 422 <description>Disable.</description> 423 <value>0</value> 424 </enumeratedValue> 425 <enumeratedValue> 426 <name>en</name> 427 <description>Enable.</description> 428 <value>1</value> 429 </enumeratedValue> 430 </enumeratedValues> 431 </field> 432 <field> 433 <name>CTZIEN</name> 434 <description>Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.</description> 435 <bitOffset>31</bitOffset> 436 <bitWidth>1</bitWidth> 437 <enumeratedValues> 438 <enumeratedValue> 439 <name>dis</name> 440 <description>Disable.</description> 441 <value>0</value> 442 </enumeratedValue> 443 <enumeratedValue> 444 <name>en</name> 445 <description>Enable.</description> 446 <value>1</value> 447 </enumeratedValue> 448 </enumeratedValues> 449 </field> 450 </fields> 451 </register> 452 <register> 453 <name>STAT</name> 454 <description>DMA Channel Status Register.</description> 455 <addressOffset>0x004</addressOffset> 456 <fields> 457 <field> 458 <name>CH_ST</name> 459 <description>Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).</description> 460 <bitOffset>0</bitOffset> 461 <bitWidth>1</bitWidth> 462 <access>read-only</access> 463 <enumeratedValues> 464 <enumeratedValue> 465 <name>dis</name> 466 <description>Disable.</description> 467 <value>0</value> 468 </enumeratedValue> 469 <enumeratedValue> 470 <name>en</name> 471 <description>Enable.</description> 472 <value>1</value> 473 </enumeratedValue> 474 </enumeratedValues> 475 </field> 476 <field> 477 <name>IPEND</name> 478 <description>Channel Interrupt.</description> 479 <bitOffset>1</bitOffset> 480 <bitWidth>1</bitWidth> 481 <access>read-only</access> 482 <enumeratedValues> 483 <enumeratedValue> 484 <name>inactive</name> 485 <description>No interrupt is pending.</description> 486 <value>0</value> 487 </enumeratedValue> 488 <enumeratedValue> 489 <name>pending</name> 490 <description>An interrupt is pending.</description> 491 <value>1</value> 492 </enumeratedValue> 493 </enumeratedValues> 494 </field> 495 <field> 496 <name>CTZ_ST</name> 497 <description>Count-to-Zero (CTZ) Status</description> 498 <bitOffset>2</bitOffset> 499 <bitWidth>1</bitWidth> 500 <modifiedWriteValues>oneToClear</modifiedWriteValues> 501 <enumeratedValues> 502 <name>ctz_st_enum_rd</name> 503 <usage>read</usage> 504 <enumeratedValue> 505 <name>noEvent</name> 506 <description>The event has not occurred.</description> 507 <value>0</value> 508 </enumeratedValue> 509 <enumeratedValue> 510 <name>occurred</name> 511 <description>The event has occurred.</description> 512 <value>1</value> 513 </enumeratedValue> 514 </enumeratedValues> 515 <enumeratedValues> 516 <name>ctz_st_enum_wr</name> 517 <usage>write</usage> 518 <enumeratedValue> 519 <name>Clear</name> 520 <description>Clears the interrupt flag</description> 521 <value>1</value> 522 </enumeratedValue> 523 </enumeratedValues> 524 </field> 525 <field> 526 <name>RLD_ST</name> 527 <description>Reload Status.</description> 528 <bitOffset>3</bitOffset> 529 <bitWidth>1</bitWidth> 530 <modifiedWriteValues>oneToClear</modifiedWriteValues> 531 <enumeratedValues> 532 <usage>read</usage> 533 <enumeratedValue> 534 <name>noEvent</name> 535 <description>The event has not occurred.</description> 536 <value>0</value> 537 </enumeratedValue> 538 <enumeratedValue> 539 <name>occurred</name> 540 <description>The event has occurred.</description> 541 <value>1</value> 542 </enumeratedValue> 543 </enumeratedValues> 544 <enumeratedValues> 545 <usage>write</usage> 546 <enumeratedValue> 547 <name>Clear</name> 548 <description>Clears the interrupt flag</description> 549 <value>1</value> 550 </enumeratedValue> 551 </enumeratedValues> 552 </field> 553 <field> 554 <name>BUS_ERR</name> 555 <description>Bus Error. Indicates that an AHB abort was received and the channel has been disabled.</description> 556 <bitOffset>4</bitOffset> 557 <bitWidth>1</bitWidth> 558 <modifiedWriteValues>oneToClear</modifiedWriteValues> 559 <enumeratedValues> 560 <usage>read</usage> 561 <enumeratedValue> 562 <name>noEvent</name> 563 <description>The event has not occurred.</description> 564 <value>0</value> 565 </enumeratedValue> 566 <enumeratedValue> 567 <name>occurred</name> 568 <description>The event has occurred.</description> 569 <value>1</value> 570 </enumeratedValue> 571 </enumeratedValues> 572 <enumeratedValues> 573 <usage>write</usage> 574 <enumeratedValue> 575 <name>Clear</name> 576 <description>Clears the interrupt flag</description> 577 <value>1</value> 578 </enumeratedValue> 579 </enumeratedValues> 580 </field> 581 <field> 582 <name>TO_ST</name> 583 <description>Time-Out Status.</description> 584 <bitOffset>6</bitOffset> 585 <bitWidth>1</bitWidth> 586 <modifiedWriteValues>oneToClear</modifiedWriteValues> 587 <enumeratedValues> 588 <usage>read</usage> 589 <enumeratedValue> 590 <name>noEvent</name> 591 <description>The event has not occurred.</description> 592 <value>0</value> 593 </enumeratedValue> 594 <enumeratedValue> 595 <name>occurred</name> 596 <description>The event has occurred.</description> 597 <value>1</value> 598 </enumeratedValue> 599 </enumeratedValues> 600 <enumeratedValues> 601 <usage>write</usage> 602 <enumeratedValue> 603 <name>Clear</name> 604 <description>Clears the interrupt flag</description> 605 <value>1</value> 606 </enumeratedValue> 607 </enumeratedValues> 608 </field> 609 </fields> 610 </register> 611 <register> 612 <name>SRC</name> 613 <description>Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.</description> 614 <addressOffset>0x008</addressOffset> 615 <fields> 616 <field> 617 <name>SRC</name> 618 <bitOffset>0</bitOffset> 619 <bitWidth>32</bitWidth> 620 </field> 621 </fields> 622 </register> 623 <register> 624 <name>DST</name> 625 <description>Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.</description> 626 <addressOffset>0x00C</addressOffset> 627 <fields> 628 <field> 629 <name>DST</name> 630 <bitOffset>0</bitOffset> 631 <bitWidth>32</bitWidth> 632 </field> 633 </fields> 634 </register> 635 <register> 636 <name>CNT</name> 637 <description>DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.</description> 638 <addressOffset>0x010</addressOffset> 639 <fields> 640 <field> 641 <name>CNT</name> 642 <description>DMA Counter.</description> 643 <bitOffset>0</bitOffset> 644 <bitWidth>24</bitWidth> 645 </field> 646 </fields> 647 </register> 648 <register> 649 <name>SRC_RLD</name> 650 <description>Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.</description> 651 <addressOffset>0x014</addressOffset> 652 <fields> 653 <field> 654 <name>SRC_RLD</name> 655 <description>Source Address Reload Value.</description> 656 <bitOffset>0</bitOffset> 657 <bitWidth>31</bitWidth> 658 </field> 659 </fields> 660 </register> 661 <register> 662 <name>DST_RLD</name> 663 <description>Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.</description> 664 <addressOffset>0x018</addressOffset> 665 <fields> 666 <field> 667 <name>DST_RLD</name> 668 <description>Destination Address Reload Value.</description> 669 <bitOffset>0</bitOffset> 670 <bitWidth>31</bitWidth> 671 </field> 672 </fields> 673 </register> 674 <register> 675 <name>CNT_RLD</name> 676 <description>DMA Channel Count Reload Register.</description> 677 <addressOffset>0x01C</addressOffset> 678 <fields> 679 <field> 680 <name>CNT_RLD</name> 681 <description>Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.</description> 682 <bitOffset>0</bitOffset> 683 <bitWidth>24</bitWidth> 684 </field> 685 <field> 686 <name>RLDEN</name> 687 <description>Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.</description> 688 <bitOffset>31</bitOffset> 689 <bitWidth>1</bitWidth> 690 <enumeratedValues> 691 <enumeratedValue> 692 <name>dis</name> 693 <description>Disable.</description> 694 <value>0</value> 695 </enumeratedValue> 696 <enumeratedValue> 697 <name>en</name> 698 <description>Enable.</description> 699 <value>1</value> 700 </enumeratedValue> 701 </enumeratedValues> 702 </field> 703 </fields> 704 </register> 705 </cluster> 706 </registers> 707 </peripheral> 708 <!-- DMA: Direct Memory Access Controller Fully Programable --> 709</device>
