1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>CTB</name> 5 <description>The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security.</description> 6 <baseAddress>0x40001000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>Crypto_Engine</name> 14 <description>Crypto Engine interrupt.</description> 15 <value>27</value> 16 </interrupt> 17 <registers> 18 <register> 19 <name>CTRL</name> 20 <description>Crypto Control Register.</description> 21 <addressOffset>0x00</addressOffset> 22 <resetValue>0xC0000000</resetValue> 23 <fields> 24 <field> 25 <name>RST</name> 26 <description>Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>1</bitWidth> 29 <enumeratedValues> 30 <name>reset_write</name> 31 <usage>write</usage> 32 <enumeratedValue> 33 <name>reset</name> 34 <description>Starts reset operation.</description> 35 <value>1</value> 36 </enumeratedValue> 37 </enumeratedValues> 38 <enumeratedValues> 39 <name>reset_read</name> 40 <usage>read</usage> 41 <enumeratedValue> 42 <name>reset_done</name> 43 <description>Reset complete.</description> 44 <value>0</value> 45 </enumeratedValue> 46 <enumeratedValue> 47 <name>busy</name> 48 <description>Reset in progress.</description> 49 <value>1</value> 50 </enumeratedValue> 51 </enumeratedValues> 52 </field> 53 <field> 54 <name>INTR</name> 55 <description>Interrupt Enable. Generates an interrupt when done or error set.</description> 56 <bitOffset>1</bitOffset> 57 <bitWidth>1</bitWidth> 58 <enumeratedValues> 59 <enumeratedValue> 60 <name>dis</name> 61 <description>Disable</description> 62 <value>0</value> 63 </enumeratedValue> 64 <enumeratedValue> 65 <name>en</name> 66 <description>Enable</description> 67 <value>1</value> 68 </enumeratedValue> 69 </enumeratedValues> 70 </field> 71 <field> 72 <name>SRC</name> 73 <description>Source Select. This bit selects the hash function and CRC generator input source.</description> 74 <bitOffset>2</bitOffset> 75 <bitWidth>1</bitWidth> 76 <enumeratedValues> 77 <enumeratedValue> 78 <name>inputFIFO</name> 79 <description>Input FIFO</description> 80 <value>0</value> 81 </enumeratedValue> 82 <enumeratedValue> 83 <name>outputFIFO</name> 84 <description>Output FIFO</description> 85 <value>1</value> 86 </enumeratedValue> 87 </enumeratedValues> 88 </field> 89 <field derivedFrom="INTR"> 90 <name>BSO</name> 91 <description>Byte Swap Output. Note. No byte swap will occur if there is not a full word.</description> 92 <bitOffset>4</bitOffset> 93 <bitWidth>1</bitWidth> 94 </field> 95 <field derivedFrom="INTR"> 96 <name>BSI</name> 97 <description>Byte Swap Input. Note. No byte swap will occur if there is not a full word.</description> 98 <bitOffset>5</bitOffset> 99 <bitWidth>1</bitWidth> 100 </field> 101 <field derivedFrom="INTR"> 102 <name>WAIT_EN</name> 103 <description>Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready.</description> 104 <bitOffset>6</bitOffset> 105 <bitWidth>1</bitWidth> 106 </field> 107 <field> 108 <name>WAIT_POL</name> 109 <description>Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state.</description> 110 <bitOffset>7</bitOffset> 111 <bitWidth>1</bitWidth> 112 <enumeratedValues> 113 <enumeratedValue> 114 <name>activeLo</name> 115 <description>Active Low.</description> 116 <value>0</value> 117 </enumeratedValue> 118 <enumeratedValue> 119 <name>activeHi</name> 120 <description>Active High.</description> 121 <value>1</value> 122 </enumeratedValue> 123 </enumeratedValues> 124 </field> 125 <field> 126 <name>WRSRC</name> 127 <description>Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled.</description> 128 <bitOffset>8</bitOffset> 129 <bitWidth>2</bitWidth> 130 <enumeratedValues> 131 <enumeratedValue> 132 <name>none</name> 133 <description>None.</description> 134 <value>0</value> 135 </enumeratedValue> 136 <enumeratedValue> 137 <name>cipherOutput</name> 138 <description>Cipher Output.</description> 139 <value>1</value> 140 </enumeratedValue> 141 <enumeratedValue> 142 <name>readFIFO</name> 143 <description>Read FIFO.</description> 144 <value>2</value> 145 </enumeratedValue> 146 </enumeratedValues> 147 </field> 148 <field> 149 <name>RDSRC</name> 150 <description>Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator.</description> 151 <bitOffset>10</bitOffset> 152 <bitWidth>2</bitWidth> 153 <enumeratedValues> 154 <enumeratedValue> 155 <name>dmaDisabled</name> 156 <description>DMA Disable.</description> 157 <value>0</value> 158 </enumeratedValue> 159 <enumeratedValue> 160 <name>dmaOrApb</name> 161 <description>DMA Or APB.</description> 162 <value>1</value> 163 </enumeratedValue> 164 <enumeratedValue> 165 <name>rng</name> 166 <description>RNG.</description> 167 <value>2</value> 168 </enumeratedValue> 169 </enumeratedValues> 170 </field> 171 <field> 172 <name>FLAG_MODE</name> 173 <description>Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs.</description> 174 <bitOffset>14</bitOffset> 175 <bitWidth>1</bitWidth> 176 <enumeratedValues> 177 <enumeratedValue> 178 <name>unres_wr</name> 179 <description>Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags.</description> 180 <value>0</value> 181 </enumeratedValue> 182 <enumeratedValue> 183 <name>res_wr</name> 184 <description>Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect.</description> 185 <value>1</value> 186 </enumeratedValue> 187 </enumeratedValues> 188 </field> 189 <field> 190 <name>DMADNEMSK</name> 191 <description>DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA.</description> 192 <bitOffset>15</bitOffset> 193 <bitWidth>1</bitWidth> 194 <enumeratedValues> 195 <enumeratedValue> 196 <name>not_used</name> 197 <description>DMA_DONE not used in setting CRYPTO_CTRL.DONE bit.</description> 198 <value>0</value> 199 </enumeratedValue> 200 <enumeratedValue> 201 <name>used</name> 202 <description>DMA_DONE used in setting CRYPTO_CTRL.DONE bit.</description> 203 <value>1</value> 204 </enumeratedValue> 205 </enumeratedValues> 206 </field> 207 <field> 208 <name>DMA_DONE</name> 209 <description>DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation.</description> 210 <bitOffset>24</bitOffset> 211 <bitWidth>1</bitWidth> 212 <enumeratedValues> 213 <enumeratedValue> 214 <name>notDone</name> 215 <description>Not Done.</description> 216 <value>0</value> 217 </enumeratedValue> 218 <enumeratedValue> 219 <name>done</name> 220 <description>Done.</description> 221 <value>1</value> 222 </enumeratedValue> 223 </enumeratedValues> 224 </field> 225 <field derivedFrom="DMA_DONE"> 226 <name>GLS_DONE</name> 227 <description>Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator.</description> 228 <bitOffset>25</bitOffset> 229 <bitWidth>1</bitWidth> 230 </field> 231 <field derivedFrom="DMA_DONE"> 232 <name>HSH_DONE</name> 233 <description>Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation.</description> 234 <bitOffset>26</bitOffset> 235 <bitWidth>1</bitWidth> 236 </field> 237 <field derivedFrom="DMA_DONE"> 238 <name>CPH_DONE</name> 239 <description>Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation.</description> 240 <bitOffset>27</bitOffset> 241 <bitWidth>1</bitWidth> 242 </field> 243 <field> 244 <name>ERR</name> 245 <description>AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block.</description> 246 <bitOffset>29</bitOffset> 247 <bitWidth>1</bitWidth> 248 <access>read-only</access> 249 <enumeratedValues> 250 <enumeratedValue> 251 <name>noError</name> 252 <description>No Error.</description> 253 <value>0</value> 254 </enumeratedValue> 255 <enumeratedValue> 256 <name>error</name> 257 <description>Error.</description> 258 <value>1</value> 259 </enumeratedValue> 260 </enumeratedValues> 261 </field> 262 <field> 263 <name>RDY</name> 264 <description>Ready. Crypto block ready for more data.</description> 265 <bitOffset>30</bitOffset> 266 <bitWidth>1</bitWidth> 267 <access>read-only</access> 268 <enumeratedValues> 269 <enumeratedValue> 270 <name>busy</name> 271 <description>Busy.</description> 272 <value>0</value> 273 </enumeratedValue> 274 <enumeratedValue> 275 <name>ready</name> 276 <description>Ready.</description> 277 <value>1</value> 278 </enumeratedValue> 279 </enumeratedValues> 280 </field> 281 <field derivedFrom="DMA_DONE"> 282 <name>DONE</name> 283 <description>Done. One or more cryptographic calculations complete (logical OR of done flags).</description> 284 <bitOffset>31</bitOffset> 285 <bitWidth>1</bitWidth> 286 <access>read-only</access> 287 </field> 288 </fields> 289 </register> 290 <register> 291 <name>CIPHER_CTRL</name> 292 <description>Cipher Control Register.</description> 293 <addressOffset>0x04</addressOffset> 294 <fields> 295 <field> 296 <name>ENC</name> 297 <description>Encrypt. Select encryption or decryption of input data.</description> 298 <bitOffset>0</bitOffset> 299 <bitWidth>1</bitWidth> 300 <enumeratedValues> 301 <enumeratedValue> 302 <name>ENCRYPT</name> 303 <description>Encrypt.</description> 304 <value>0</value> 305 </enumeratedValue> 306 <enumeratedValue> 307 <name>DECRYPT</name> 308 <description>Decrypt.</description> 309 <value>1</value> 310 </enumeratedValue> 311 </enumeratedValues> 312 </field> 313 <field> 314 <name>KEY</name> 315 <description>Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag.</description> 316 <bitOffset>1</bitOffset> 317 <bitWidth>1</bitWidth> 318 <enumeratedValues> 319 <enumeratedValue> 320 <name>complete</name> 321 <description>No operation/complete.</description> 322 <value>0</value> 323 </enumeratedValue> 324 <enumeratedValue> 325 <name>start</name> 326 <description>Start operation.</description> 327 <value>1</value> 328 </enumeratedValue> 329 </enumeratedValues> 330 </field> 331 <field> 332 <name>SRC</name> 333 <description>Source of Random key.</description> 334 <bitOffset>2</bitOffset> 335 <bitWidth>2</bitWidth> 336 <enumeratedValues> 337 <enumeratedValue> 338 <name>cipherKey</name> 339 <description>User cipher key (0x4000_1060).</description> 340 <value>0</value> 341 </enumeratedValue> 342 <enumeratedValue> 343 <name>regFile</name> 344 <description>Key from battery-backed register file (0x4000_5000 to 0x4000_501F).</description> 345 <value>2</value> 346 </enumeratedValue> 347 <enumeratedValue> 348 <name>qspiKey_regFile</name> 349 <description>Key from battery-backed register file (0x4000_5020 to 0x4000_502F).</description> 350 <value>3</value> 351 </enumeratedValue> 352 </enumeratedValues> 353 </field> 354 <field> 355 <name>CIPHER</name> 356 <description>Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation.</description> 357 <bitOffset>4</bitOffset> 358 <bitWidth>3</bitWidth> 359 <enumeratedValues> 360 <enumeratedValue> 361 <name>dis</name> 362 <description>Disabled.</description> 363 <value>0</value> 364 </enumeratedValue> 365 <enumeratedValue> 366 <name>aes128</name> 367 <description>AES 128.</description> 368 <value>1</value> 369 </enumeratedValue> 370 <enumeratedValue> 371 <name>aes192</name> 372 <description>AES 192.</description> 373 <value>2</value> 374 </enumeratedValue> 375 <enumeratedValue> 376 <name>aes256</name> 377 <description>AES 256.</description> 378 <value>3</value> 379 </enumeratedValue> 380 <enumeratedValue> 381 <name>des</name> 382 <description>DES.</description> 383 <value>4</value> 384 </enumeratedValue> 385 <enumeratedValue> 386 <name>tdes</name> 387 <description>Triple DES.</description> 388 <value>5</value> 389 </enumeratedValue> 390 </enumeratedValues> 391 </field> 392 <field> 393 <name>MODE</name> 394 <description>Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes.</description> 395 <bitOffset>8</bitOffset> 396 <bitWidth>3</bitWidth> 397 <enumeratedValues> 398 <enumeratedValue> 399 <name>ECB</name> 400 <description>ECB Mode.</description> 401 <value>0</value> 402 </enumeratedValue> 403 <enumeratedValue> 404 <name>CBC</name> 405 <description>CBC Mode.</description> 406 <value>1</value> 407 </enumeratedValue> 408 <enumeratedValue> 409 <name>CFB</name> 410 <description>CFB (AES only).</description> 411 <value>2</value> 412 </enumeratedValue> 413 <enumeratedValue> 414 <name>OFB</name> 415 <description>OFB (AES only).</description> 416 <value>3</value> 417 </enumeratedValue> 418 <enumeratedValue> 419 <name>CTR</name> 420 <description>CTR (AES only).</description> 421 <value>4</value> 422 </enumeratedValue> 423 <enumeratedValue> 424 <name>GCM</name> 425 <description>GCM.</description> 426 <value>5</value> 427 </enumeratedValue> 428 <enumeratedValue> 429 <name>CCM</name> 430 <description>CCM.</description> 431 <value>6</value> 432 </enumeratedValue> 433 </enumeratedValues> 434 </field> 435 <field> 436 <name>HVC</name> 437 <description>H Vector Computation.</description> 438 <bitOffset>11</bitOffset> 439 <bitWidth>1</bitWidth> 440 <access>read-only</access> 441 </field> 442 <field> 443 <name>DTYPE</name> 444 <description>GCM/CCM data type.</description> 445 <bitOffset>12</bitOffset> 446 <bitWidth>1</bitWidth> 447 <access>read-only</access> 448 <enumeratedValues> 449 <enumeratedValue> 450 <name>AAD</name> 451 <description>AAD.</description> 452 <value>0</value> 453 </enumeratedValue> 454 <enumeratedValue> 455 <name>PLD</name> 456 <description>PLD.</description> 457 <value>1</value> 458 </enumeratedValue> 459 </enumeratedValues> 460 </field> 461 <field> 462 <name>CCMM</name> 463 <description>CCM M Parameter.</description> 464 <bitOffset>13</bitOffset> 465 <bitWidth>3</bitWidth> 466 <access>read-only</access> 467 <enumeratedValues> 468 <enumeratedValue> 469 <name>4</name> 470 <description>4</description> 471 <value>1</value> 472 </enumeratedValue> 473 <enumeratedValue> 474 <name>6</name> 475 <description>6</description> 476 <value>2</value> 477 </enumeratedValue> 478 <enumeratedValue> 479 <name>8</name> 480 <description>8</description> 481 <value>3</value> 482 </enumeratedValue> 483 <enumeratedValue> 484 <name>10</name> 485 <description>10</description> 486 <value>4</value> 487 </enumeratedValue> 488 <enumeratedValue> 489 <name>12</name> 490 <description>12</description> 491 <value>5</value> 492 </enumeratedValue> 493 <enumeratedValue> 494 <name>14</name> 495 <description>14</description> 496 <value>6</value> 497 </enumeratedValue> 498 <enumeratedValue> 499 <name>16</name> 500 <description>16</description> 501 <value>7</value> 502 </enumeratedValue> 503 </enumeratedValues> 504 </field> 505 <field> 506 <name>CCML</name> 507 <description>CCM L Parameter.</description> 508 <bitOffset>16</bitOffset> 509 <bitWidth>3</bitWidth> 510 <access>read-only</access> 511 <enumeratedValues> 512 <enumeratedValue> 513 <name>2</name> 514 <description>2</description> 515 <value>1</value> 516 </enumeratedValue> 517 <enumeratedValue> 518 <name>3</name> 519 <description>3</description> 520 <value>2</value> 521 </enumeratedValue> 522 <enumeratedValue> 523 <name>4</name> 524 <description>4</description> 525 <value>3</value> 526 </enumeratedValue> 527 <enumeratedValue> 528 <name>5</name> 529 <description>5</description> 530 <value>4</value> 531 </enumeratedValue> 532 <enumeratedValue> 533 <name>6</name> 534 <description>6</description> 535 <value>5</value> 536 </enumeratedValue> 537 <enumeratedValue> 538 <name>7</name> 539 <description>7</description> 540 <value>6</value> 541 </enumeratedValue> 542 <enumeratedValue> 543 <name>8</name> 544 <description>8</description> 545 <value>7</value> 546 </enumeratedValue> 547 </enumeratedValues> 548 </field> 549 </fields> 550 </register> 551 <register> 552 <name>HASH_CTRL</name> 553 <description>HASH Control Register.</description> 554 <addressOffset>0x08</addressOffset> 555 <fields> 556 <field> 557 <name>INIT</name> 558 <description>Initialize. Initializes hash registers with standard constants.</description> 559 <bitOffset>0</bitOffset> 560 <bitWidth>1</bitWidth> 561 <enumeratedValues> 562 <enumeratedValue> 563 <name>nop</name> 564 <description>No operation/complete.</description> 565 <value>0</value> 566 </enumeratedValue> 567 <enumeratedValue> 568 <name>start</name> 569 <description>Start operation.</description> 570 <value>1</value> 571 </enumeratedValue> 572 </enumeratedValues> 573 </field> 574 <field> 575 <name>XOR</name> 576 <description>XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad.</description> 577 <bitOffset>1</bitOffset> 578 <bitWidth>1</bitWidth> 579 <enumeratedValues> 580 <enumeratedValue> 581 <name>dis</name> 582 <description>Disable.</description> 583 <value>0</value> 584 </enumeratedValue> 585 <enumeratedValue> 586 <name>en</name> 587 <description>Enable.</description> 588 <value>1</value> 589 </enumeratedValue> 590 </enumeratedValues> 591 </field> 592 <field> 593 <name>HASH</name> 594 <description>Hash function selection.</description> 595 <bitOffset>2</bitOffset> 596 <bitWidth>3</bitWidth> 597 <enumeratedValues> 598 <enumeratedValue> 599 <name>dis</name> 600 <description>Disabled.</description> 601 <value>0</value> 602 </enumeratedValue> 603 <enumeratedValue> 604 <name>sha1</name> 605 <description>SHA-1.</description> 606 <value>1</value> 607 </enumeratedValue> 608 <enumeratedValue> 609 <name>sha224</name> 610 <description>SHA 224.</description> 611 <value>2</value> 612 </enumeratedValue> 613 <enumeratedValue> 614 <name>sha256</name> 615 <description>SHA 256.</description> 616 <value>3</value> 617 </enumeratedValue> 618 <enumeratedValue> 619 <name>sha384</name> 620 <description>SHA 384.</description> 621 <value>4</value> 622 </enumeratedValue> 623 <enumeratedValue> 624 <name>sha512</name> 625 <description>SHA 512.</description> 626 <value>5</value> 627 </enumeratedValue> 628 </enumeratedValues> 629 </field> 630 <field> 631 <name>LAST</name> 632 <description>Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash.</description> 633 <bitOffset>5</bitOffset> 634 <bitWidth>1</bitWidth> 635 <enumeratedValues> 636 <enumeratedValue> 637 <name>noEffect</name> 638 <description>No Effect.</description> 639 <value>0</value> 640 </enumeratedValue> 641 <enumeratedValue> 642 <name>lastMsgData</name> 643 <description>Last Message Data.</description> 644 <value>1</value> 645 </enumeratedValue> 646 </enumeratedValues> 647 </field> 648 </fields> 649 </register> 650 <register> 651 <name>CRC_CTRL</name> 652 <description>CRC Control Register.</description> 653 <addressOffset>0x0C</addressOffset> 654 <fields> 655 <field> 656 <name>CRC</name> 657 <description>Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled.</description> 658 <bitOffset>0</bitOffset> 659 <bitWidth>1</bitWidth> 660 <enumeratedValues> 661 <enumeratedValue> 662 <name>dis</name> 663 <description>Disable.</description> 664 <value>0</value> 665 </enumeratedValue> 666 <enumeratedValue> 667 <name>en</name> 668 <description>Enable.</description> 669 <value>1</value> 670 </enumeratedValue> 671 </enumeratedValues> 672 </field> 673 <field> 674 <name>MSB</name> 675 <description>MSB select. This bit selects the order of calculating CRC on data.</description> 676 <bitOffset>1</bitOffset> 677 <bitWidth>1</bitWidth> 678 <enumeratedValues> 679 <enumeratedValue> 680 <name>lsbFirst</name> 681 <description>LSB First.</description> 682 <value>0</value> 683 </enumeratedValue> 684 <enumeratedValue> 685 <name>msbFirst</name> 686 <description>MSB First.</description> 687 <value>1</value> 688 </enumeratedValue> 689 </enumeratedValues> 690 </field> 691 <field derivedFrom="CRC"> 692 <name>PRNG</name> 693 <description>Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle.</description> 694 <bitOffset>2</bitOffset> 695 <bitWidth>1</bitWidth> 696 </field> 697 <field derivedFrom="CRC"> 698 <name>ENT</name> 699 <description>Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source.</description> 700 <bitOffset>3</bitOffset> 701 <bitWidth>1</bitWidth> 702 </field> 703 <field derivedFrom="CRC"> 704 <name>HAM</name> 705 <description>Hamming Code Enable. Enable hamming code calculation.</description> 706 <bitOffset>4</bitOffset> 707 <bitWidth>1</bitWidth> 708 </field> 709 <field> 710 <name>HRST</name> 711 <description>Hamming Reset. Reset Hamming code ECC generator for next block.</description> 712 <bitOffset>5</bitOffset> 713 <bitWidth>1</bitWidth> 714 <access>write-only</access> 715 <enumeratedValues> 716 <usage>write</usage> 717 <enumeratedValue> 718 <name>reset</name> 719 <description>Starts reset operation.</description> 720 <value>1</value> 721 </enumeratedValue> 722 </enumeratedValues> 723 </field> 724 </fields> 725 </register> 726 <register> 727 <name>DMA_SRC</name> 728 <description>Crypto DMA Source Address.</description> 729 <addressOffset>0x10</addressOffset> 730 <fields> 731 <field> 732 <name>ADDR</name> 733 <description>DMA Source Address.</description> 734 <bitOffset>0</bitOffset> 735 <bitWidth>32</bitWidth> 736 </field> 737 </fields> 738 </register> 739 <register> 740 <name>DMA_DEST</name> 741 <description>Crypto DMA Destination Address.</description> 742 <addressOffset>0x14</addressOffset> 743 <fields> 744 <field> 745 <name>ADDR</name> 746 <description>DMA Destination Address.</description> 747 <bitOffset>0</bitOffset> 748 <bitWidth>32</bitWidth> 749 </field> 750 </fields> 751 </register> 752 <register> 753 <name>DMA_CNT</name> 754 <description>Crypto DMA Byte Count.</description> 755 <addressOffset>0x18</addressOffset> 756 <fields> 757 <field> 758 <name>ADDR</name> 759 <description>DMA Byte Address.</description> 760 <bitOffset>0</bitOffset> 761 <bitWidth>32</bitWidth> 762 </field> 763 </fields> 764 </register> 765 <register> 766 <name>MAA_CTRL</name> 767 <description>MAA Control Register.</description> 768 <addressOffset>0x1C</addressOffset> 769 </register> 770 <register> 771 <dim>4</dim> 772 <dimIncrement>4</dimIncrement> 773 <name>DIN[%s]</name> 774 <description>Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.</description> 775 <addressOffset>0x20</addressOffset> 776 <access>write-only</access> 777 <fields> 778 <field> 779 <name>DATA</name> 780 <description>Crypto Data Input. Input can be written to this register instead of using DMA.</description> 781 <bitOffset>0</bitOffset> 782 <bitWidth>32</bitWidth> 783 </field> 784 </fields> 785 </register> 786 <register> 787 <dim>4</dim> 788 <dimIncrement>4</dimIncrement> 789 <name>DOUT[%s]</name> 790 <description>Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.</description> 791 <addressOffset>0x30</addressOffset> 792 <access>read-only</access> 793 <fields> 794 <field> 795 <name>DATA</name> 796 <description>Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.</description> 797 <bitOffset>0</bitOffset> 798 <bitWidth>32</bitWidth> 799 </field> 800 </fields> 801 </register> 802 <register> 803 <name>CRC_POLY</name> 804 <description>CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.</description> 805 <addressOffset>0x40</addressOffset> 806 <resetValue>0xEDB88320</resetValue> 807 <fields> 808 <field> 809 <name>POLY</name> 810 <description>CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.</description> 811 <bitOffset>0</bitOffset> 812 <bitWidth>32</bitWidth> 813 </field> 814 </fields> 815 </register> 816 <register> 817 <name>CRC_VAL</name> 818 <description>CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit.</description> 819 <addressOffset>0x44</addressOffset> 820 <resetValue>0xFFFFFFFF</resetValue> 821 <fields> 822 <field> 823 <name>VAL</name> 824 <description>CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit.</description> 825 <bitOffset>0</bitOffset> 826 <bitWidth>32</bitWidth> 827 </field> 828 </fields> 829 </register> 830 <register> 831 <name>CRC_PRNG</name> 832 <description>CRC PRNG Register.</description> 833 <addressOffset>0x48</addressOffset> 834 <fields> 835 <field> 836 <name>PRNG</name> 837 <description>PRNG</description> 838 <bitOffset>0</bitOffset> 839 <bitWidth>32</bitWidth> 840 </field> 841 </fields> 842 </register> 843 <register> 844 <name>HAM_ECC</name> 845 <description>Hamming ECC Register.</description> 846 <addressOffset>0x4C</addressOffset> 847 <fields> 848 <field> 849 <name>ECC</name> 850 <description>Hamming ECC Value. These bits are the even parity of their corresponding bit groups.</description> 851 <bitOffset>0</bitOffset> 852 <bitWidth>16</bitWidth> 853 </field> 854 <field> 855 <name>PAR</name> 856 <description>Parity. This is the parity of the entire array.</description> 857 <bitOffset>16</bitOffset> 858 <bitWidth>1</bitWidth> 859 <enumeratedValues> 860 <enumeratedValue> 861 <name>even</name> 862 <description>Even.</description> 863 <value>0</value> 864 </enumeratedValue> 865 <enumeratedValue> 866 <name>odd</name> 867 <description>Odd.</description> 868 <value>1</value> 869 </enumeratedValue> 870 </enumeratedValues> 871 </field> 872 </fields> 873 </register> 874 <register> 875 <dim>4</dim> 876 <dimIncrement>4</dimIncrement> 877 <name>CIPHER_INIT[%s]</name> 878 <description>Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.</description> 879 <addressOffset>0x50</addressOffset> 880 <fields> 881 <field> 882 <name>IVEC</name> 883 <description>Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.</description> 884 <bitOffset>0</bitOffset> 885 <bitWidth>32</bitWidth> 886 </field> 887 </fields> 888 </register> 889 <register> 890 <dim>8</dim> 891 <dimIncrement>4</dimIncrement> 892 <name>CIPHER_KEY[%s]</name> 893 <description>Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.</description> 894 <addressOffset>0x60</addressOffset> 895 <access>write-only</access> 896 <fields> 897 <field> 898 <name>KEY</name> 899 <description>Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.</description> 900 <bitOffset>0</bitOffset> 901 <bitWidth>32</bitWidth> 902 </field> 903 </fields> 904 </register> 905 <register> 906 <dim>16</dim> 907 <dimIncrement>4</dimIncrement> 908 <name>HASH_DIGEST[%s]</name> 909 <description>This register holds the calculated hash value. This register is affected by the endian swap bits.</description> 910 <addressOffset>0x80</addressOffset> 911 <fields> 912 <field> 913 <name>HASH</name> 914 <description>This register holds the calculated hash value. This register is affected by the endian swap bits.</description> 915 <bitOffset>0</bitOffset> 916 <bitWidth>32</bitWidth> 917 </field> 918 </fields> 919 </register> 920 <register> 921 <dim>4</dim> 922 <dimIncrement>4</dimIncrement> 923 <name>HASH_MSG_SZ[%s]</name> 924 <description>Message Size. This register holds the lowest 32-bit of message size in bytes.</description> 925 <addressOffset>0xC0</addressOffset> 926 <fields> 927 <field> 928 <name>MSGSZ</name> 929 <description>Message Size. This register holds the lowest 32-bit of message size in bytes.</description> 930 <bitOffset>0</bitOffset> 931 <bitWidth>32</bitWidth> 932 </field> 933 </fields> 934 </register> 935 <register> 936 <name>MAA_MAWS</name> 937 <description>MAA Word Size Register.</description> 938 <addressOffset>0xD0</addressOffset> 939 <resetValue>0x0</resetValue> 940 <fields> 941 <field> 942 <name>SIZE</name> 943 <description>MAA Word Size.</description> 944 <bitOffset>0</bitOffset> 945 <bitWidth>32</bitWidth> 946 </field> 947 </fields> 948 </register> 949 <register> 950 <dim>2</dim> 951 <dimIncrement>4</dimIncrement> 952 <name>AAD_LENGTH[%s]</name> 953 <description>AAD Length Registers.</description> 954 <addressOffset>0xD0</addressOffset> 955 <resetValue>0x0</resetValue> 956 <fields> 957 <field> 958 <name>LENGTH</name> 959 <description>AAD length in bytes for AES GCM and CCM operations.</description> 960 <bitOffset>0</bitOffset> 961 <bitWidth>32</bitWidth> 962 </field> 963 </fields> 964 </register> 965 <register> 966 <dim>2</dim> 967 <dimIncrement>4</dimIncrement> 968 <name>PLD_LENGTH[%s]</name> 969 <description>PLD Length Registers.</description> 970 <addressOffset>0xD8</addressOffset> 971 <resetValue>0x0</resetValue> 972 <fields> 973 <field> 974 <name>LENGTH</name> 975 <description>PLD length in bytes for AES GCM and CCM operations.</description> 976 <bitOffset>0</bitOffset> 977 <bitWidth>32</bitWidth> 978 </field> 979 </fields> 980 </register> 981 <register> 982 <dim>4</dim> 983 <dimIncrement>4</dimIncrement> 984 <name>TAGMIC[%s]</name> 985 <description>TAG/MIC Registers.</description> 986 <addressOffset>0xE0</addressOffset> 987 <fields> 988 <field> 989 <name>LENGTH</name> 990 <description>TAG/MIC output for AES GCM and CCM operations.</description> 991 <bitOffset>0</bitOffset> 992 <bitWidth>32</bitWidth> 993 </field> 994 </fields> 995 </register> 996 </registers> 997 </peripheral> 998 <!-- CRYPTO: The Cryptographic Tool Box --> 999</device>
