1 /** 2 * @file clcd_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the CLCD_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _CLCD_REVA_REGS_H_ 27 #define _CLCD_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup clcd_reva 65 * @defgroup clcd_reva_registers CLCD_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the CLCD_REVA Peripheral Module. 67 * @details Color LCD Controller 68 */ 69 70 /** 71 * @ingroup clcd_reva_registers 72 * Structure type to access the CLCD_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t clk; /**< <tt>\b 0x000:</tt> CLCD_REVA CLK Register */ 76 __IO uint32_t vtim_0; /**< <tt>\b 0x004:</tt> CLCD_REVA VTIM_0 Register */ 77 __IO uint32_t vtim_1; /**< <tt>\b 0x008:</tt> CLCD_REVA VTIM_1 Register */ 78 __IO uint32_t htim; /**< <tt>\b 0x00C:</tt> CLCD_REVA HTIM Register */ 79 __IO uint32_t ctrl; /**< <tt>\b 0x010:</tt> CLCD_REVA CTRL Register */ 80 __R uint32_t rsv_0x14; 81 __IO uint32_t fr; /**< <tt>\b 0x18:</tt> CLCD_REVA FR Register */ 82 __R uint32_t rsv_0x1c; 83 __IO uint32_t int_en; /**< <tt>\b 0x020:</tt> CLCD_REVA INT_EN Register */ 84 __IO uint32_t stat; /**< <tt>\b 0x024:</tt> CLCD_REVA STAT Register */ 85 __R uint32_t rsv_0x28_0x3ff[246]; 86 __IO uint32_t palette[256]; /**< <tt>\b 0x400:</tt> CLCD_REVA PALETTE Register */ 87 } mxc_clcd_reva_regs_t; 88 89 /** 90 * @ingroup clcd_reva_registers 91 * @defgroup CLCD_REVA_CLK CLCD_REVA_CLK 92 * @brief LCD Clock Control Register 93 * @{ 94 */ 95 #define MXC_F_CLCD_REVA_CLK_CLKDIV_POS 0 /**< CLK_CLKDIV Position */ 96 #define MXC_F_CLCD_REVA_CLK_CLKDIV ((uint32_t)(0xFFUL << MXC_F_CLCD_REVA_CLK_CLKDIV_POS)) /**< CLK_CLKDIV Mask */ 97 98 #define MXC_F_CLCD_REVA_CLK_ACB_POS 8 /**< CLK_ACB Position */ 99 #define MXC_F_CLCD_REVA_CLK_ACB ((uint32_t)(0xFFUL << MXC_F_CLCD_REVA_CLK_ACB_POS)) /**< CLK_ACB Mask */ 100 101 #define MXC_F_CLCD_REVA_CLK_DPOL_POS 16 /**< CLK_DPOL Position */ 102 #define MXC_F_CLCD_REVA_CLK_DPOL ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_CLK_DPOL_POS)) /**< CLK_DPOL Mask */ 103 #define MXC_V_CLCD_REVA_CLK_DPOL_ACTIVEHI ((uint32_t)0x0UL) /**< CLK_DPOL_ACTIVEHI Value */ 104 #define MXC_S_CLCD_REVA_CLK_DPOL_ACTIVEHI (MXC_V_CLCD_REVA_CLK_DPOL_ACTIVEHI << MXC_F_CLCD_REVA_CLK_DPOL_POS) /**< CLK_DPOL_ACTIVEHI Setting */ 105 #define MXC_V_CLCD_REVA_CLK_DPOL_ACTIVELO ((uint32_t)0x1UL) /**< CLK_DPOL_ACTIVELO Value */ 106 #define MXC_S_CLCD_REVA_CLK_DPOL_ACTIVELO (MXC_V_CLCD_REVA_CLK_DPOL_ACTIVELO << MXC_F_CLCD_REVA_CLK_DPOL_POS) /**< CLK_DPOL_ACTIVELO Setting */ 107 108 #define MXC_F_CLCD_REVA_CLK_VPOL_POS 17 /**< CLK_VPOL Position */ 109 #define MXC_F_CLCD_REVA_CLK_VPOL ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_CLK_VPOL_POS)) /**< CLK_VPOL Mask */ 110 #define MXC_V_CLCD_REVA_CLK_VPOL_ACTIVEHI ((uint32_t)0x1UL) /**< CLK_VPOL_ACTIVEHI Value */ 111 #define MXC_S_CLCD_REVA_CLK_VPOL_ACTIVEHI (MXC_V_CLCD_REVA_CLK_VPOL_ACTIVEHI << MXC_F_CLCD_REVA_CLK_VPOL_POS) /**< CLK_VPOL_ACTIVEHI Setting */ 112 #define MXC_V_CLCD_REVA_CLK_VPOL_ACTIVELO ((uint32_t)0x0UL) /**< CLK_VPOL_ACTIVELO Value */ 113 #define MXC_S_CLCD_REVA_CLK_VPOL_ACTIVELO (MXC_V_CLCD_REVA_CLK_VPOL_ACTIVELO << MXC_F_CLCD_REVA_CLK_VPOL_POS) /**< CLK_VPOL_ACTIVELO Setting */ 114 115 #define MXC_F_CLCD_REVA_CLK_HPOL_POS 18 /**< CLK_HPOL Position */ 116 #define MXC_F_CLCD_REVA_CLK_HPOL ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_CLK_HPOL_POS)) /**< CLK_HPOL Mask */ 117 #define MXC_V_CLCD_REVA_CLK_HPOL_ACTIVEHI ((uint32_t)0x1UL) /**< CLK_HPOL_ACTIVEHI Value */ 118 #define MXC_S_CLCD_REVA_CLK_HPOL_ACTIVEHI (MXC_V_CLCD_REVA_CLK_HPOL_ACTIVEHI << MXC_F_CLCD_REVA_CLK_HPOL_POS) /**< CLK_HPOL_ACTIVEHI Setting */ 119 #define MXC_V_CLCD_REVA_CLK_HPOL_ACTIVELO ((uint32_t)0x0UL) /**< CLK_HPOL_ACTIVELO Value */ 120 #define MXC_S_CLCD_REVA_CLK_HPOL_ACTIVELO (MXC_V_CLCD_REVA_CLK_HPOL_ACTIVELO << MXC_F_CLCD_REVA_CLK_HPOL_POS) /**< CLK_HPOL_ACTIVELO Setting */ 121 122 #define MXC_F_CLCD_REVA_CLK_EDGE_POS 19 /**< CLK_EDGE Position */ 123 #define MXC_F_CLCD_REVA_CLK_EDGE ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_CLK_EDGE_POS)) /**< CLK_EDGE Mask */ 124 #define MXC_V_CLCD_REVA_CLK_EDGE_RISEEDGE ((uint32_t)0x0UL) /**< CLK_EDGE_RISEEDGE Value */ 125 #define MXC_S_CLCD_REVA_CLK_EDGE_RISEEDGE (MXC_V_CLCD_REVA_CLK_EDGE_RISEEDGE << MXC_F_CLCD_REVA_CLK_EDGE_POS) /**< CLK_EDGE_RISEEDGE Setting */ 126 #define MXC_V_CLCD_REVA_CLK_EDGE_FALLEDGE ((uint32_t)0x1UL) /**< CLK_EDGE_FALLEDGE Value */ 127 #define MXC_S_CLCD_REVA_CLK_EDGE_FALLEDGE (MXC_V_CLCD_REVA_CLK_EDGE_FALLEDGE << MXC_F_CLCD_REVA_CLK_EDGE_POS) /**< CLK_EDGE_FALLEDGE Setting */ 128 129 #define MXC_F_CLCD_REVA_CLK_PASCLK_POS 20 /**< CLK_PASCLK Position */ 130 #define MXC_F_CLCD_REVA_CLK_PASCLK ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_CLK_PASCLK_POS)) /**< CLK_PASCLK Mask */ 131 #define MXC_V_CLCD_REVA_CLK_PASCLK_ALWAYSACTIVE ((uint32_t)0x0UL) /**< CLK_PASCLK_ALWAYSACTIVE Value */ 132 #define MXC_S_CLCD_REVA_CLK_PASCLK_ALWAYSACTIVE (MXC_V_CLCD_REVA_CLK_PASCLK_ALWAYSACTIVE << MXC_F_CLCD_REVA_CLK_PASCLK_POS) /**< CLK_PASCLK_ALWAYSACTIVE Setting */ 133 #define MXC_V_CLCD_REVA_CLK_PASCLK_ACTIVEONDATA ((uint32_t)0x1UL) /**< CLK_PASCLK_ACTIVEONDATA Value */ 134 #define MXC_S_CLCD_REVA_CLK_PASCLK_ACTIVEONDATA (MXC_V_CLCD_REVA_CLK_PASCLK_ACTIVEONDATA << MXC_F_CLCD_REVA_CLK_PASCLK_POS) /**< CLK_PASCLK_ACTIVEONDATA Setting */ 135 136 /**@} end of group CLCD_REVA_CLK_Register */ 137 138 /** 139 * @ingroup clcd_reva_registers 140 * @defgroup CLCD_REVA_VTIM_0 CLCD_REVA_VTIM_0 141 * @brief LCD Vertical Timing 0 Register 142 * @{ 143 */ 144 #define MXC_F_CLCD_REVA_VTIM_0_VLINES_POS 0 /**< VTIM_0_VLINES Position */ 145 #define MXC_F_CLCD_REVA_VTIM_0_VLINES ((uint32_t)(0xFFUL << MXC_F_CLCD_REVA_VTIM_0_VLINES_POS)) /**< VTIM_0_VLINES Mask */ 146 147 #define MXC_F_CLCD_REVA_VTIM_0_VBACKPORCH_POS 16 /**< VTIM_0_VBACKPORCH Position */ 148 #define MXC_F_CLCD_REVA_VTIM_0_VBACKPORCH ((uint32_t)(0xFFUL << MXC_F_CLCD_REVA_VTIM_0_VBACKPORCH_POS)) /**< VTIM_0_VBACKPORCH Mask */ 149 150 /**@} end of group CLCD_REVA_VTIM_0_Register */ 151 152 /** 153 * @ingroup clcd_reva_registers 154 * @defgroup CLCD_REVA_VTIM_1 CLCD_REVA_VTIM_1 155 * @brief LCD Vertical Timing 1 Register 156 * @{ 157 */ 158 #define MXC_F_CLCD_REVA_VTIM_1_VSYNCWIDTH_POS 0 /**< VTIM_1_VSYNCWIDTH Position */ 159 #define MXC_F_CLCD_REVA_VTIM_1_VSYNCWIDTH ((uint32_t)(0xFFUL << MXC_F_CLCD_REVA_VTIM_1_VSYNCWIDTH_POS)) /**< VTIM_1_VSYNCWIDTH Mask */ 160 161 #define MXC_F_CLCD_REVA_VTIM_1_VFRONTPORCH_POS 16 /**< VTIM_1_VFRONTPORCH Position */ 162 #define MXC_F_CLCD_REVA_VTIM_1_VFRONTPORCH ((uint32_t)(0xFFUL << MXC_F_CLCD_REVA_VTIM_1_VFRONTPORCH_POS)) /**< VTIM_1_VFRONTPORCH Mask */ 163 164 /**@} end of group CLCD_REVA_VTIM_1_Register */ 165 166 /** 167 * @ingroup clcd_reva_registers 168 * @defgroup CLCD_REVA_HTIM CLCD_REVA_HTIM 169 * @brief LCD Horizontal Timing Register. 170 * @{ 171 */ 172 #define MXC_F_CLCD_REVA_HTIM_HSYNCWIDTH_POS 0 /**< HTIM_HSYNCWIDTH Position */ 173 #define MXC_F_CLCD_REVA_HTIM_HSYNCWIDTH ((uint32_t)(0xFFUL << MXC_F_CLCD_REVA_HTIM_HSYNCWIDTH_POS)) /**< HTIM_HSYNCWIDTH Mask */ 174 175 #define MXC_F_CLCD_REVA_HTIM_HFRONTPORCH_POS 8 /**< HTIM_HFRONTPORCH Position */ 176 #define MXC_F_CLCD_REVA_HTIM_HFRONTPORCH ((uint32_t)(0xFFUL << MXC_F_CLCD_REVA_HTIM_HFRONTPORCH_POS)) /**< HTIM_HFRONTPORCH Mask */ 177 178 #define MXC_F_CLCD_REVA_HTIM_HSIZE_POS 16 /**< HTIM_HSIZE Position */ 179 #define MXC_F_CLCD_REVA_HTIM_HSIZE ((uint32_t)(0xFFUL << MXC_F_CLCD_REVA_HTIM_HSIZE_POS)) /**< HTIM_HSIZE Mask */ 180 181 #define MXC_F_CLCD_REVA_HTIM_HBACKPORCH_POS 24 /**< HTIM_HBACKPORCH Position */ 182 #define MXC_F_CLCD_REVA_HTIM_HBACKPORCH ((uint32_t)(0xFFUL << MXC_F_CLCD_REVA_HTIM_HBACKPORCH_POS)) /**< HTIM_HBACKPORCH Mask */ 183 184 /**@} end of group CLCD_REVA_HTIM_Register */ 185 186 /** 187 * @ingroup clcd_reva_registers 188 * @defgroup CLCD_REVA_CTRL CLCD_REVA_CTRL 189 * @brief LCD Control Register 190 * @{ 191 */ 192 #define MXC_F_CLCD_REVA_CTRL_LCDEN_POS 0 /**< CTRL_LCDEN Position */ 193 #define MXC_F_CLCD_REVA_CTRL_LCDEN ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_CTRL_LCDEN_POS)) /**< CTRL_LCDEN Mask */ 194 #define MXC_V_CLCD_REVA_CTRL_LCDEN_DISABLE ((uint32_t)0x0UL) /**< CTRL_LCDEN_DISABLE Value */ 195 #define MXC_S_CLCD_REVA_CTRL_LCDEN_DISABLE (MXC_V_CLCD_REVA_CTRL_LCDEN_DISABLE << MXC_F_CLCD_REVA_CTRL_LCDEN_POS) /**< CTRL_LCDEN_DISABLE Setting */ 196 #define MXC_V_CLCD_REVA_CTRL_LCDEN_ENABLE ((uint32_t)0x1UL) /**< CTRL_LCDEN_ENABLE Value */ 197 #define MXC_S_CLCD_REVA_CTRL_LCDEN_ENABLE (MXC_V_CLCD_REVA_CTRL_LCDEN_ENABLE << MXC_F_CLCD_REVA_CTRL_LCDEN_POS) /**< CTRL_LCDEN_ENABLE Setting */ 198 199 #define MXC_F_CLCD_REVA_CTRL_VISEL_POS 1 /**< CTRL_VISEL Position */ 200 #define MXC_F_CLCD_REVA_CTRL_VISEL ((uint32_t)(0x3UL << MXC_F_CLCD_REVA_CTRL_VISEL_POS)) /**< CTRL_VISEL Mask */ 201 #define MXC_V_CLCD_REVA_CTRL_VISEL_ONVERTSYNC ((uint32_t)0x0UL) /**< CTRL_VISEL_ONVERTSYNC Value */ 202 #define MXC_S_CLCD_REVA_CTRL_VISEL_ONVERTSYNC (MXC_V_CLCD_REVA_CTRL_VISEL_ONVERTSYNC << MXC_F_CLCD_REVA_CTRL_VISEL_POS) /**< CTRL_VISEL_ONVERTSYNC Setting */ 203 #define MXC_V_CLCD_REVA_CTRL_VISEL_ONVERTBACKPORCH ((uint32_t)0x1UL) /**< CTRL_VISEL_ONVERTBACKPORCH Value */ 204 #define MXC_S_CLCD_REVA_CTRL_VISEL_ONVERTBACKPORCH (MXC_V_CLCD_REVA_CTRL_VISEL_ONVERTBACKPORCH << MXC_F_CLCD_REVA_CTRL_VISEL_POS) /**< CTRL_VISEL_ONVERTBACKPORCH Setting */ 205 #define MXC_V_CLCD_REVA_CTRL_VISEL_ONACTIVEVIDEO ((uint32_t)0x2UL) /**< CTRL_VISEL_ONACTIVEVIDEO Value */ 206 #define MXC_S_CLCD_REVA_CTRL_VISEL_ONACTIVEVIDEO (MXC_V_CLCD_REVA_CTRL_VISEL_ONACTIVEVIDEO << MXC_F_CLCD_REVA_CTRL_VISEL_POS) /**< CTRL_VISEL_ONACTIVEVIDEO Setting */ 207 #define MXC_V_CLCD_REVA_CTRL_VISEL_ONVERTFRONTPORCH ((uint32_t)0x3UL) /**< CTRL_VISEL_ONVERTFRONTPORCH Value */ 208 #define MXC_S_CLCD_REVA_CTRL_VISEL_ONVERTFRONTPORCH (MXC_V_CLCD_REVA_CTRL_VISEL_ONVERTFRONTPORCH << MXC_F_CLCD_REVA_CTRL_VISEL_POS) /**< CTRL_VISEL_ONVERTFRONTPORCH Setting */ 209 210 #define MXC_F_CLCD_REVA_CTRL_DISPTYPE_POS 4 /**< CTRL_DISPTYPE Position */ 211 #define MXC_F_CLCD_REVA_CTRL_DISPTYPE ((uint32_t)(0xFUL << MXC_F_CLCD_REVA_CTRL_DISPTYPE_POS)) /**< CTRL_DISPTYPE Mask */ 212 #define MXC_V_CLCD_REVA_CTRL_DISPTYPE_STNCOLOR8BIT ((uint32_t)0x4UL) /**< CTRL_DISPTYPE_STNCOLOR8BIT Value */ 213 #define MXC_S_CLCD_REVA_CTRL_DISPTYPE_STNCOLOR8BIT (MXC_V_CLCD_REVA_CTRL_DISPTYPE_STNCOLOR8BIT << MXC_F_CLCD_REVA_CTRL_DISPTYPE_POS) /**< CTRL_DISPTYPE_STNCOLOR8BIT Setting */ 214 #define MXC_V_CLCD_REVA_CTRL_DISPTYPE_CLCD ((uint32_t)0x8UL) /**< CTRL_DISPTYPE_CLCD_REVA Value */ 215 #define MXC_S_CLCD_REVA_CTRL_DISPTYPE_CLCD (MXC_V_CLCD_REVA_CTRL_DISPTYPE_CLCD << MXC_F_CLCD_REVA_CTRL_DISPTYPE_POS) /**< CTRL_DISPTYPE_CLCD_REVA Setting */ 216 217 #define MXC_F_CLCD_REVA_CTRL_BPP_POS 8 /**< CTRL_BPP Position */ 218 #define MXC_F_CLCD_REVA_CTRL_BPP ((uint32_t)(0x7UL << MXC_F_CLCD_REVA_CTRL_BPP_POS)) /**< CTRL_BPP Mask */ 219 #define MXC_V_CLCD_REVA_CTRL_BPP_BPP1 ((uint32_t)0x0UL) /**< CTRL_BPP_BPP1 Value */ 220 #define MXC_S_CLCD_REVA_CTRL_BPP_BPP1 (MXC_V_CLCD_REVA_CTRL_BPP_BPP1 << MXC_F_CLCD_REVA_CTRL_BPP_POS) /**< CTRL_BPP_BPP1 Setting */ 221 #define MXC_V_CLCD_REVA_CTRL_BPP_BPP2 ((uint32_t)0x1UL) /**< CTRL_BPP_BPP2 Value */ 222 #define MXC_S_CLCD_REVA_CTRL_BPP_BPP2 (MXC_V_CLCD_REVA_CTRL_BPP_BPP2 << MXC_F_CLCD_REVA_CTRL_BPP_POS) /**< CTRL_BPP_BPP2 Setting */ 223 #define MXC_V_CLCD_REVA_CTRL_BPP_BPP4 ((uint32_t)0x2UL) /**< CTRL_BPP_BPP4 Value */ 224 #define MXC_S_CLCD_REVA_CTRL_BPP_BPP4 (MXC_V_CLCD_REVA_CTRL_BPP_BPP4 << MXC_F_CLCD_REVA_CTRL_BPP_POS) /**< CTRL_BPP_BPP4 Setting */ 225 #define MXC_V_CLCD_REVA_CTRL_BPP_BPP8 ((uint32_t)0x3UL) /**< CTRL_BPP_BPP8 Value */ 226 #define MXC_S_CLCD_REVA_CTRL_BPP_BPP8 (MXC_V_CLCD_REVA_CTRL_BPP_BPP8 << MXC_F_CLCD_REVA_CTRL_BPP_POS) /**< CTRL_BPP_BPP8 Setting */ 227 #define MXC_V_CLCD_REVA_CTRL_BPP_BPP16 ((uint32_t)0x4UL) /**< CTRL_BPP_BPP16 Value */ 228 #define MXC_S_CLCD_REVA_CTRL_BPP_BPP16 (MXC_V_CLCD_REVA_CTRL_BPP_BPP16 << MXC_F_CLCD_REVA_CTRL_BPP_POS) /**< CTRL_BPP_BPP16 Setting */ 229 #define MXC_V_CLCD_REVA_CTRL_BPP_BPP24 ((uint32_t)0x5UL) /**< CTRL_BPP_BPP24 Value */ 230 #define MXC_S_CLCD_REVA_CTRL_BPP_BPP24 (MXC_V_CLCD_REVA_CTRL_BPP_BPP24 << MXC_F_CLCD_REVA_CTRL_BPP_POS) /**< CTRL_BPP_BPP24 Setting */ 231 232 #define MXC_F_CLCD_REVA_CTRL_MODE565_POS 11 /**< CTRL_MODE565 Position */ 233 #define MXC_F_CLCD_REVA_CTRL_MODE565 ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_CTRL_MODE565_POS)) /**< CTRL_MODE565 Mask */ 234 #define MXC_V_CLCD_REVA_CTRL_MODE565_BGR556 ((uint32_t)0x0UL) /**< CTRL_MODE565_BGR556 Value */ 235 #define MXC_S_CLCD_REVA_CTRL_MODE565_BGR556 (MXC_V_CLCD_REVA_CTRL_MODE565_BGR556 << MXC_F_CLCD_REVA_CTRL_MODE565_POS) /**< CTRL_MODE565_BGR556 Setting */ 236 #define MXC_V_CLCD_REVA_CTRL_MODE565_RGB565 ((uint32_t)0x1UL) /**< CTRL_MODE565_RGB565 Value */ 237 #define MXC_S_CLCD_REVA_CTRL_MODE565_RGB565 (MXC_V_CLCD_REVA_CTRL_MODE565_RGB565 << MXC_F_CLCD_REVA_CTRL_MODE565_POS) /**< CTRL_MODE565_RGB565 Setting */ 238 239 #define MXC_F_CLCD_REVA_CTRL_EMODE_POS 12 /**< CTRL_EMODE Position */ 240 #define MXC_F_CLCD_REVA_CTRL_EMODE ((uint32_t)(0x3UL << MXC_F_CLCD_REVA_CTRL_EMODE_POS)) /**< CTRL_EMODE Mask */ 241 #define MXC_V_CLCD_REVA_CTRL_EMODE_LLBP ((uint32_t)0x0UL) /**< CTRL_EMODE_LLBP Value */ 242 #define MXC_S_CLCD_REVA_CTRL_EMODE_LLBP (MXC_V_CLCD_REVA_CTRL_EMODE_LLBP << MXC_F_CLCD_REVA_CTRL_EMODE_POS) /**< CTRL_EMODE_LLBP Setting */ 243 #define MXC_V_CLCD_REVA_CTRL_EMODE_BBBP ((uint32_t)0x1UL) /**< CTRL_EMODE_BBBP Value */ 244 #define MXC_S_CLCD_REVA_CTRL_EMODE_BBBP (MXC_V_CLCD_REVA_CTRL_EMODE_BBBP << MXC_F_CLCD_REVA_CTRL_EMODE_POS) /**< CTRL_EMODE_BBBP Setting */ 245 #define MXC_V_CLCD_REVA_CTRL_EMODE_LBBP ((uint32_t)0x2UL) /**< CTRL_EMODE_LBBP Value */ 246 #define MXC_S_CLCD_REVA_CTRL_EMODE_LBBP (MXC_V_CLCD_REVA_CTRL_EMODE_LBBP << MXC_F_CLCD_REVA_CTRL_EMODE_POS) /**< CTRL_EMODE_LBBP Setting */ 247 #define MXC_V_CLCD_REVA_CTRL_EMODE_RFU ((uint32_t)0x3UL) /**< CTRL_EMODE_RFU Value */ 248 #define MXC_S_CLCD_REVA_CTRL_EMODE_RFU (MXC_V_CLCD_REVA_CTRL_EMODE_RFU << MXC_F_CLCD_REVA_CTRL_EMODE_POS) /**< CTRL_EMODE_RFU Setting */ 249 250 #define MXC_F_CLCD_REVA_CTRL_C24_POS 15 /**< CTRL_C24 Position */ 251 #define MXC_F_CLCD_REVA_CTRL_C24 ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_CTRL_C24_POS)) /**< CTRL_C24 Mask */ 252 253 #define MXC_F_CLCD_REVA_CTRL_BURST_POS 19 /**< CTRL_BURST Position */ 254 #define MXC_F_CLCD_REVA_CTRL_BURST ((uint32_t)(0x3UL << MXC_F_CLCD_REVA_CTRL_BURST_POS)) /**< CTRL_BURST Mask */ 255 #define MXC_V_CLCD_REVA_CTRL_BURST_WORDS4 ((uint32_t)0x0UL) /**< CTRL_BURST_WORDS4 Value */ 256 #define MXC_S_CLCD_REVA_CTRL_BURST_WORDS4 (MXC_V_CLCD_REVA_CTRL_BURST_WORDS4 << MXC_F_CLCD_REVA_CTRL_BURST_POS) /**< CTRL_BURST_WORDS4 Setting */ 257 #define MXC_V_CLCD_REVA_CTRL_BURST_WORDS8 ((uint32_t)0x1UL) /**< CTRL_BURST_WORDS8 Value */ 258 #define MXC_S_CLCD_REVA_CTRL_BURST_WORDS8 (MXC_V_CLCD_REVA_CTRL_BURST_WORDS8 << MXC_F_CLCD_REVA_CTRL_BURST_POS) /**< CTRL_BURST_WORDS8 Setting */ 259 260 #define MXC_F_CLCD_REVA_CTRL_LPOL_POS 21 /**< CTRL_LPOL Position */ 261 #define MXC_F_CLCD_REVA_CTRL_LPOL ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_CTRL_LPOL_POS)) /**< CTRL_LPOL Mask */ 262 #define MXC_V_CLCD_REVA_CTRL_LPOL_ACTIVEHI ((uint32_t)0x0UL) /**< CTRL_LPOL_ACTIVEHI Value */ 263 #define MXC_S_CLCD_REVA_CTRL_LPOL_ACTIVEHI (MXC_V_CLCD_REVA_CTRL_LPOL_ACTIVEHI << MXC_F_CLCD_REVA_CTRL_LPOL_POS) /**< CTRL_LPOL_ACTIVEHI Setting */ 264 #define MXC_V_CLCD_REVA_CTRL_LPOL_ACTIVELO ((uint32_t)0x1UL) /**< CTRL_LPOL_ACTIVELO Value */ 265 #define MXC_S_CLCD_REVA_CTRL_LPOL_ACTIVELO (MXC_V_CLCD_REVA_CTRL_LPOL_ACTIVELO << MXC_F_CLCD_REVA_CTRL_LPOL_POS) /**< CTRL_LPOL_ACTIVELO Setting */ 266 267 #define MXC_F_CLCD_REVA_CTRL_PEN_POS 22 /**< CTRL_PEN Position */ 268 #define MXC_F_CLCD_REVA_CTRL_PEN ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_CTRL_PEN_POS)) /**< CTRL_PEN Mask */ 269 270 /**@} end of group CLCD_REVA_CTRL_Register */ 271 272 /** 273 * @ingroup clcd_reva_registers 274 * @defgroup CLCD_REVA_INT_EN CLCD_REVA_INT_EN 275 * @brief LCD Interrupt Enable Register. 276 * @{ 277 */ 278 #define MXC_F_CLCD_REVA_INT_EN_UFLO_POS 0 /**< INT_EN_UFLO Position */ 279 #define MXC_F_CLCD_REVA_INT_EN_UFLO ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_INT_EN_UFLO_POS)) /**< INT_EN_UFLO Mask */ 280 281 #define MXC_F_CLCD_REVA_INT_EN_ADRRDY_POS 1 /**< INT_EN_ADRRDY Position */ 282 #define MXC_F_CLCD_REVA_INT_EN_ADRRDY ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_INT_EN_ADRRDY_POS)) /**< INT_EN_ADRRDY Mask */ 283 284 #define MXC_F_CLCD_REVA_INT_EN_VCI_POS 2 /**< INT_EN_VCI Position */ 285 #define MXC_F_CLCD_REVA_INT_EN_VCI ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_INT_EN_VCI_POS)) /**< INT_EN_VCI Mask */ 286 287 #define MXC_F_CLCD_REVA_INT_EN_BERR_POS 3 /**< INT_EN_BERR Position */ 288 #define MXC_F_CLCD_REVA_INT_EN_BERR ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_INT_EN_BERR_POS)) /**< INT_EN_BERR Mask */ 289 290 /**@} end of group CLCD_REVA_INT_EN_Register */ 291 292 /** 293 * @ingroup clcd_reva_registers 294 * @defgroup CLCD_REVA_STAT CLCD_REVA_STAT 295 * @brief LCD Status Register. 296 * @{ 297 */ 298 #define MXC_F_CLCD_REVA_STAT_UFLO_POS 0 /**< STAT_UFLO Position */ 299 #define MXC_F_CLCD_REVA_STAT_UFLO ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_STAT_UFLO_POS)) /**< STAT_UFLO Mask */ 300 #define MXC_V_CLCD_REVA_STAT_UFLO_INACTIVE ((uint32_t)0x0UL) /**< STAT_UFLO_INACTIVE Value */ 301 #define MXC_S_CLCD_REVA_STAT_UFLO_INACTIVE (MXC_V_CLCD_REVA_STAT_UFLO_INACTIVE << MXC_F_CLCD_REVA_STAT_UFLO_POS) /**< STAT_UFLO_INACTIVE Setting */ 302 #define MXC_V_CLCD_REVA_STAT_UFLO_PENDING ((uint32_t)0x1UL) /**< STAT_UFLO_PENDING Value */ 303 #define MXC_S_CLCD_REVA_STAT_UFLO_PENDING (MXC_V_CLCD_REVA_STAT_UFLO_PENDING << MXC_F_CLCD_REVA_STAT_UFLO_POS) /**< STAT_UFLO_PENDING Setting */ 304 #define MXC_V_CLCD_REVA_STAT_UFLO_CLEAR ((uint32_t)0x1UL) /**< STAT_UFLO_CLEAR Value */ 305 #define MXC_S_CLCD_REVA_STAT_UFLO_CLEAR (MXC_V_CLCD_REVA_STAT_UFLO_CLEAR << MXC_F_CLCD_REVA_STAT_UFLO_POS) /**< STAT_UFLO_CLEAR Setting */ 306 307 #define MXC_F_CLCD_REVA_STAT_ADRRDY_POS 1 /**< STAT_ADRRDY Position */ 308 #define MXC_F_CLCD_REVA_STAT_ADRRDY ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_STAT_ADRRDY_POS)) /**< STAT_ADRRDY Mask */ 309 #define MXC_V_CLCD_REVA_STAT_ADRRDY_INACTIVE ((uint32_t)0x0UL) /**< STAT_ADRRDY_INACTIVE Value */ 310 #define MXC_S_CLCD_REVA_STAT_ADRRDY_INACTIVE (MXC_V_CLCD_REVA_STAT_ADRRDY_INACTIVE << MXC_F_CLCD_REVA_STAT_ADRRDY_POS) /**< STAT_ADRRDY_INACTIVE Setting */ 311 #define MXC_V_CLCD_REVA_STAT_ADRRDY_PENDING ((uint32_t)0x1UL) /**< STAT_ADRRDY_PENDING Value */ 312 #define MXC_S_CLCD_REVA_STAT_ADRRDY_PENDING (MXC_V_CLCD_REVA_STAT_ADRRDY_PENDING << MXC_F_CLCD_REVA_STAT_ADRRDY_POS) /**< STAT_ADRRDY_PENDING Setting */ 313 #define MXC_V_CLCD_REVA_STAT_ADRRDY_CLEAR ((uint32_t)0x1UL) /**< STAT_ADRRDY_CLEAR Value */ 314 #define MXC_S_CLCD_REVA_STAT_ADRRDY_CLEAR (MXC_V_CLCD_REVA_STAT_ADRRDY_CLEAR << MXC_F_CLCD_REVA_STAT_ADRRDY_POS) /**< STAT_ADRRDY_CLEAR Setting */ 315 316 #define MXC_F_CLCD_REVA_STAT_VCI_POS 2 /**< STAT_VCI Position */ 317 #define MXC_F_CLCD_REVA_STAT_VCI ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_STAT_VCI_POS)) /**< STAT_VCI Mask */ 318 #define MXC_V_CLCD_REVA_STAT_VCI_INACTIVE ((uint32_t)0x0UL) /**< STAT_VCI_INACTIVE Value */ 319 #define MXC_S_CLCD_REVA_STAT_VCI_INACTIVE (MXC_V_CLCD_REVA_STAT_VCI_INACTIVE << MXC_F_CLCD_REVA_STAT_VCI_POS) /**< STAT_VCI_INACTIVE Setting */ 320 #define MXC_V_CLCD_REVA_STAT_VCI_PENDING ((uint32_t)0x1UL) /**< STAT_VCI_PENDING Value */ 321 #define MXC_S_CLCD_REVA_STAT_VCI_PENDING (MXC_V_CLCD_REVA_STAT_VCI_PENDING << MXC_F_CLCD_REVA_STAT_VCI_POS) /**< STAT_VCI_PENDING Setting */ 322 #define MXC_V_CLCD_REVA_STAT_VCI_CLEAR ((uint32_t)0x1UL) /**< STAT_VCI_CLEAR Value */ 323 #define MXC_S_CLCD_REVA_STAT_VCI_CLEAR (MXC_V_CLCD_REVA_STAT_VCI_CLEAR << MXC_F_CLCD_REVA_STAT_VCI_POS) /**< STAT_VCI_CLEAR Setting */ 324 325 #define MXC_F_CLCD_REVA_STAT_BERR_POS 3 /**< STAT_BERR Position */ 326 #define MXC_F_CLCD_REVA_STAT_BERR ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_STAT_BERR_POS)) /**< STAT_BERR Mask */ 327 #define MXC_V_CLCD_REVA_STAT_BERR_INACTIVE ((uint32_t)0x0UL) /**< STAT_BERR_INACTIVE Value */ 328 #define MXC_S_CLCD_REVA_STAT_BERR_INACTIVE (MXC_V_CLCD_REVA_STAT_BERR_INACTIVE << MXC_F_CLCD_REVA_STAT_BERR_POS) /**< STAT_BERR_INACTIVE Setting */ 329 #define MXC_V_CLCD_REVA_STAT_BERR_PENDING ((uint32_t)0x1UL) /**< STAT_BERR_PENDING Value */ 330 #define MXC_S_CLCD_REVA_STAT_BERR_PENDING (MXC_V_CLCD_REVA_STAT_BERR_PENDING << MXC_F_CLCD_REVA_STAT_BERR_POS) /**< STAT_BERR_PENDING Setting */ 331 #define MXC_V_CLCD_REVA_STAT_BERR_CLEAR ((uint32_t)0x1UL) /**< STAT_BERR_CLEAR Value */ 332 #define MXC_S_CLCD_REVA_STAT_BERR_CLEAR (MXC_V_CLCD_REVA_STAT_BERR_CLEAR << MXC_F_CLCD_REVA_STAT_BERR_POS) /**< STAT_BERR_CLEAR Setting */ 333 334 #define MXC_F_CLCD_REVA_STAT_LCDIDLE_POS 8 /**< STAT_LCDIDLE Position */ 335 #define MXC_F_CLCD_REVA_STAT_LCDIDLE ((uint32_t)(0x1UL << MXC_F_CLCD_REVA_STAT_LCDIDLE_POS)) /**< STAT_LCDIDLE Mask */ 336 #define MXC_V_CLCD_REVA_STAT_LCDIDLE_BUSY ((uint32_t)0x0UL) /**< STAT_LCDIDLE_BUSY Value */ 337 #define MXC_S_CLCD_REVA_STAT_LCDIDLE_BUSY (MXC_V_CLCD_REVA_STAT_LCDIDLE_BUSY << MXC_F_CLCD_REVA_STAT_LCDIDLE_POS) /**< STAT_LCDIDLE_BUSY Setting */ 338 #define MXC_V_CLCD_REVA_STAT_LCDIDLE_READY ((uint32_t)0x1UL) /**< STAT_LCDIDLE_READY Value */ 339 #define MXC_S_CLCD_REVA_STAT_LCDIDLE_READY (MXC_V_CLCD_REVA_STAT_LCDIDLE_READY << MXC_F_CLCD_REVA_STAT_LCDIDLE_POS) /**< STAT_LCDIDLE_READY Setting */ 340 341 /**@} end of group CLCD_REVA_STAT_Register */ 342 343 /** 344 * @ingroup clcd_reva_registers 345 * @defgroup CLCD_REVA_PALETTE CLCD_REVA_PALETTE 346 * @brief Palette 347 * @{ 348 */ 349 #define MXC_F_CLCD_REVA_PALETTE_RED_POS 0 /**< PALETTE_RED Position */ 350 #define MXC_F_CLCD_REVA_PALETTE_RED ((uint32_t)(0xFFUL << MXC_F_CLCD_REVA_PALETTE_RED_POS)) /**< PALETTE_RED Mask */ 351 352 #define MXC_F_CLCD_REVA_PALETTE_GREEN_POS 8 /**< PALETTE_GREEN Position */ 353 #define MXC_F_CLCD_REVA_PALETTE_GREEN ((uint32_t)(0xFFUL << MXC_F_CLCD_REVA_PALETTE_GREEN_POS)) /**< PALETTE_GREEN Mask */ 354 355 #define MXC_F_CLCD_REVA_PALETTE_BLUE_POS 16 /**< PALETTE_BLUE Position */ 356 #define MXC_F_CLCD_REVA_PALETTE_BLUE ((uint32_t)(0xFFUL << MXC_F_CLCD_REVA_PALETTE_BLUE_POS)) /**< PALETTE_BLUE Mask */ 357 358 /**@} end of group CLCD_REVA_PALETTE_Register */ 359 360 #ifdef __cplusplus 361 } 362 #endif 363 364 #endif /* _CLCD_REVA_REGS_H_ */ 365
