1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <!-- AFE: Stacked Die --> 5 <name>AFE_HART</name> 6 <description>Analog Front End HART Registers on Stacked Die via SPI</description> 7 <baseAddress>0x4FD00000</baseAddress> 8 <addressBlock> 9 <offset>0x00</offset> 10 <size>0x200</size> 11 <usage>registers</usage> 12 </addressBlock> 13 <registers> 14 <register> 15 <name>CTRL</name> 16 <description>HART Control</description> 17 <!-- Top 2 bytes of address encodes the register address --> 18 <!-- Address \bBits 27&28 are MSB address bits, which must be written into ana_src_sel[1:0] as bank select --> 19 <!-- The HART is available at ana_src_sel[1:0] = 0b11, therefore these bits are set in all address offsets below --> 20 <!-- Bottom byte of address encodes the register width in bytes 1 - 4 (8bits to 32bits) --> 21 <!-- Due to sorting conventions of header files, address needs to be MSB --> 22 <addressOffset>0x01800003</addressOffset> 23 <fields> 24 <field> 25 <name>ADM_TM_EN</name> 26 <description>Description not included</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>1</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <name>RX_TX_CTL</name> 34 <description>Control HART Transmit and Receive Functions</description> 35 <addressOffset>0x01810003</addressOffset> 36 <fields> 37 <field> 38 <name>RX_ADC_REF_EN</name> 39 <description>Description not included</description> 40 <bitOffset>0</bitOffset> 41 <bitWidth>1</bitWidth> 42 </field> 43 <field> 44 <name>RX_ADC_REFBUF_EN</name> 45 <description>Description not included</description> 46 <bitOffset>1</bitOffset> 47 <bitWidth>1</bitWidth> 48 </field> 49 <field> 50 <name>RX_ADC_OFFSET_SEL</name> 51 <description>Description not included</description> 52 <bitOffset>2</bitOffset> 53 <bitWidth>1</bitWidth> 54 </field> 55 <field> 56 <name>RX_DOUT_UART_EN</name> 57 <description>Description not included</description> 58 <bitOffset>3</bitOffset> 59 <bitWidth>1</bitWidth> 60 </field> 61 <field> 62 <name>RX_ADC_PWR_UP_SMP_IGNR</name> 63 <description>Description not included</description> 64 <bitOffset>4</bitOffset> 65 <bitWidth>4</bitWidth> 66 </field> 67 <field> 68 <name>RX_BP_SETTLE_CNT</name> 69 <description>Description not included</description> 70 <bitOffset>8</bitOffset> 71 <bitWidth>8</bitWidth> 72 </field> 73 <field> 74 <name>RX_ADC_PWR_DLY_CNT</name> 75 <description>Description not included</description> 76 <bitOffset>16</bitOffset> 77 <bitWidth>4</bitWidth> 78 </field> 79 <field> 80 <name>TX_BUF_EN</name> 81 <description>Description not included</description> 82 <bitOffset>20</bitOffset> 83 <bitWidth>1</bitWidth> 84 </field> 85 <field> 86 <name>TX_BUS_DCL_EN</name> 87 <description>Description not included</description> 88 <bitOffset>21</bitOffset> 89 <bitWidth>1</bitWidth> 90 </field> 91 <field> 92 <name>TX_WS_DIS_RS</name> 93 <description>Description not included</description> 94 <bitOffset>22</bitOffset> 95 <bitWidth>1</bitWidth> 96 </field> 97 <field> 98 <name>TX_4MHZ_CLK_EN</name> 99 <description>Description not included</description> 100 <bitOffset>23</bitOffset> 101 <bitWidth>1</bitWidth> 102 </field> 103 </fields> 104 </register> 105 <register> 106 <name>RX_CTL_EXT1</name> 107 <description>Receive Control Extension Register 1</description> 108 <addressOffset>0x01820003</addressOffset> 109 <fields> 110 <field> 111 <name>RX_AN_INIT_VAL</name> 112 <description>Description not included</description> 113 <bitOffset>0</bitOffset> 114 <bitWidth>19</bitWidth> 115 </field> 116 </fields> 117 </register> 118 <register> 119 <name>RX_CTL_EXT2</name> 120 <description>Receive Control Extension Register 2</description> 121 <addressOffset>0x01830003</addressOffset> 122 <fields> 123 <field> 124 <name>RX_ARN_INIT_VAL</name> 125 <description>Description not included</description> 126 <bitOffset>0</bitOffset> 127 <bitWidth>15</bitWidth> 128 </field> 129 <field> 130 <name>RX_ZC_IGN_VAL</name> 131 <description>Description not included</description> 132 <bitOffset>16</bitOffset> 133 <bitWidth>2</bitWidth> 134 </field> 135 <field> 136 <name>RX_UART_TIMER_SYN_ALWS_EN</name> 137 <description>Description not included</description> 138 <bitOffset>20</bitOffset> 139 <bitWidth>1</bitWidth> 140 </field> 141 <field> 142 <name>RX_UART_TIMER_FAST_CNT_EN</name> 143 <description>Description not included</description> 144 <bitOffset>21</bitOffset> 145 <bitWidth>1</bitWidth> 146 </field> 147 </fields> 148 </register> 149 <register> 150 <name>RX_DB_THRSHLD</name> 151 <description>Receive Bit-Detect/Demodulation Threshold</description> 152 <addressOffset>0x01840003</addressOffset> 153 <fields> 154 <field> 155 <name>RX_BITDTCT_DN_THRSHLD</name> 156 <description>Description not included</description> 157 <bitOffset>0</bitOffset> 158 <bitWidth>9</bitWidth> 159 </field> 160 <field> 161 <name>RX_BITDTCT_UP_THRSHLD</name> 162 <description>Description not included</description> 163 <bitOffset>12</bitOffset> 164 <bitWidth>9</bitWidth> 165 </field> 166 </fields> 167 </register> 168 <register> 169 <name>RX_CRD_UP_THRSHLD</name> 170 <description>Receive Carrier Detect Up Threshold Register</description> 171 <addressOffset>0x01850003</addressOffset> 172 <fields> 173 <field> 174 <name>RX_CRD_UP_THRSHLD</name> 175 <description>Description not included</description> 176 <bitOffset>0</bitOffset> 177 <bitWidth>19</bitWidth> 178 </field> 179 </fields> 180 </register> 181 <register> 182 <name>RX_CRD_DN_THRSHLD</name> 183 <description>Receive Carrier Detect Down Threshold Register</description> 184 <addressOffset>0x01860003</addressOffset> 185 <fields> 186 <field> 187 <name>RX_CRD_DN_THRSHLD</name> 188 <description>Description not included</description> 189 <bitOffset>0</bitOffset> 190 <bitWidth>19</bitWidth> 191 </field> 192 </fields> 193 </register> 194 <register> 195 <name>RX_CRD_DOUT_THRSHLD</name> 196 <description>Receive Carrier Detect DOUT Threshold</description> 197 <addressOffset>0x01870003</addressOffset> 198 <fields> 199 <field> 200 <name>RX_CRD_DOUT_THRSHLD</name> 201 <description>Description not included</description> 202 <bitOffset>0</bitOffset> 203 <bitWidth>19</bitWidth> 204 </field> 205 </fields> 206 </register> 207 <register> 208 <name>TX_MARKSPACE_CNT</name> 209 <description>Transmit Mark-Space Count Values</description> 210 <addressOffset>0x01880003</addressOffset> 211 <fields> 212 <field> 213 <name>TX_SPACE_CNT</name> 214 <description>Description not included</description> 215 <bitOffset>0</bitOffset> 216 <bitWidth>10</bitWidth> 217 </field> 218 <field> 219 <name>TX_MARK_CNT</name> 220 <description>Description not included</description> 221 <bitOffset>12</bitOffset> 222 <bitWidth>10</bitWidth> 223 </field> 224 </fields> 225 </register> 226 <register> 227 <name>STAT</name> 228 <description>Status Register</description> 229 <addressOffset>0x01890003</addressOffset> 230 </register> 231 <register> 232 <name>TRIM</name> 233 <description>HART Trim Register</description> 234 <addressOffset>0x018A0003</addressOffset> 235 <fields> 236 <field> 237 <name>TRIM_BIAS</name> 238 <description>Description not included</description> 239 <bitOffset>0</bitOffset> 240 <bitWidth>5</bitWidth> 241 </field> 242 <field> 243 <name>TRIM_BG</name> 244 <description>Description not included</description> 245 <bitOffset>8</bitOffset> 246 <bitWidth>6</bitWidth> 247 </field> 248 <field> 249 <name>TRIM_TX_SR</name> 250 <description>Description not included</description> 251 <bitOffset>16</bitOffset> 252 <bitWidth>4</bitWidth> 253 </field> 254 </fields> 255 </register> 256 <register> 257 <name>TM</name> 258 <description>Testmode</description> 259 <addressOffset>0x018B0003</addressOffset> 260 <fields> 261 <field> 262 <name>TM_EN</name> 263 <description>Description not included</description> 264 <bitOffset>0</bitOffset> 265 <bitWidth>1</bitWidth> 266 </field> 267 <field> 268 <name>TM_BIAS_EN</name> 269 <description>Description not included</description> 270 <bitOffset>1</bitOffset> 271 <bitWidth>1</bitWidth> 272 </field> 273 <field> 274 <name>TM_BG_EN</name> 275 <description>Description not included</description> 276 <bitOffset>3</bitOffset> 277 <bitWidth>1</bitWidth> 278 </field> 279 <field> 280 <name>TM_VREF_EN</name> 281 <description>Description not included</description> 282 <bitOffset>3</bitOffset> 283 <bitWidth>1</bitWidth> 284 </field> 285 </fields> 286 </register> 287 </registers> 288 </peripheral> 289 <!-- AFE: Stacked Die --> 290</device>
