1 /** 2 * @file 3 * @brief Serial Peripheral Interface (SPI) communications driver. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2025 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_SPI_H_ 26 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_SPI_H_ 27 28 /***** includes *******/ 29 #include <stdbool.h> 30 #include "spi_regs.h" 31 #include "mxc_sys.h" 32 #include "mxc_assert.h" 33 #include "gpio.h" 34 #include "mxc_pins.h" 35 #include "mxc_lock.h" 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 /** 42 * @defgroup spi SPI 43 * @ingroup periphlibs 44 * @{ 45 */ 46 47 /***** Definitions *****/ 48 49 /** 50 * @brief The list of SPI Widths supported 51 * 52 * The SPI Width can be set on a per-transaction basis. 53 * An example use case of SPI_WIDTH_STANDARD_HALFDUPLEX is 54 * given. 55 * 56 * Using a MAX31865 RTD-to-SPI IC, read back the temperature 57 * The IC requires a SPI Read to be executed as 58 * 1. Assert SS 59 * 2. Write an 8bit register address 60 * 3. Read back the 8 bit register 61 * 4. Deassert SS 62 * This can be accomplished with the STANDARD_HALFDUPLEX width 63 * 1. set txData to the address, txLen=1 64 * 2. set rxData to a buffer of 1 byte, rxLen=1 65 * 3. The driver will transmit the txData, and after completion of 66 * txData begin to recieve data, padding MOSI with DefaultTXData 67 * 68 */ 69 typedef enum { 70 SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex 71 SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex 72 SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex 73 SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex 74 } mxc_spi_width_t; 75 76 /** 77 * @brief The list of SPI modes 78 * 79 * SPI supports four combinations of clock and phase polarity 80 * 81 * Clock polarity is controlled using the bit SPIn_CTRL2.cpol 82 * and determines if the clock is active high or active low 83 * 84 * Clock phase determines when the data must be stable for sampling 85 * 86 */ 87 typedef enum { 88 SPI_MODE_0, ///< clock phase = 0, clock polarity = 0 89 SPI_MODE_1, ///< clock phase = 0, clock polarity = 1 90 SPI_MODE_2, ///< clock phase = 1, clock polarity = 0 91 SPI_MODE_3, ///< clock phase = 1, clock polarity = 1 92 } mxc_spi_mode_t; 93 94 typedef struct _mxc_spi_pins_t mxc_spi_pins_t; 95 96 /** 97 * @brief Structure used to initialize SPI pins. 98 * 99 * @note All values must be initialized. 100 * 101 * @note True equals pin is set for the spi function false the pin is left to its latest state. 102 */ 103 struct _mxc_spi_pins_t { 104 bool clock; ///<Clock pin 105 bool ss0; ///< Slave select pin 0 106 bool ss1; ///< Slave select pin 1 107 bool ss2; ///< Slave select pin 2 108 bool miso; ///< miso pin 109 bool mosi; ///< mosi pin 110 bool sdio2; ///< SDIO2 pin 111 bool sdio3; ///< SDIO3 pin 112 bool vddioh; ///< VDDIOH Select 113 }; 114 115 typedef struct _mxc_spi_req_t mxc_spi_req_t; 116 /** 117 * @brief The callback routine used to indicate the transaction has terminated. 118 * 119 * @param req The details of the transaction. 120 * @param result See \ref MXC_Error_Codes for the list of error codes. 121 */ 122 typedef void (*spi_complete_cb_t)(void *req, int result); 123 124 /** 125 * @brief The information required to perform a complete SPI transaction 126 * 127 * This structure is used by blocking, async, and DMA based transactions. 128 * @note "completeCB" only needs to be initialized for interrupt driven (Async) and DMA transactions. 129 */ 130 struct _mxc_spi_req_t { 131 mxc_spi_regs_t *spi; ///<Point to SPI registers 132 int ssIdx; ///< Slave select line to use (Master only, ignored in slave mode) 133 int ssDeassert; ///< 1 - Deassert SS at end of transaction, 0 - leave SS asserted 134 uint8_t *txData; ///< Buffer containing transmit data. For character sizes 135 ///< < 8 bits, pad the MSB of each byte with zeros. For 136 ///< character sizes > 8 bits, use two bytes per character 137 ///< and pad the MSB of the upper byte with zeros 138 uint8_t *rxData; ///< Buffer to store received data For character sizes 139 ///< < 8 bits, pad the MSB of each byte with zeros. For 140 ///< character sizes > 8 bits, use two bytes per character 141 ///< and pad the MSB of the upper byte with zeros 142 uint32_t txLen; ///< Number of bytes to be sent from txData 143 uint32_t rxLen; ///< Number of bytes to be stored in rxData 144 uint32_t txCnt; ///< Number of bytes actually transmitted from txData 145 uint32_t rxCnt; ///< Number of bytes stored in rxData 146 147 spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete 148 }; 149 150 /* ************************************************************************* */ 151 /* Control/Configuration functions */ 152 /* ************************************************************************* */ 153 154 /** 155 * @brief Initialize and enable SPI peripheral. 156 * 157 * This function initializes everything necessary to call a SPI transaction function. 158 * Some parameters are set to defaults as follows: 159 * SPI Mode - 0 160 * SPI Width - SPI_WIDTH_STANDARD (even if quadModeUsed is set) 161 * 162 * These parameters can be modified after initialization using low level functions 163 * 164 * @param spi Pointer to SPI registers (selects the SPI block used.) 165 * @param masterMode Whether to put the device in master or slave mode. Use 166 * non-zero for master mode, and zero for slave mode. 167 * @param quadModeUsed Whether to obtain control of the SDIO2/3 pins. Use 168 * non-zero if the pins are needed (if Quad Mode will 169 * be used), and zero if they are not needed (quad mode 170 * will never be used). 171 * @param numSlaves The number of slaves used, if in master mode. This 172 * is used to obtain control of the necessary SS pins. 173 * In slave mode this is ignored and SS1 is used. 174 * @param ssPolarity This field sets the SS active polarity for each 175 * slave, each bit position corresponds to each SS line. 176 * @param hz The requested clock frequency. The actual clock frequency 177 * will be returned by the function if successful. Used in 178 * master mode only. 179 * @param pins SPI pin structure. Pins selected as true will be initialized 180 * for the requested SPI block. 181 * 182 * @return If successful, the actual clock frequency is returned. Otherwise, see 183 * \ref MXC_Error_Codes for a list of return codes. 184 */ 185 int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, 186 unsigned ssPolarity, unsigned int hz, mxc_spi_pins_t pins); 187 188 /** 189 * @brief Disable and shutdown SPI peripheral. 190 * 191 * @param spi Pointer to SPI registers (selects the SPI block used.) 192 * 193 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 194 */ 195 int MXC_SPI_Shutdown(mxc_spi_regs_t *spi); 196 197 /** 198 * @brief Checks if the given SPI bus can be placed in sleep mode. 199 * 200 * This functions checks to see if there are any on-going SPI transactions in 201 * progress. If there are transactions in progress, the application should 202 * wait until the SPI bus is free before entering a low-power state. 203 * 204 * @param spi Pointer to SPI registers (selects the SPI block used.) 205 * 206 * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref 207 * MXC_Error_Codes for the list of error return codes. 208 */ 209 int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi); 210 211 /** 212 * @brief Returns the frequency of the clock used as the bit rate generator for a given SPI instance. 213 * 214 * @param spi Pointer to SPI registers (selects the SPI block used.) 215 * 216 * @return Frequency of the clock used as the bit rate generator 217 */ 218 int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi); 219 220 /** 221 * @brief Set the frequency of the SPI interface. 222 * 223 * This function is applicable in Master mode only 224 * 225 * @param spi Pointer to SPI registers (selects the SPI block used.) 226 * @param hz The desired frequency in Hertz. 227 * 228 * @return Negative if error, otherwise actual speed set. See \ref 229 * MXC_Error_Codes for the list of error return codes. 230 */ 231 int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz); 232 233 /** 234 * @brief Get the frequency of the SPI interface. 235 * 236 * This function is applicable in Master mode only 237 * 238 * @param spi Pointer to SPI registers (selects the SPI block used.) 239 * 240 * @return The SPI bus frequency in Hertz 241 */ 242 unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi); 243 244 /** 245 * @brief Sets the number of bits per character 246 * 247 * @param spi Pointer to SPI registers (selects the SPI block used.) 248 * @param dataSize The number of bits per character 249 * 250 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 251 */ 252 int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize); 253 254 /** 255 * @brief Gets the number of bits per character 256 * 257 * @param spi Pointer to SPI registers (selects the SPI block used.) 258 * 259 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 260 */ 261 int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi); 262 263 /* ************************************************************************* */ 264 /* Low-level functions */ 265 /* ************************************************************************* */ 266 267 /** 268 * @brief Sets the slave select (SS) line used for transmissions 269 * 270 * This function is applicable in Master mode only 271 * 272 * @param spi Pointer to SPI registers (selects the SPI block used.) 273 * @param ssIdx Slave select index 274 * 275 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 276 */ 277 int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx); 278 279 /** 280 * @brief Gets the slave select (SS) line used for transmissions 281 * 282 * This function is applicable in Master mode only 283 * 284 * @param spi Pointer to SPI registers (selects the SPI block used.) 285 * 286 * @return slave slect 287 */ 288 int MXC_SPI_GetSlave(mxc_spi_regs_t *spi); 289 290 /** 291 * @brief Sets the SPI width used for transmissions 292 * 293 * @param spi Pointer to SPI registers (selects the SPI block used.) 294 * @param spiWidth SPI Width (3-Wire, Standard, Dual SPI, Quad SPI) 295 * 296 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 297 */ 298 int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth); 299 300 /** 301 * @brief Gets the SPI width used for transmissions 302 * 303 * @param spi Pointer to SPI registers (selects the SPI block used.) 304 * 305 * @return Spi Width 306 */ 307 mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi); 308 309 /** 310 * @brief Sets the spi mode using clock polarity and clock phase 311 * 312 * @param spi Pointer to SPI registers (selects the SPI block used.) 313 * @param spiMode \ref mxc_spi_mode_t 314 * 315 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 316 */ 317 int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode); 318 319 /** 320 * @brief Gets the spi mode 321 * 322 * @param spi Pointer to SPI registers (selects the SPI block used.) 323 * 324 * @return mxc_spi_mode_t \ref mxc_spi_mode_t 325 */ 326 mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi); 327 328 /** 329 * @brief Starts a SPI Transmission 330 * 331 * This function is applicable in Master mode only 332 * 333 * The user must ensure that there are no ongoing transmissions before 334 * calling this function 335 * 336 * @param spi Pointer to SPI registers (selects the SPI block used.) 337 * 338 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 339 */ 340 int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi); 341 342 /** 343 * @brief Checks the SPI Peripheral for an ongoing transmission 344 * 345 * This function is applicable in Master mode only 346 * 347 * @param spi Pointer to SPI registers (selects the SPI block used.) 348 * 349 * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. 350 */ 351 int MXC_SPI_GetActive(mxc_spi_regs_t *spi); 352 353 /** 354 * @brief Aborts an ongoing SPI Transmission 355 * 356 * This function is applicable in Master mode only 357 * 358 * @param spi Pointer to SPI registers (selects the SPI block used.) 359 * 360 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 361 */ 362 int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi); 363 364 /** 365 * @brief Unloads bytes from the receive FIFO. 366 * 367 * @param spi Pointer to SPI registers (selects the SPI block used.) 368 * @param bytes The buffer to read the data into. 369 * @param len The number of bytes to read. 370 * 371 * @return The number of bytes actually read. 372 */ 373 unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); 374 375 /** 376 * @brief Get the number of bytes currently available in the receive FIFO. 377 * 378 * @param spi Pointer to SPI registers (selects the SPI block used.) 379 * 380 * @return The number of bytes available. 381 */ 382 unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi); 383 384 /** 385 * @brief Loads bytes into the transmit FIFO. 386 * 387 * @param spi Pointer to SPI registers (selects the SPI block used.) 388 * @param bytes The buffer containing the bytes to write 389 * @param len The number of bytes to write. 390 * 391 * @return The number of bytes actually written. 392 */ 393 unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); 394 395 /** 396 * @brief Get the amount of free space available in the transmit FIFO. 397 * 398 * @param spi Pointer to SPI registers (selects the SPI block used.) 399 * 400 * @return The number of bytes available. 401 */ 402 unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi); 403 404 /** 405 * @brief Removes and discards all bytes currently in the receive FIFO. 406 * 407 * @param spi Pointer to SPI registers (selects the SPI block used.) 408 */ 409 void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi); 410 411 /** 412 * @brief Removes and discards all bytes currently in the transmit FIFO. 413 * 414 * @param spi Pointer to SPI registers (selects the SPI block used.) 415 */ 416 void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); 417 418 /** 419 * @brief Set the receive threshold level. 420 * 421 * RX FIFO Receive threshold. Smaller values will cause 422 * interrupts to occur more often, but reduce the possibility 423 * of losing data because of a FIFO overflow. Larger values 424 * will reduce the time required by the ISR, but increase the 425 * possibility of data loss. Passing an invalid value will 426 * cause the driver to use the value already set in the 427 * appropriate register. 428 * 429 * @param spi Pointer to SPI registers (selects the SPI block used.) 430 * @param numBytes The threshold level to set. This value must be 431 * between 0 and 8 inclusive. 432 * 433 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 434 */ 435 int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); 436 437 /** 438 * @brief Get the current receive threshold level. 439 * 440 * @param spi Pointer to SPI registers (selects the SPI block used.) 441 * 442 * @return The receive threshold value (in bytes). 443 */ 444 unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); 445 446 /** 447 * @brief Set the transmit threshold level. 448 * 449 * TX FIFO threshold. Smaller values will cause interrupts 450 * to occur more often, but reduce the possibility of terminating 451 * a transaction early in master mode, or transmitting invalid data 452 * in slave mode. Larger values will reduce the time required by 453 * the ISR, but increase the possibility errors occurring. Passing 454 * an invalid value will cause the driver to use the value already 455 * set in the appropriate register. 456 * 457 * @param spi Pointer to SPI registers (selects the SPI block used.) 458 * @param numBytes The threshold level to set. This value must be 459 * between 0 and 8 inclusive. 460 * 461 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 462 */ 463 int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); 464 465 /** 466 * @brief Get the current transmit threshold level. 467 * 468 * @param spi Pointer to SPI registers (selects the SPI block used.) 469 * 470 * @return The transmit threshold value (in bytes). 471 */ 472 unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); 473 474 /** 475 * @brief Gets the interrupt flags that are currently set 476 * 477 * These functions should not be used while using non-blocking Transaction Level 478 * functions (Async or DMA) 479 * 480 * @param spi Pointer to SPI registers (selects the SPI block used.) 481 * 482 * @return The interrupt flags 483 */ 484 unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi); 485 486 /** 487 * @brief Clears the interrupt flags that are currently set 488 * 489 * These functions should not be used while using non-blocking Transaction Level 490 * functions (Async or DMA) 491 * 492 * @param spi Pointer to SPI registers (selects the SPI block used.) 493 * 494 */ 495 void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi); 496 497 /** 498 * @brief Enables specific interrupts 499 * 500 * These functions should not be used while using non-blocking Transaction Level 501 * functions (Async or DMA) 502 * 503 * @param spi Pointer to SPI registers (selects the SPI block used.) 504 * @param intEn The interrupts to be enabled 505 */ 506 void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int intEn); 507 508 /** 509 * @brief Disables specific interrupts 510 * 511 * These functions should not be used while using non-blocking Transaction Level 512 * functions (Async or DMA) 513 * 514 * @param spi Pointer to SPI registers (selects the SPI block used.) 515 * @param intDis The interrupts to be disabled 516 */ 517 void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int intDis); 518 519 /* ************************************************************************* */ 520 /* Transaction level functions */ 521 /* ************************************************************************* */ 522 523 /** 524 * @brief Performs a blocking SPI transaction. 525 * 526 * Performs a blocking SPI transaction. 527 * These actions will be performed in Master Mode: 528 * 1. Assert the specified SS 529 * 2. In Full Duplex Modes, send TX data while receiving RX Data 530 * if rxLen > txLen, pad txData with DefaultTXData 531 * if txLen > rxLen, discard rxData where rxCnt > rxLen 532 * 3. In Half Duplex Modes, send TX Data, then receive RX Data 533 * 4. Deassert the specified SS 534 * 535 * These actions will be performed in Slave Mode: 536 * 1. Fill FIFO with txData 537 * 2. Wait for SS Assert 538 * 3. If needed, pad txData with DefaultTXData 539 * 4. Unload RX FIFO as needed 540 * 5. On SS Deassert, return 541 * 542 * @param req Pointer to details of the transaction 543 * 544 * @return See \ref MXC_Error_Codes for the list of error return codes. 545 */ 546 int MXC_SPI_MasterTransaction(mxc_spi_req_t *req); 547 548 /** 549 * @brief Setup an interrupt-driven SPI transaction 550 * 551 * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary 552 * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) 553 * 554 * @param req Pointer to details of the transaction 555 * 556 * @return See \ref MXC_Error_Codes for the list of error return codes. 557 */ 558 int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req); 559 560 /** 561 * @brief Setup a DMA driven SPI transaction 562 * 563 * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary 564 * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) 565 * 566 * The lowest-indexed unused DMA channel will be acquired (using the DMA API) and 567 * set up to load/unload the FIFOs with as few interrupt-based events as 568 * possible. The channel will be reset and returned to the system at the end of 569 * the transaction. 570 * 571 * @param req Pointer to details of the transaction 572 * 573 * @return See \ref MXC_Error_Codes for the list of error return codes. 574 */ 575 int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req); 576 577 /** 578 * @brief Performs a blocking SPI transaction. 579 * 580 * Performs a blocking SPI transaction. 581 * These actions will be performed in Slave Mode: 582 * 1. Fill FIFO with txData 583 * 2. Wait for SS Assert 584 * 3. If needed, pad txData with DefaultTXData 585 * 4. Unload RX FIFO as needed 586 * 5. On SS Deassert, return 587 * 588 * @param req Pointer to details of the transaction 589 * 590 * @return See \ref MXC_Error_Codes for the list of error return codes. 591 */ 592 int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req); 593 594 /** 595 * @brief Setup an interrupt-driven SPI transaction 596 * 597 * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary 598 * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) 599 * 600 * @param req Pointer to details of the transactionz 601 * 602 * @return See \ref MXC_Error_Codes for the list of error return codes. 603 */ 604 int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req); 605 606 /** 607 * @brief Setup a DMA driven SPI transaction 608 * 609 * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary 610 * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) 611 * 612 * The lowest-indexed unused DMA channel will be acquired (using the DMA API) and 613 * set up to load/unload the FIFOs with as few interrupt-based events as 614 * possible. The channel will be reset and returned to the system at the end of 615 * the transaction. 616 * 617 * @param req Pointer to details of the transaction 618 * 619 * @return See \ref MXC_Error_Codes for the list of error return codes. 620 */ 621 int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req); 622 623 /** 624 * @brief Sets the TX data to transmit as a 'dummy' byte 625 * 626 * In single wire master mode, this data is transmitted on MOSI when performing 627 * an RX (MISO) only transaction. This defaults to 0. 628 * 629 * @param spi Pointer to SPI registers (selects the SPI block used.) 630 * @param defaultTXData Data to shift out in RX-only transactions 631 * 632 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 633 */ 634 int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData); 635 636 /** 637 * @brief Abort any asynchronous requests in progress. 638 * 639 * Abort any asynchronous requests in progress. Any callbacks associated with 640 * the active transaction will be executed to indicate when the transaction 641 * has been terminated. 642 * 643 * @param spi Pointer to SPI registers (selects the SPI block used.) 644 */ 645 void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi); 646 647 /** 648 * @brief The processing function for asynchronous transactions. 649 * 650 * When using the asynchronous functions, the application must call this 651 * function periodically. This can be done from within the SPI interrupt 652 * handler or periodically by the application if SPI interrupts are disabled. 653 * 654 * @param spi Pointer to SPI registers (selects the SPI block used.) 655 */ 656 void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi); 657 658 /** 659 * @brief Enable/Disable HW CS control feature. 660 * 661 * Depending on the application, the user might need to manually drive the slave select pin. 662 * The SPI driver automatically drives the SS pin and this function enables/disables this 663 * feature. 664 * 665 * @param spi Pointer to SPI registers (selects the SPI block used.) 666 * @param state Non-zero values: enable HW SS mode. Zero: disable HW SS mode. 667 */ 668 void MXC_SPI_HWSSControl(mxc_spi_regs_t *spi, int state); 669 /**@} end of group spi */ 670 671 #ifdef __cplusplus 672 } 673 #endif 674 675 #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_SPI_H_ 676
