1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 /**
22 * @file mxc_sys.h
23 * @brief System level header file.
24 */
25
26 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_MXC_SYS_H_
27 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_MXC_SYS_H_
28
29 #include "mxc_device.h"
30 #include "lpgcr_regs.h"
31 #include "gcr_regs.h"
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 /**
38 * @defgroup mxc_sys System Configuration (MXC_SYS)
39 * @ingroup syscfg
40 * @details API for system configuration including clock source selection and entering critical sections of code.
41 * @{
42 */
43
44 /** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */
45 typedef enum {
46 MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */
47 MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */
48 MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */
49 MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS, /**< Reset GPIO1 */
50 MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, /**< Reset TMR0 */
51 MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS, /**< Reset TMR1 */
52 MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS, /**< Reset TMR2 */
53 MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS, /**< Reset TMR3 */
54 MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */
55 MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */
56 MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */
57 MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */
58 MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */
59 MXC_SYS_RESET0_SMPHR = MXC_F_GCR_RST0_SMPHR_POS, /**< Reset SMPHR */
60 MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */
61 MXC_SYS_RESET0_CNN = MXC_F_GCR_RST0_CNN_POS, /**< Reset CNN */
62 MXC_SYS_RESET0_ADC = MXC_F_GCR_RST0_ADC_POS, /**< Reset ADC */
63 MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS, /**< Reset UART2 */
64 MXC_SYS_RESET0_SOFT = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */
65 MXC_SYS_RESET0_PERIPH = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */
66 MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, /**< System reset */
67 /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
68 MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */
69 MXC_SYS_RESET1_PT = (MXC_F_GCR_RST1_PT_POS + 32), /**< Reset PT */
70 MXC_SYS_RESET1_OWM = (MXC_F_GCR_RST1_OWM_POS + 32), /**< Reset OWM */
71 MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset CRC */
72 MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset AES */
73 MXC_SYS_RESET1_SMPHR = (MXC_F_GCR_RST1_SMPHR_POS + 32), /**< Reset SMPHR */
74 MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset I2C2 */
75 MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset I2S*/
76 MXC_SYS_RESET1_DVS = (MXC_F_GCR_RST1_DVS_POS + 32), /**< Reset DVS */
77 MXC_SYS_RESET1_SIMO = (MXC_F_GCR_RST1_SIMO_POS + 32), /**< Reset SIMO */
78 MXC_SYS_RESET1_SPI0 = (MXC_F_GCR_RST1_SPI0_POS + 32), /**< Reset SPI0 */
79 MXC_SYS_RESET1_CPU1 = (MXC_F_GCR_RST1_CPU1_POS + 32), /**< Reset CPU1 */
80 /* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */
81 MXC_SYS_RESET_GPIO2 = (MXC_F_LPGCR_RST_GPIO2_POS + 64), /**< Reset GPIO2 */
82 MXC_SYS_RESET_WDT1 = (MXC_F_LPGCR_RST_WDT1_POS + 64), /**< Reset WDT1 */
83 MXC_SYS_RESET_TMR4 = (MXC_F_LPGCR_RST_TMR4_POS + 64), /**< Reset TMR4 */
84 MXC_SYS_RESET_TMR5 = (MXC_F_LPGCR_RST_TMR5_POS + 64), /**< Reset TMR5 */
85 MXC_SYS_RESET_UART3 = (MXC_F_LPGCR_RST_UART3_POS + 64), /**< Reset UART3 */
86 MXC_SYS_RESET_LPCOMP = (MXC_F_LPGCR_RST_LPCOMP_POS + 64), /**< Reset LPCOMP */
87 } mxc_sys_reset_t;
88
89 /** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */
90 typedef enum {
91 MXC_SYS_PERIPH_CLOCK_GPIO0 =
92 MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
93 MXC_SYS_PERIPH_CLOCK_GPIO1 =
94 MXC_F_GCR_PCLKDIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */
95 MXC_SYS_PERIPH_CLOCK_DMA =
96 MXC_F_GCR_PCLKDIS0_DMA_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
97 MXC_SYS_PERIPH_CLOCK_SPI1 =
98 MXC_F_GCR_PCLKDIS0_SPI1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
99 MXC_SYS_PERIPH_CLOCK_UART0 =
100 MXC_F_GCR_PCLKDIS0_UART0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
101 MXC_SYS_PERIPH_CLOCK_UART1 =
102 MXC_F_GCR_PCLKDIS0_UART1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
103 MXC_SYS_PERIPH_CLOCK_I2C0 =
104 MXC_F_GCR_PCLKDIS0_I2C0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
105 MXC_SYS_PERIPH_CLOCK_TMR0 =
106 MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR0 clock */
107 MXC_SYS_PERIPH_CLOCK_TMR1 =
108 MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR1 clock */
109 MXC_SYS_PERIPH_CLOCK_TMR2 =
110 MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR2 clock */
111 MXC_SYS_PERIPH_CLOCK_TMR3 =
112 MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */
113 MXC_SYS_PERIPH_CLOCK_ADC =
114 MXC_F_GCR_PCLKDIS0_ADC_POS, /**< Disable MXC_F_GCR_PCLKDIS0_ADC clock */
115 MXC_SYS_PERIPH_CLOCK_CNN =
116 MXC_F_GCR_PCLKDIS0_CNN_POS, /**< Disable MXC_F_GCR_PCLKDIS0_CNN clock */
117 MXC_SYS_PERIPH_CLOCK_I2C1 =
118 MXC_F_GCR_PCLKDIS0_I2C1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
119 MXC_SYS_PERIPH_CLOCK_PT = MXC_F_GCR_PCLKDIS0_PT_POS, /**< Disable MXC_F_GCR_PCLKDIS0_PT clock */
120 /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
121 MXC_SYS_PERIPH_CLOCK_UART2 =
122 (MXC_F_GCR_PCLKDIS1_UART2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */
123 MXC_SYS_PERIPH_CLOCK_TRNG =
124 (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */
125 MXC_SYS_PERIPH_CLOCK_SMPHR =
126 (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SMPHR clock */
127 MXC_SYS_PERIPH_CLOCK_OWIRE =
128 (MXC_F_GCR_PCLKDIS1_OWM_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_OWM clock */
129 MXC_SYS_PERIPH_CLOCK_CRC =
130 (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CRC clock */
131 MXC_SYS_PERIPH_CLOCK_AES =
132 (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_AES clock */
133 MXC_SYS_PERIPH_CLOCK_I2S =
134 (MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
135 MXC_SYS_PERIPH_CLOCK_SPI0 =
136 (MXC_F_GCR_PCLKDIS1_SPI0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SPI0 clock */
137 MXC_SYS_PERIPH_CLOCK_PCIF =
138 (MXC_F_GCR_PCLKDIS1_PCIF_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_PCIF clock */
139 MXC_SYS_PERIPH_CLOCK_I2C2 =
140 (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */
141 MXC_SYS_PERIPH_CLOCK_WDT0 =
142 (MXC_F_GCR_PCLKDIS1_WDT0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */
143 MXC_SYS_PERIPH_CLOCK_CPU1 =
144 (MXC_F_GCR_PCLKDIS1_CPU1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CPU1 clock */
145 /* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */
146 MXC_SYS_PERIPH_CLOCK_GPIO2 =
147 (MXC_F_LPGCR_PCLKDIS_GPIO2_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_GPIO2 clock */
148 MXC_SYS_PERIPH_CLOCK_WDT1 =
149 (MXC_F_LPGCR_PCLKDIS_WDT1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_WDT2 clock */
150 MXC_SYS_PERIPH_CLOCK_TMR4 =
151 (MXC_F_LPGCR_PCLKDIS_TMR4_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */
152 MXC_SYS_PERIPH_CLOCK_TMR5 =
153 (MXC_F_LPGCR_PCLKDIS_TMR5_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */
154 MXC_SYS_PERIPH_CLOCK_UART3 =
155 (MXC_F_LPGCR_PCLKDIS_UART3_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */
156 MXC_SYS_PERIPH_CLOCK_LPCOMP =
157 (MXC_F_LPGCR_PCLKDIS_LPCOMP_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_LPCOMP clock */
158 } mxc_sys_periph_clock_t;
159
160 /** @brief Enumeration to select System Clock source */
161 typedef enum {
162 MXC_SYS_CLOCK_IPO =
163 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO, /**< Select the Internal Primary Oscillator (IPO) */
164 MXC_SYS_CLOCK_IBRO =
165 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO, /**< Select the Internal Baud Rate Oscillator (IBRO) */
166 MXC_SYS_CLOCK_ISO =
167 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO, /**< Select the Internal Secondary Oscillator (ISO) */
168 MXC_SYS_CLOCK_INRO =
169 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO, /**< Select the Internal Nanoring Oscillator (INRO) */
170 MXC_SYS_CLOCK_ERTCO =
171 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO, /**< Select the External RTC Crystal Oscillator */
172 MXC_SYS_CLOCK_EXTCLK =
173 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK /**< Use the external system clock input */
174 } mxc_sys_system_clock_t;
175
176 /** @brief Enumeration to set the System Clock divider */
177 typedef enum {
178 MXC_SYS_CLOCK_DIV_1 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1,
179 MXC_SYS_CLOCK_DIV_2 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2,
180 MXC_SYS_CLOCK_DIV_4 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4,
181 MXC_SYS_CLOCK_DIV_8 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8,
182 MXC_SYS_CLOCK_DIV_16 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16,
183 MXC_SYS_CLOCK_DIV_32 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32,
184 MXC_SYS_CLOCK_DIV_64 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64,
185 MXC_SYS_CLOCK_DIV_128 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128
186 } mxc_sys_system_clock_div_t;
187
188 #define MXC_SYS_USN_CHECKSUM_LEN 16 // Length of the USN + padding for checksum compute
189 #define MXC_SYS_USN_CSUM_FIELD_LEN 2 // Size of the checksum field in the USN
190 #define MXC_SYS_USN_LEN 13 // Size of the USN including the checksum
191
192 /***** Function Prototypes *****/
193
194 typedef struct {
195 int ie_status;
196 int in_critical;
197 } mxc_crit_state_t;
198
199 static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 };
200
_mxc_crit_get_state(void)201 static inline void _mxc_crit_get_state(void)
202 {
203 #ifndef __riscv
204 /*
205 On ARM M the 0th bit of the Priority Mask register indicates
206 whether interrupts are enabled or not.
207
208 0 = enabled
209 1 = disabled
210 */
211 uint32_t primask = __get_PRIMASK();
212 _state.ie_status = (primask == 0);
213 #else
214 /*
215 On RISC-V bit position 3 (Machine Interrupt Enable) of the
216 mstatus register indicates whether interrupts are enabled.
217
218 0 = disabled
219 1 = enabled
220 */
221 uint32_t mstatus = get_mstatus();
222 _state.ie_status = ((mstatus & (1 << 3)) != 0);
223 #endif
224 }
225
226 /**
227 * @brief Enter a critical section of code that cannot be interrupted. Call @ref MXC_SYS_Crit_Exit to exit the critical section.
228 * @details Ex:
229 * @code
230 * MXC_SYS_Crit_Enter();
231 * printf("Hello critical section!\n");
232 * MXC_SYS_Crit_Exit();
233 * @endcode
234 * The @ref MXC_CRITICAL macro is also provided as a convencience macro for wrapping a code section in this way.
235 * @returns None
236 */
MXC_SYS_Crit_Enter(void)237 static inline void MXC_SYS_Crit_Enter(void)
238 {
239 _mxc_crit_get_state();
240 if (_state.ie_status)
241 __disable_irq();
242 _state.in_critical = 1;
243 }
244
245 /**
246 * @brief Exit a critical section of code from @ref MXC_SYS_Crit_Enter
247 * @returns None
248 */
MXC_SYS_Crit_Exit(void)249 static inline void MXC_SYS_Crit_Exit(void)
250 {
251 if (_state.ie_status) {
252 __enable_irq();
253 }
254 _state.in_critical = 0;
255 _mxc_crit_get_state();
256 /*
257 ^ Reset the state again to prevent edge case
258 where interrupts get disabled, then Crit_Exit() gets
259 called, which would inadvertently re-enable interrupts
260 from old state.
261 */
262 }
263
264 /**
265 * @brief Polls whether code is currently executing from a critical section.
266 * @returns 1 if code is currently in a critical section (interrupts are disabled).
267 * 0 if code is not in a critical section.
268 */
MXC_SYS_In_Crit_Section(void)269 static inline int MXC_SYS_In_Crit_Section(void)
270 {
271 return _state.in_critical;
272 }
273
274 // clang-format off
275 /**
276 * @brief Macro for wrapping a section of code to make it critical (interrupts disabled). Note: this macro
277 * does not support nesting.
278 * @details
279 * Ex:
280 * \code
281 * MXC_CRITICAL(
282 * printf("Hello critical section!\n");
283 * )
284 * \endcode
285 * This macro places a call to @ref MXC_SYS_Crit_Enter before the code, and a call to @ref MXC_SYS_Crit_Exit after.
286 * @param code The code section to wrap.
287 */
288 #define MXC_CRITICAL(code) {\
289 MXC_SYS_Crit_Enter();\
290 code;\
291 MXC_SYS_Crit_Exit();\
292 }
293 // clang-format on
294
295 /**
296 * @brief Reads the device USN and verifies the checksum.
297 * @param usn Pointer to store the USN. Array must be at least MXC_SYS_USN_LEN bytes long.
298 * @param checksum Optional pointer to store the AES checksum. If not NULL, checksum is verified with AES engine.
299 * @returns E_NO_ERROR if everything is successful.
300 */
301 int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum);
302
303 /**
304 * @brief Determines if the selected peripheral clock is enabled.
305 * @param clock Enumeration for desired clock.
306 * @returns 0 is the clock is disabled, non 0 if the clock is enabled.
307 */
308 int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock);
309
310 /**
311 * @brief Disables the selected peripheral clock.
312 * @param clock Enumeration for desired clock.
313 */
314 void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock);
315
316 /**
317 * @brief Enables the selected peripheral clock.
318 * @param clock Enumeration for desired clock.
319 */
320 void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock);
321
322 /**
323 * @brief Enables the 32kHz oscillator
324 * @param mxc_sys_cfg Not used, may be NULL.
325 */
326 void MXC_SYS_RTCClockEnable(void);
327
328 /**
329 * @brief Disables the 32kHz oscillator
330 * @returns E_NO_ERROR if everything is successful
331 */
332 int MXC_SYS_RTCClockDisable(void);
333
334 /**
335 * @brief Enable System Clock Source without switching to it
336 * @param clock The clock to enable
337 * @return E_NO_ERROR if everything is successful
338 */
339 int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock);
340
341 /**
342 * @brief Disable System Clock Source
343 * @param clock The clock to disable
344 * @return E_NO_ERROR if everything is successful
345 */
346 int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock);
347
348 /**
349 * @brief Get the current system clock divider.
350 * @returns The enumerator for the current system clock divider.
351 */
352 mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void);
353
354 /**
355 * @brief Set the system clock divider.
356 * @param div Enumeration for desired clock divider.
357 */
358 void MXC_SYS_SetClockDiv(mxc_sys_system_clock_div_t div);
359
360 /**
361 * @brief Select the system clock.
362 * @param clock Enumeration for desired clock. Note: If using the external clock input be sure to define EXTCLK_FREQ correctly.
363 * The default EXTCLK_FREQ value is defined in the system_max78000.h file and can be overridden at compile time.
364 * @returns E_NO_ERROR if everything is successful.
365 */
366 int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock);
367
368 /**
369 * @brief Wait for a clock to enable with timeout
370 * @param ready The clock to wait for
371 * @return E_NO_ERROR if ready, E_TIME_OUT if timeout
372 */
373 int MXC_SYS_Clock_Timeout(uint32_t ready);
374
375 /**
376 * @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register.
377 * @param Enumeration for what to reset. Can reset multiple items at once.
378 */
379 void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset);
380
381 /**
382 * @brief Setup and run RISCV core
383 */
384 void MXC_SYS_RISCVRun(void);
385
386 /**
387 * @brief Shutdown the RISCV core
388 */
389 void MXC_SYS_RISCVShutdown(void);
390
391 /**
392 * @brief Returns the clock rate (in Hz) of the Risc-V core.
393 */
394 uint32_t MXC_SYS_RiscVClockRate(void);
395
396 /**
397 * @brief This function PERMANENTLY locks the Debug Access Port.
398 *
399 * @warning After executing this function you will never be able
400 * to reprogram the target micro.
401 */
402 int MXC_SYS_LockDAP_Permanent(void);
403
404 #ifdef __cplusplus
405 }
406 #endif
407
408 #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_MXC_SYS_H_
409
