1 /** 2 * @file dma.h 3 * @brief Direct Memory Access (DMA) driver function prototypes and data types. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32690_DMA_H_ 27 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32690_DMA_H_ 28 29 /* **** Includes **** */ 30 #include <stdbool.h> 31 #include "mxc_device.h" 32 #include "dma_regs.h" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /** 39 * @defgroup dma Direct Memory Access (DMA) 40 * @ingroup periphlibs 41 * @{ 42 */ 43 44 /* **** Definitions **** */ 45 46 /** 47 * @brief Enumeration for the DMA Channel's priority level. 48 * 49 */ 50 typedef enum { 51 MXC_DMA_PRIO_HIGH = MXC_V_DMA_CTRL_PRI_HIGH, ///< High Priority 52 MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CTRL_PRI_MEDHIGH, ///< Medium High Priority 53 MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CTRL_PRI_MEDLOW, ///< Medium Low Priority 54 MXC_DMA_PRIO_LOW = MXC_V_DMA_CTRL_PRI_LOW, ///< Low Priority 55 } mxc_dma_priority_t; 56 57 /** @brief DMA request select */ 58 typedef enum { 59 MXC_DMA_REQUEST_MEMTOMEM = 60 MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection 61 MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX, ///< SPI0 Receive DMA Request Selection 62 MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX, ///< SPI1 Receive DMA Request Selection 63 MXC_DMA_REQUEST_SPI2RX = MXC_S_DMA_CTRL_REQUEST_SPI2RX, ///< SPI2 Receive DMA Request Selection 64 MXC_DMA_REQUEST_SPI3RX = MXC_S_DMA_CTRL_REQUEST_SPI3RX, ///< SPI3 Receive DMA Request Selection 65 MXC_DMA_REQUEST_SPI4RX = MXC_S_DMA_CTRL_REQUEST_SPI4RX, ///< SPI4 Receive DMA Request Selection 66 MXC_DMA_REQUEST_UART0RX = 67 MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection 68 MXC_DMA_REQUEST_UART1RX = 69 MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection 70 MXC_DMA_REQUEST_UART2RX = 71 MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection 72 MXC_DMA_REQUEST_UART3RX = 73 MXC_S_DMA_CTRL_REQUEST_UART3RX, ///< UART3 Receive DMA Request Selection 74 MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CTRL_REQUEST_I2C0RX, ///< I2C0 Receive DMA Request Selection 75 MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CTRL_REQUEST_I2C1RX, ///< I2C1 Receive DMA Request Selection 76 MXC_DMA_REQUEST_I2C2RX = MXC_S_DMA_CTRL_REQUEST_I2C2RX, ///< I2C2 Receive DMA Request Selection 77 MXC_DMA_REQUEST_ADC = MXC_S_DMA_CTRL_REQUEST_ADC, ///< ADC Receive DMA Request Selection 78 MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX, ///< I2S Receive DMA Request Selection 79 MXC_DMA_REQUEST_CAN0RX = MXC_S_DMA_CTRL_REQUEST_CAN0RX, ///< CAN0 Receive DMA Request Selection 80 MXC_DMA_REQUEST_CAN1RX = MXC_S_DMA_CTRL_REQUEST_CAN1RX, ///< CAN1 Receive DMA Request Selection 81 MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection 82 MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection 83 MXC_DMA_REQUEST_SPI2TX = MXC_S_DMA_CTRL_REQUEST_SPI2TX, ///< SPI2 Transmit DMA Request Selection 84 MXC_DMA_REQUEST_SPI3TX = MXC_S_DMA_CTRL_REQUEST_SPI3TX, ///< SPI3 Transmit DMA Request Selection 85 MXC_DMA_REQUEST_SPI4TX = MXC_S_DMA_CTRL_REQUEST_SPI4TX, ///< SPI4 Transmit DMA Request Selection 86 MXC_DMA_REQUEST_UART0TX = 87 MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection 88 MXC_DMA_REQUEST_UART1TX = 89 MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection 90 MXC_DMA_REQUEST_UART2TX = 91 MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART2 Transmit DMA Request Selection 92 MXC_DMA_REQUEST_UART3TX = 93 MXC_S_DMA_CTRL_REQUEST_UART3TX, ///< UART3 Receive DMA Request Selection 94 MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CTRL_REQUEST_I2C0TX, ///< I2C0 Transmit DMA Request Selection 95 MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CTRL_REQUEST_I2C1TX, ///< I2C1 Transmit DMA Request Selection 96 MXC_DMA_REQUEST_I2C2TX = MXC_S_DMA_CTRL_REQUEST_I2C2TX, ///< I2C2 Transmit DMA Request Selection 97 MXC_DMA_REQUEST_I2STX = MXC_S_DMA_CTRL_REQUEST_I2STX, ///< I2S Transmit DMA Request Selection 98 MXC_DMA_REQUEST_CAN0TX = MXC_S_DMA_CTRL_REQUEST_CAN0TX, ///< CAN0 Transmit DMA Request Selection 99 MXC_DMA_REQUEST_CAN1TX = MXC_S_DMA_CTRL_REQUEST_CAN1TX, ///< CAN1 Transmit DMA Request Selection 100 } mxc_dma_reqsel_t; 101 102 /** @brief Enumeration for the DMA prescaler */ 103 typedef enum { 104 MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CTRL_TO_CLKDIV_DIS, ///< Prescaler disabled 105 MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CTRL_TO_CLKDIV_DIV256, ///< Divide by 256 106 MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K, ///< Divide by 65,536 107 MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M, ///< Divide by 16,777,216 108 } mxc_dma_prescale_t; 109 110 /** @brief Enumeration for the DMA timeout value */ 111 typedef enum { 112 MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CTRL_TO_PER_TO4, ///< DMA timeout of 4 clocks 113 MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CTRL_TO_PER_TO8, ///< DMA timeout of 8 clocks 114 MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CTRL_TO_PER_TO16, ///< DMA timeout of 16 clocks 115 MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CTRL_TO_PER_TO32, ///< DMA timeout of 32 clocks 116 MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CTRL_TO_PER_TO64, ///< DMA timeout of 64 clocks 117 MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CTRL_TO_PER_TO128, ///< DMA timeout of 128 clocks 118 MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CTRL_TO_PER_TO256, ///< DMA timeout of 256 clocks 119 MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CTRL_TO_PER_TO512, ///< DMA timeout of 512 clocks 120 } mxc_dma_timeout_t; 121 122 /** @brief DMA transfer data width */ 123 typedef enum { 124 /* Using the '_V_' define instead of the '_S_' since these same values will be used to 125 specify the DSTWD also. The API functions will shift the value the correct amount 126 prior to writing the cfg register. */ 127 MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CTRL_SRCWD_BYTE, ///< DMA transfer in bytes 128 MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CTRL_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words 129 MXC_DMA_WIDTH_WORD = MXC_V_DMA_CTRL_SRCWD_WORD, ///< DMA transfer in 32-bit words 130 } mxc_dma_width_t; 131 132 /** 133 * @brief The basic configuration information to set up a DMA channel 134 * and prepare it for transfers. 135 * 136 */ 137 typedef struct { 138 int ch; ///< The channel to load the configuration data into 139 mxc_dma_reqsel_t reqsel; ///< The request select line to be used (mem2mem, peripheral) 140 mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width) 141 mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width) 142 int srcinc_en; ///< Whether to increment the source address during the transfer 143 int dstinc_en; ///< Whether to increment the source address during the transfer 144 } mxc_dma_config_t; 145 146 /** 147 * @brief The information needed to complete a DMA transfer 148 * 149 */ 150 typedef struct { 151 int ch; ///< The channel to use for the transfer 152 void *source; ///< Pointer to the source address, if applicable 153 void *dest; ///< Pointer to the destination address, if applicable 154 int len; ///< Number of bytes to transfer 155 } mxc_dma_srcdst_t; 156 157 /** 158 * @brief The advanced configuration options, these are optional but could 159 * be needed in cases where multiple DMA channels are running concurrently 160 * or DMA is being used with low bandwidth peripherals. 161 * 162 */ 163 typedef struct { 164 int ch; ///< The channel to use for the transfer 165 mxc_dma_priority_t prio; ///< The DMA priority for the channel 166 unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer 167 mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout 168 mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer 169 unsigned int burst_size; ///< Number of bytes moved in a single burst 170 } mxc_dma_adv_config_t; 171 172 /** 173 * @brief The callback called on completion of a DMA_MemCpy() transfer 174 * 175 * @param dest Pointer to the destination of the copy 176 */ 177 typedef void (*mxc_dma_complete_cb_t)(void *dest); 178 179 /** 180 * @brief The callback called on completion of a transfer, 181 * @note This callback is used with MXC_DMA_DoTransfer() 182 * to allow the user to chain an unlimited number of 183 * DMA Transfers. 184 * 185 * @param trans Struct of the completed transfer 186 * 187 * @return Returns the next transfer to be completed, or NULL 188 * if no more transfers will be done 189 */ 190 typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); 191 192 /* **** Function Prototypes **** */ 193 /*************************/ 194 /* Low Level Functions */ 195 /*************************/ 196 /** 197 * @brief Initialize DMA resources 198 * @details This initialization is required before using the DMA driver functions. 199 * @note On default this function enables DMA peripheral clock. 200 * if you wish to manage clock and gpio related things in upper level instead of here. 201 * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. 202 * By this flag this function will remove clock and gpio related codes from file. 203 * @return #E_NO_ERROR if successful 204 */ 205 int MXC_DMA_Init(void); 206 207 /** 208 * @brief De-Initialize DMA resources. 209 */ 210 void MXC_DMA_DeInit(void); 211 212 /** 213 * @brief Request DMA channel 214 * @details Returns a handle to the first free DMA channel, which can be used via API calls 215 * or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function. 216 * @return Non-negative channel handle (inclusive of zero). 217 * @return #E_NONE_AVAIL All channels in use. 218 * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. 219 * @return #E_BUSY DMA is currently busy (locked), try again later. 220 */ 221 int MXC_DMA_AcquireChannel(void); 222 223 /** 224 * @brief Release DMA channel 225 * @details Stops any DMA operation on the channel and returns it to the pool of free channels. 226 * 227 * @param ch channel handle to release 228 * 229 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 230 */ 231 int MXC_DMA_ReleaseChannel(int ch); 232 233 /** 234 * @brief Configure the DMA channel 235 * @details Configures the channel, which was previously requested by MXC_DMA_Getchannel() 236 * 237 * @param config Struct containing DMA configuration parameters 238 * @param srcdst Struct containing pointers and length of DMA operation 239 * 240 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 241 */ 242 int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); 243 244 /** 245 * @brief Configure the DMA channel with more advanced parameters 246 * 247 * @param advConfig Struct containing advanced DMA parameters 248 * 249 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 250 */ 251 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig); 252 253 /** 254 * @brief Set channel source, destination, and count for the transfer 255 * @param srcdst Struct containing the channel, source, destination, and count for the channel 256 * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, 257 * either src_addr or dst_addr will be ignored by the DMA engine. 258 * In these cases, the address is a don't-care. See the User's 259 * Guide for more information. 260 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 261 */ 262 int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst); 263 264 /** 265 * @brief Get channel source, destination, and count for transfer 266 * 267 * @param srcdst Pointer to struct with the correct channel number 268 * 269 * @return See \ref MXC_Error_Codes for a list of return values 270 */ 271 int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst); 272 273 /** 274 * @brief Set channel reload source, destination, and count for the transfer 275 * @param srcdstReload Struct containing the channel, source, destination, and count for the channel 276 * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, 277 * either src_addr or dst_addr will be ignored by the DMA engine. 278 * In these cases, the address is a don't-care. See the User's 279 * Guide for more information. 280 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 281 */ 282 int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdstReload); 283 284 /** 285 * @brief Get channel reload source, destination, and count for transfer 286 * 287 * @param srcdstReload Pointer to struct with the correct channel number 288 * 289 * @return See \ref MXC_Error_Codes for a list of return values 290 */ 291 int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload); 292 293 /** 294 * @brief Set channel interrupt callback 295 * @param ch channel handle 296 * @param callback Pointer to a function to call when the channel 297 * interrupt flag is set and interrupts are enabled or 298 * when DMA is shutdown by the driver. 299 * @details Configures the channel interrupt callback. The @p callback 300 * function is called for two conditions: 301 * -# When the channel's interrupt flag is set and DMA interrupts 302 * are enabled. 303 * -# If the driver calls the MXC_DMA_Shutdown() function. The 304 * callback function prototype is: 305 * @code 306 * void callback_fn(int ch, int reason); 307 * @endcode 308 * @p ch indicates the channel that generated the callback, @p 309 * reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN 310 * if the DMA is being shutdown. 311 * 312 * @return #E_BAD_PARAM if an unused or invalid channel handle, 313 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 314 */ 315 int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)); 316 317 /** 318 * @brief Set channel interrupt 319 * @note Each channel has two interrupts (complete, and count to zero). 320 * To enable complete, pass true for chdis. To enable count to zero, 321 * pass true for ctz. 322 * @param ch Channel Handle 323 * @param chdis Enable channel complete interrupt 324 * @param ctz Enable channel count to zero interrupt. 325 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 326 */ 327 int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz); 328 329 /** 330 * @brief Enable channel interrupt 331 * @note Each channel has two interrupts (complete, and count to zero) 332 which must also be enabled with MXC_DMA_SetChannelInterruptEn() 333 * @param ch channel handle 334 * @param flags The flags to enable 335 * @return #E_BAD_PARAM if an unused or invalid channel handle, 336 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 337 */ 338 int MXC_DMA_ChannelEnableInt(int ch, int flags); 339 340 /** 341 * @brief Disable channel interrupt 342 * @param ch channel handle 343 * @param flags The flags to disable 344 * @return #E_BAD_PARAM if an unused or invalid channel handle, 345 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 346 */ 347 int MXC_DMA_ChannelDisableInt(int ch, int flags); 348 349 /** 350 * @brief Read channel interrupt flags 351 * @param ch channel handle 352 * @return #E_BAD_PARAM if an unused or invalid channel handle, 353 * flags otherwise, \ref MXC_Error_Codes 354 */ 355 int MXC_DMA_ChannelGetFlags(int ch); 356 357 /** 358 * @brief Clear channel interrupt flags 359 * @param ch channel handle 360 * @param flags The flags to clear 361 * @return #E_BAD_PARAM if an unused or invalid channel handle, 362 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 363 */ 364 int MXC_DMA_ChannelClearFlags(int ch, int flags); 365 366 /** 367 * @brief Enable channel interrupt 368 * @note Each channel has two interrupts (complete, and count to zero) 369 which must also be enabled with MXC_DMA_SetChannelInterruptEn() 370 * @param ch channel handle 371 * @return #E_BAD_PARAM if an unused or invalid channel handle, 372 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 373 */ 374 int MXC_DMA_EnableInt(int ch); 375 376 /** 377 * @brief Disable channel interrupt 378 * @param ch channel handle 379 * @return #E_BAD_PARAM if an unused or invalid channel handle, 380 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 381 */ 382 int MXC_DMA_DisableInt(int ch); 383 384 /** 385 * @brief Start transfer 386 * @param ch channel handle 387 * @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. 388 * @return #E_BAD_PARAM if an unused or invalid channel handle, 389 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 390 */ 391 int MXC_DMA_Start(int ch); 392 393 /** 394 * @brief Stop DMA transfer, irrespective of status (complete or in-progress) 395 * @param ch channel handle 396 * @return #E_BAD_PARAM if an unused or invalid channel handle, 397 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 398 */ 399 int MXC_DMA_Stop(int ch); 400 401 /** 402 * @brief Get a pointer to the DMA channel registers 403 * @param ch channel handle 404 * @details If direct access to DMA channel registers is required, this 405 * function can be used on a channel handle returned by MXC_DMA_AcquireChannel(). 406 * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise 407 */ 408 mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch); 409 410 /** 411 * @brief Interrupt handler function 412 * @details Call this function as the ISR for each DMA channel under driver control. 413 * Interrupt flags for channel ch will be automatically cleared before return. 414 */ 415 void MXC_DMA_Handler(void); 416 417 /*************************/ 418 /* High Level Functions */ 419 /*************************/ 420 421 /** 422 * @brief Performs a memcpy, using DMA, optionally asynchronous 423 * @note The user must have the DMA interrupt enabled and call 424 * MXC_DMA_Handler() from the ISR. 425 * 426 * @param dest pointer to destination memory 427 * @param src pointer to source memory 428 * @param len number of bytes to copy 429 * @param callback function to call when transfer is complete 430 * 431 * @return see \ref MXC_Error_Codes 432 */ 433 int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback); 434 435 /** 436 * @brief Performs a memcpy, using DMA, optionally asynchronous 437 * @note The user must have the DMA interrupt enabled and call 438 * MXC_DMA_Handler() from the ISR. 439 * 440 * @param config The channel config struct 441 * @param firstSrcDst The source, destination, and count for the first transfer 442 * @param callback function is called when transfer is complete 443 * 444 * @return see \ref MXC_Error_Codes 445 */ 446 int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, 447 mxc_dma_trans_chain_t callback); 448 /** 449 * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver 450 */ 451 452 /**@} end of group dma */ 453 #ifdef __cplusplus 454 } 455 #endif 456 457 #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32690_DMA_H_ 458
