1 /** 2 * @file dma.h 3 * @brief Direct Memory Access (DMA) driver function prototypes and data types. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32665_DMA_H_ 27 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32665_DMA_H_ 28 29 /* **** Includes **** */ 30 #include <stdbool.h> 31 #include "mxc_device.h" 32 #include "dma_regs.h" 33 #include "mxc_errors.h" 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 /** 40 * @defgroup dma Direct Memory Access (DMA) 41 * @ingroup periphlibs 42 * @{ 43 */ 44 45 /* **** Definitions **** */ 46 47 /** 48 * Enumeration for the DMA Channel's priority level. 49 */ 50 typedef enum { 51 MXC_DMA_PRIO_HIGH = MXC_S_DMA_CFG_PRI_HIGH, /**< High Priority */ 52 MXC_DMA_PRIO_MEDHIGH = MXC_S_DMA_CFG_PRI_MEDHIGH, /**< Medium High Priority */ 53 MXC_DMA_PRIO_MEDLOW = MXC_S_DMA_CFG_PRI_MEDLOW, /**< Medium Low Priority */ 54 MXC_DMA_PRIO_LOW = MXC_S_DMA_CFG_PRI_LOW, /**< Low Priority */ 55 } mxc_dma_priority_t; 56 57 /** @brief DMA request select */ 58 typedef enum { 59 MXC_DMA_REQUEST_MEMTOMEM = 60 MXC_S_DMA_CFG_REQSEL_MEMTOMEM, /**< Memory to Memory DMA Request Selection */ 61 MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX, /**< SPI0 Receive DMA Request Selection */ 62 MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX, /**< SPI1 Receive DMA Request Selection */ 63 MXC_DMA_REQUEST_SPI2RX = MXC_S_DMA_CFG_REQSEL_SPI2RX, /**< SPI2 Receive DMA Request Selection */ 64 MXC_DMA_REQUEST_UART0RX = 65 MXC_S_DMA_CFG_REQSEL_UART0RX, /**< UART0 Receive DMA Request Selection */ 66 MXC_DMA_REQUEST_UART1RX = 67 MXC_S_DMA_CFG_REQSEL_UART1RX, /**< UART1 Receive DMA Request Selection */ 68 MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX, /**< I2C0 Receive DMA Request Selection */ 69 MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX, /**< I2C1 Receive DMA Request Selection */ 70 MXC_DMA_REQUEST_ADC = MXC_S_DMA_CFG_REQSEL_ADC, /**< ADC DMA Request Selection */ 71 MXC_DMA_REQUEST_I2C2RX = MXC_S_DMA_CFG_REQSEL_I2C2RX, 72 MXC_DMA_REQUEST_UART2RX = 73 MXC_S_DMA_CFG_REQSEL_UART2RX, /**< UART2 Receive DMA Request Selection */ 74 //MXC_DMA_REQSEL_SPI3RX = MXC_S_DMA_CFG_REQSEL_SPI3RX, /**< SPI3 Receive DMA Request Selection */ 75 //MXC_DMA_REQSEL_SPI_MSS0RX = MXC_S_DMA_CFG_REQSEL_SPI_MSS0RX, /**< I2S Receive DMA Request Selection */ 76 MXC_DMA_REQUEST_USBRXEP1 = 77 MXC_S_DMA_CFG_REQSEL_USBRXEP1, /**< USB Receive Endpoint 1 DMA Request Selection */ 78 MXC_DMA_REQUEST_USBRXEP2 = 79 MXC_S_DMA_CFG_REQSEL_USBRXEP2, /**< USB Receive Endpoint 2 DMA Request Selection */ 80 MXC_DMA_REQUEST_USBRXEP3 = 81 MXC_S_DMA_CFG_REQSEL_USBRXEP3, /**< USB Receive Endpoint 3 DMA Request Selection */ 82 MXC_DMA_REQUEST_USBRXEP4 = 83 MXC_S_DMA_CFG_REQSEL_USBRXEP4, /**< USB Receive Endpoint 4 DMA Request Selection */ 84 MXC_DMA_REQUEST_USBRXEP5 = 85 MXC_S_DMA_CFG_REQSEL_USBRXEP5, /**< USB Receive Endpoint 5 DMA Request Selection */ 86 MXC_DMA_REQUEST_USBRXEP6 = 87 MXC_S_DMA_CFG_REQSEL_USBRXEP6, /**< USB Receive Endpoint 6 DMA Request Selection */ 88 MXC_DMA_REQUEST_USBRXEP7 = 89 MXC_S_DMA_CFG_REQSEL_USBRXEP7, /**< USB Receive Endpoint 7 DMA Request Selection */ 90 MXC_DMA_REQUEST_USBRXEP8 = 91 MXC_S_DMA_CFG_REQSEL_USBRXEP8, /**< USB Receive Endpoint 8 DMA Request Selection */ 92 MXC_DMA_REQUEST_USBRXEP9 = 93 MXC_S_DMA_CFG_REQSEL_USBRXEP9, /**< USB Receive Endpoint 9 DMA Request Selection */ 94 MXC_DMA_REQUEST_USBRXEP10 = 95 MXC_S_DMA_CFG_REQSEL_USBRXEP10, /**< USB Receive Endpoint 10 DMA Request Selection */ 96 MXC_DMA_REQUEST_USBRXEP11 = 97 MXC_S_DMA_CFG_REQSEL_USBRXEP11, /**< USB Receive Endpoint 11 DMA Request Selection */ 98 MXC_DMA_REQUEST_SPI0TX = 99 MXC_S_DMA_CFG_REQSEL_SPI0TX, /**< SPI0 Transmit DMA Request Selection */ 100 MXC_DMA_REQUEST_SPI1TX = 101 MXC_S_DMA_CFG_REQSEL_SPI1TX, /**< SPI1 Transmit DMA Request Selection */ 102 MXC_DMA_REQUEST_SPI2TX = 103 MXC_S_DMA_CFG_REQSEL_SPI2TX, /**< SPI2 Transmit DMA Request Selection */ 104 MXC_DMA_REQUEST_UART0TX = 105 MXC_S_DMA_CFG_REQSEL_UART0TX, /**< UART0 Transmit DMA Request Selection */ 106 MXC_DMA_REQUEST_UART1TX = 107 MXC_S_DMA_CFG_REQSEL_UART1TX, /**< UART1 Transmit DMA Request Selection */ 108 MXC_DMA_REQUEST_I2C0TX = 109 MXC_S_DMA_CFG_REQSEL_I2C0TX, /**< I2C0 Transmit DMA Request Selection */ 110 MXC_DMA_REQUEST_I2C1TX = 111 MXC_S_DMA_CFG_REQSEL_I2C1TX, /**< I2C1 Transmit DMA Request Selection */ 112 MXC_DMA_REQUEST_I2C2TX = 113 MXC_S_DMA_CFG_REQSEL_I2C2TX, /**< I2C2 Transmit DMA Request Selection */ 114 MXC_DMA_REQUEST_UART2TX = 115 MXC_S_DMA_CFG_REQSEL_UART2TX, /**< UART 2 Transmit DMA Request Selection */ 116 //MXC_DMA_REQUEST_SPI3TX = MXC_S_DMA_CFG_REQSEL_SPI3TX, /**< SPI3 Transmit DMA Request Selection */ 117 //MXC_DMA_REQUEST_SPI_MSS0TX = MXC_S_DMA_CFG_REQSEL_SPI_MSS0TX, /**< I2S Transmit DMA Request Selection */ 118 MXC_DMA_REQUEST_USBTXEP1 = 119 MXC_S_DMA_CFG_REQSEL_USBTXEP1, /**< USB TX Endpoint 1 DMA Request Selection */ 120 MXC_DMA_REQUEST_USBTXEP2 = 121 MXC_S_DMA_CFG_REQSEL_USBTXEP2, /**< USB TX Endpoint 2 DMA Request Selection */ 122 MXC_DMA_REQUEST_USBTXEP3 = 123 MXC_S_DMA_CFG_REQSEL_USBTXEP3, /**< USB TX Endpoint 3 DMA Request Selection */ 124 MXC_DMA_REQUEST_USBTXEP4 = 125 MXC_S_DMA_CFG_REQSEL_USBTXEP4, /**< USB TX Endpoint 4 DMA Request Selection */ 126 MXC_DMA_REQUEST_USBTXEP5 = 127 MXC_S_DMA_CFG_REQSEL_USBTXEP5, /**< USB TX Endpoint 5 DMA Request Selection */ 128 MXC_DMA_REQUEST_USBTXEP6 = 129 MXC_S_DMA_CFG_REQSEL_USBTXEP6, /**< USB TX Endpoint 6 DMA Request Selection */ 130 MXC_DMA_REQUEST_USBTXEP7 = 131 MXC_S_DMA_CFG_REQSEL_USBTXEP7, /**< USB TX Endpoint 7 DMA Request Selection */ 132 MXC_DMA_REQUEST_USBTXEP8 = 133 MXC_S_DMA_CFG_REQSEL_USBTXEP8, /**< USB TX Endpoint 8 DMA Request Selection */ 134 MXC_DMA_REQUEST_USBTXEP9 = 135 MXC_S_DMA_CFG_REQSEL_USBTXEP9, /**< USB TX Endpoint 9 DMA Request Selection */ 136 MXC_DMA_REQUEST_USBTXEP10 = 137 MXC_S_DMA_CFG_REQSEL_USBTXEP10, /**< USB TX Endpoint 10 DMA Request Selection */ 138 MXC_DMA_REQUEST_USBTXEP11 = 139 MXC_S_DMA_CFG_REQSEL_USBTXEP11, /**< USB TX Endpoint 11 DMA Request Selection */ 140 } mxc_dma_reqsel_t; 141 142 /** @brief Enumeration for the DMA prescaler */ 143 typedef enum { 144 MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS, /**< Prescaler disabled */ 145 MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256, /**< Divide by 256 */ 146 MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K, /**< Divide by 65,536 */ 147 MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M, /**< Divide by 16,777,216 */ 148 } mxc_dma_prescale_t; 149 150 /** @brief Enumeration for the DMA timeout value */ 151 typedef enum { 152 MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4, /**< DMA timeout of 4 clocks */ 153 MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8, /**< DMA timeout of 8 clocks */ 154 MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16, /**< DMA timeout of 16 clocks */ 155 MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32, /**< DMA timeout of 32 clocks */ 156 MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64, /**< DMA timeout of 64 clocks */ 157 MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128, /**< DMA timeout of 128 clocks */ 158 MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256, /**< DMA timeout of 256 clocks */ 159 MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512 /**< DMA timeout of 512 clocks */ 160 } mxc_dma_timeout_t; 161 162 /** @brief DMA transfer data width */ 163 typedef enum { 164 /* Using the '_V_' define instead of the '_S_' since these same values will be used to 165 specify the DSTWD also. The API functions will shift the value the correct amount 166 prior to writing the cfg register. */ 167 MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE, /**< DMA transfer in bytes */ 168 MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD, /**< DMA transfer in 16-bit half-words */ 169 MXC_DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD /**< DMA transfer in 32-bit words */ 170 } mxc_dma_width_t; 171 172 /** 173 * @brief The basic configuration information to set up a DMA channel 174 * and prepare it for transfers. 175 * 176 */ 177 typedef struct { 178 int ch; ///< The channel to load the configuration data into 179 mxc_dma_reqsel_t reqsel; ///< The request select line to be used (mem2mem, peripheral) 180 mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width) 181 mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width) 182 int srcinc_en; ///< Whether to increment the source address during the transfer 183 int dstinc_en; ///< Whether to increment the source address during the transfer 184 } mxc_dma_config_t; 185 186 /** 187 * @brief The information needed to complete a DMA transfer 188 * 189 */ 190 typedef struct { 191 int ch; ///< The channel to use for the transfer 192 void *source; ///< Pointer to the source address, if applicable 193 void *dest; ///< Pointer to the destination address, if applicable 194 int len; ///< Number of bytes to transfer 195 } mxc_dma_srcdst_t; 196 197 /** 198 * @brief The advanced configuration options, these are optional but could 199 * be needed in cases where multiple DMA channels are running concurrently 200 * or DMA is being used with low bandwidth peripherals. 201 * 202 */ 203 typedef struct { 204 int ch; ///< The channel to use for the transfer 205 mxc_dma_priority_t prio; ///< The DMA priority for the channel 206 unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer 207 mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout 208 mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer 209 unsigned int burst_size; ///< Number of bytes moved in a single burst 210 } mxc_dma_adv_config_t; 211 212 /** 213 * @brief The callback called on completion of a DMA_MemCpy() transfer 214 * 215 * @param dest Pointer to the destination of the copy 216 */ 217 typedef void (*mxc_dma_complete_cb_t)(void *dest); 218 219 /** 220 * @brief The callback called on completion of a transfer, 221 * @note This callback is used with MXC_DMA_DoTransfer() 222 * to allow the user to chain an unlimited number of 223 * DMA Transfers. 224 * 225 * @param trans Struct of the completed transfer 226 * 227 * @return Returns the next transfer to be completed, or NULL 228 * if no more transfers will be done 229 */ 230 typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); 231 232 /* **** Function Prototypes **** */ 233 /*************************/ 234 /* Low Level Functions */ 235 /*************************/ 236 /** 237 * @brief Initialize DMA resources 238 * @param dma Pointer to DMA registers. 239 * @details This initialization is required before using the DMA driver functions. 240 * @note On default this function enables DMA peripheral clock. 241 * if you wish to manage clock and gpio related things in upper level instead of here. 242 * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. 243 * By this flag this function will remove clock and gpio related codes from file. 244 * @return #E_NO_ERROR if successful 245 */ 246 int MXC_DMA_Init(mxc_dma_regs_t *dma); 247 248 /** 249 * @brief De-Initialize DMA resources. 250 * 251 * @param dma Pointer to DMA registers. 252 */ 253 void MXC_DMA_DeInit(mxc_dma_regs_t *dma); 254 255 /** 256 * @brief Request DMA channel 257 * @param dma Pointer to DMA registers. 258 * @details Returns a handle to the first free DMA channel, which can be used via API calls 259 * or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function. 260 * @return Non-negative channel handle (inclusive of zero). 261 * @return #E_NONE_AVAIL All channels in use. 262 * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. 263 * @return #E_BUSY DMA is currently busy (locked), try again later. 264 */ 265 int MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma); 266 267 /** 268 * @brief Release DMA channel 269 * @details Stops any DMA operation on the channel and returns it to the pool of free channels. 270 * 271 * @param ch channel handle to release 272 * 273 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 274 */ 275 int MXC_DMA_ReleaseChannel(int ch); 276 277 /** 278 * @brief Configure the DMA channel 279 * @details Configures the channel, which was previously requested by MXC_DMA_Getchannel() 280 * 281 * @param config Struct containing DMA configuration parameters 282 * @param srcdst Struct containing pointers and length of DMA operation 283 * 284 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 285 */ 286 int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); 287 288 /** 289 * @brief Configure the DMA channel with more advanced parameters 290 * 291 * @param advConfig Struct containing advanced DMA parameters 292 * 293 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 294 */ 295 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig); 296 297 /** 298 * @brief Set channel source, destination, and count for the transfer 299 * @param srcdst Struct containing the channel, source, destination, and count for the channel 300 * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, 301 * either src_addr or dst_addr will be ignored by the DMA engine. 302 * In these cases, the address is a don't-care. See the User's 303 * Guide for more information. 304 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 305 */ 306 int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst); 307 308 /** 309 * @brief Get channel source, destination, and count for transfer 310 * 311 * @param srcdst Pointer to struct with the correct channel number 312 * 313 * @return See \ref MXC_Error_Codes for a list of return values 314 */ 315 316 int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst); 317 318 /** 319 * @brief Set channel reload source, destination, and count for the transfer 320 * @param srcdstReload Struct containing the channel, source, destination, and count for the channel 321 * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, 322 * either src_addr or dst_addr will be ignored by the DMA engine. 323 * In these cases, the address is a don't-care. See the User's 324 * Guide for more information. 325 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 326 */ 327 int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdstReload); 328 329 /** 330 * @brief Get channel reload source, destination, and count for transfer 331 * 332 * @param srcdstReload Pointer to struct with the correct channel number 333 * 334 * @return See \ref MXC_Error_Codes for a list of return values 335 */ 336 337 int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload); 338 339 /** 340 * @brief Set channel interrupt callback 341 * @param ch channel handle 342 * @param callback Pointer to a function to call when the channel 343 * interrupt flag is set and interrupts are enabled or 344 * when DMA is shutdown by the driver. 345 * @details Configures the channel interrupt callback. The @p callback 346 * function is called for two conditions: 347 * -# When the channel's interrupt flag is set and DMA interrupts 348 * are enabled. 349 * -# If the driver calls the MXC_DMA_Shutdown() function. The 350 * callback function prototype is: 351 * @code 352 * void callback_fn(int ch, int reason); 353 * @endcode 354 * @p ch indicates the channel that generated the callback, @p 355 * reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN 356 * if the DMA is being shutdown. 357 * 358 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR 359 * otherwise 360 */ 361 int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)); 362 363 /** 364 * @brief Set channel interrupt 365 * @note Each channel has two interrupts (complete, and count to zero). 366 * To enable complete, pass true for chdis. To enable count to zero, 367 * pass true for ctz. 368 * @param ch Channel Handle 369 * @param chdis Enable channel complete interrupt 370 * @param ctz Enable channel count to zero interrupt. 371 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 372 */ 373 int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz); 374 375 /** 376 * @brief Enable channel interrupt 377 * @note Each channel has two interrupts (complete, and count to zero) 378 which must also be enabled with MXC_DMA_SetChannelInterruptEn() 379 * @param ch channel handle 380 * @param flags The flags to enable 381 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 382 */ 383 int MXC_DMA_ChannelEnableInt(int ch, int flags); 384 385 /** 386 * @brief Disable channel interrupt 387 * @param ch channel handle 388 * @param flags The flags to disable 389 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 390 */ 391 int MXC_DMA_ChannelDisableInt(int ch, int flags); 392 393 /** 394 * @brief Read channel interrupt flags 395 * @param ch channel handle 396 * @return #E_BAD_PARAM if an unused or invalid channel handle, flags otherwise 397 */ 398 int MXC_DMA_ChannelGetFlags(int ch); 399 400 /** 401 * @brief Clear channel interrupt flags 402 * @param ch channel handle 403 * @param flags The flags to clear 404 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 405 */ 406 int MXC_DMA_ChannelClearFlags(int ch, int flags); 407 408 /** 409 * @brief Enable channel interrupt 410 * @note Each channel has two interrupts (complete, and count to zero) 411 which must also be enabled with MXC_DMA_SetChannelInterruptEn() 412 * @param ch channel handle 413 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 414 */ 415 int MXC_DMA_EnableInt(int ch); 416 417 /** 418 * @brief Disable channel interrupt 419 * @param ch channel handle 420 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 421 */ 422 int MXC_DMA_DisableInt(int ch); 423 424 /** 425 * @brief Start transfer 426 * @param ch channel handle 427 * @note Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. 428 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 429 */ 430 int MXC_DMA_Start(int ch); 431 432 /** 433 * @brief Stop DMA transfer, irrespective of status (complete or in-progress) 434 * @param ch channel handle 435 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 436 */ 437 int MXC_DMA_Stop(int ch); 438 439 /** 440 * @brief Get a pointer to the DMA channel registers 441 * @param ch channel handle 442 * @note If direct access to DMA channel registers is required, this 443 * function can be used on a channel handle returned by MXC_DMA_AcquireChannel(). 444 * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise 445 */ 446 mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch); 447 448 /** 449 * @brief Interrupt handler function 450 * @param dma Pointer to DMA registers. 451 * @details Call this function as the ISR for each DMA channel under driver control. 452 * Interrupt flags for channel ch will be automatically cleared before return. 453 */ 454 void MXC_DMA_Handler(mxc_dma_regs_t *dma); 455 456 /*************************/ 457 /* High Level Functions */ 458 /*************************/ 459 460 /** 461 * @brief Performs a memcpy, using DMA, optionally asynchronous 462 * @note The user must have the DMA interrupt enabled and call 463 * MXC_DMA_Handler() from the ISR. 464 * 465 * @param dma Pointer to DMA registers. 466 * @param dest pointer to destination memory 467 * @param src pointer to source memory 468 * @param len number of bytes to copy 469 * @param callback function to call when transfer is complete 470 * 471 * @return see \ref MXC_Error_Codes 472 */ 473 int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, 474 mxc_dma_complete_cb_t callback); 475 476 /** 477 * @brief Performs a memcpy, using DMA, optionally asynchronous 478 * @note The user must have the DMA interrupt enabled and call 479 * MXC_DMA_Handler() from the ISR. 480 * 481 * @param dma Pointer to DMA registers. 482 * @param config The channel config struct 483 * @param firstSrcDst The source, destination, and count for the first transfer 484 * @param callback function is called when transfer is complete 485 * 486 * @return see \ref MXC_Error_Codes 487 */ 488 int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, 489 mxc_dma_trans_chain_t callback); 490 /** 491 * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver 492 */ 493 494 /**@} end of group dma */ 495 #ifdef __cplusplus 496 } 497 #endif 498 499 #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32665_DMA_H_ 500
