1 /** 2 * @file spi.h 3 * @brief Serial Peripheral Interface (SPI) communications driver. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPI_H_ 27 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPI_H_ 28 29 /***** includes *******/ 30 #include "spi_regs.h" 31 #include "mxc_sys.h" 32 #include "mxc_assert.h" 33 #include "gpio.h" 34 #include "mxc_pins.h" 35 #include "mxc_lock.h" 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 /***** Definitions *****/ 42 43 /** 44 * @defgroup spi SPI 45 * @ingroup periphlibs 46 * @{ 47 */ 48 49 /** 50 * @brief The list of SPI Widths supported 51 * 52 * The SPI Width can be set on a per-transaction basis. 53 * An example use case of SPI_WIDTH_STANDARD_HALFDUPLEX is 54 * given. 55 * 56 * Using a MAX31865 RTD-to-SPI IC, read back the temperature 57 * The IC requires a SPI Read to be executed as 58 * 1. Assert SS 59 * 2. Write an 8bit register address 60 * 3. Read back the 8 bit register 61 * 4. Deassert SS 62 * This can be accomplished with the STANDARD_HALFDUPLEX width 63 * 1. set txData to the address, txLen=1 64 * 2. set rxData to a buffer of 1 byte, rxLen=1 65 * 3. The driver will transmit the txData, and after completion of 66 * txData begin to recieve data, padding MOSI with DefaultTXData 67 * 68 */ 69 typedef enum { 70 SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex 71 SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex 72 SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex 73 SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex 74 } mxc_spi_width_t; 75 76 /** 77 * @brief The list of SPI modes 78 * 79 * SPI supports four combinations of clock and phase polarity 80 * 81 * Clock polarity is controlled using the bit SPIn_CTRL2.cpol 82 * and determines if the clock is active high or active low 83 * 84 * Clock phase determines when the data must be stable for sampling 85 * 86 */ 87 typedef enum { 88 SPI_MODE_0, ///< clock phase = 0, clock polarity = 0 89 SPI_MODE_1, ///< clock phase = 0, clock polarity = 1 90 SPI_MODE_2, ///< clock phase = 1, clock polarity = 0 91 SPI_MODE_3, ///< clock phase = 1, clock polarity = 1 92 } mxc_spi_mode_t; 93 94 typedef struct _mxc_spi_req_t mxc_spi_req_t; 95 96 /** 97 * @brief The callback routine used to indicate the transaction has terminated. 98 * 99 * @param req The details of the transaction. 100 * @param result See \ref MXC_Error_Codes for the list of error codes. 101 */ 102 typedef void (*spi_complete_cb_t)(void *req, int result); 103 104 /** 105 * @brief The information required to perform a complete SPI transaction 106 * 107 * This structure is used by blocking, async, and DMA based transactions. 108 * @param "completeCB" only needs to be initialized for interrupt driven (Async) and DMA transactions. 109 */ 110 struct _mxc_spi_req_t { 111 mxc_spi_regs_t *spi; ///<Point to SPI registers 112 int ssIdx; ///< Slave select line to use (Master only, ignored in slave mode) 113 int ssDeassert; ///< 1 - Deassert SS at end of transaction, 0 - leave SS asserted 114 uint8_t *txData; ///< Buffer containing transmit data. For character sizes 115 ///< < 8 bits, pad the MSB of each byte with zeros. For 116 ///< character sizes > 8 bits, use two bytes per character 117 ///< and pad the MSB of the upper byte with zeros 118 uint8_t *rxData; ///< Buffer to store received data For character sizes 119 ///< < 8 bits, pad the MSB of each byte with zeros. For 120 ///< character sizes > 8 bits, use two bytes per character 121 ///< and pad the MSB of the upper byte with zeros 122 uint32_t txLen; ///< Number of bytes to be sent from txData 123 uint32_t rxLen; ///< Number of bytes to be stored in rxData 124 uint32_t txCnt; ///< Number of bytes actually transmitted from txData 125 uint32_t rxCnt; ///< Number of bytes stored in rxData 126 127 spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete 128 }; 129 130 /* ************************************************************************* */ 131 /* Control/Configuration functions */ 132 /* ************************************************************************* */ 133 134 /** 135 * @brief Initialize and enable SPI peripheral. 136 * 137 * This function initializes everything necessary to call a SPI transaction function. 138 * Some parameters are set to defaults as follows: 139 * SPI Mode - 0 140 * SPI Width - SPI_WIDTH_STANDARD (even if quadModeUsed is set) 141 * 142 * These parameters can be modified after initialization using low level functions 143 * 144 * @note On default this function enables I2C peripheral clock and i2c gpio pins. 145 * if you wish to manage clock and gpio related things in upper level instead of here. 146 * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. 147 * By this flag this function will remove clock and gpio related codes from file. 148 * 149 * @param spi Pointer to SPI registers (selects the SPI block used.) 150 * @param masterMode Whether to put the device in master or slave mode. Use 151 * non-zero for master mode, and zero for slave mode. 152 * @param quadModeUsed Whether to obtain control of the SDIO2/3 pins. Use 153 * non-zero if the pins are needed (if Quad Mode will 154 * be used), and zero if they are not needed (quad mode 155 * will never be used). 156 * @param numSlaves The number of slaves used, if in master mode. This 157 * is used to obtain control of the necessary SS pins. 158 * In slave mode this is ignored and SS1 is used. 159 * @param ssPolarity This field sets the SS active polarity for each 160 * slave, each bit position corresponds to each SS line. 161 * @param hz The requested clock frequency. The actual clock frequency 162 * will be returned by the function if successful. Used in 163 * master mode only. 164 * 165 * @return If successful, the actual clock frequency is returned. Otherwise, see 166 * \ref MXC_Error_Codes for a list of return codes. 167 */ 168 int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, 169 unsigned ssPolarity, unsigned int hz); 170 171 /** 172 * @brief Disable and shutdown SPI peripheral. 173 * 174 * @param spi Pointer to SPI registers (selects the SPI block used.) 175 * 176 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 177 */ 178 int MXC_SPI_Shutdown(mxc_spi_regs_t *spi); 179 180 /** 181 * @brief Checks if the given SPI bus can be placed in sleep mode. 182 * 183 * This functions checks to see if there are any on-going SPI transactions in 184 * progress. If there are transactions in progress, the application should 185 * wait until the SPI bus is free before entering a low-power state. 186 * 187 * @param spi Pointer to SPI registers (selects the SPI block used.) 188 * 189 * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref 190 * MXC_Error_Codes for the list of error return codes. 191 */ 192 int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi); 193 194 /** 195 * @brief Returns the frequency of the clock used as the bit rate generator for a given SPI instance. 196 * 197 * @param spi Pointer to SPI registers (selects the SPI block used.) 198 * 199 * @return Frequency of the clock used as the bit rate generator 200 */ 201 int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi); 202 203 /** 204 * @brief Set the frequency of the SPI interface. 205 * 206 * This function is applicable in Master mode only 207 * 208 * @param spi Pointer to SPI registers (selects the SPI block used.) 209 * @param hz The desired frequency in Hertz. 210 * 211 * @return Negative if error, otherwise actual speed set. See \ref 212 * MXC_Error_Codes for the list of error return codes. 213 */ 214 int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz); 215 216 /** 217 * @brief Get the frequency of the SPI interface. 218 * 219 * This function is applicable in Master mode only 220 * 221 * @param spi Pointer to SPI registers (selects the SPI block used.) 222 * 223 * @return The SPI bus frequency in Hertz 224 */ 225 unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi); 226 227 /** 228 * @brief Sets the number of bits per character 229 * 230 * @param spi Pointer to SPI registers (selects the SPI block used.) 231 * @param dataSize The number of bits per character 232 * 233 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 234 */ 235 int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize); 236 237 /** 238 * @brief Gets the number of bits per character 239 * 240 * @param spi Pointer to SPI registers (selects the SPI block used.) 241 * 242 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 243 */ 244 int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi); 245 246 /* ************************************************************************* */ 247 /* Low-level functions */ 248 /* ************************************************************************* */ 249 250 /** 251 * @brief Sets the slave select (SS) line used for transmissions 252 * 253 * This function is applicable in Master mode only 254 * 255 * @param spi Pointer to SPI registers (selects the SPI block used.) 256 * @param ssIdx Slave select index 257 * 258 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 259 */ 260 int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx); 261 262 /** 263 * @brief Gets the slave select (SS) line used for transmissions 264 * 265 * This function is applicable in Master mode only 266 * 267 * @param spi Pointer to SPI registers (selects the SPI block used.) 268 * 269 * @return slave slect 270 */ 271 int MXC_SPI_GetSlave(mxc_spi_regs_t *spi); 272 273 /** 274 * @brief Sets the SPI width used for transmissions 275 * 276 * @param spi Pointer to SPI registers (selects the SPI block used.) 277 * @param spiWidth SPI Width (3-Wire, Standard, Dual SPI, Quad SPI) 278 * 279 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 280 */ 281 int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth); 282 283 /** 284 * @brief Gets the SPI width used for transmissions 285 * 286 * @param spi Pointer to SPI registers (selects the SPI block used.) 287 * 288 * @return Spi Width \ref mxc_spi_width_t 289 */ 290 mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi); 291 292 /** 293 * @brief Sets the spi mode using clock polarity and clock phase 294 * 295 * @param spi Pointer to SPI registers (selects the SPI block used.) 296 * @param spiMode \ref mxc_spi_mode_t 297 * 298 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 299 */ 300 int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode); 301 302 /** 303 * @brief Gets the spi mode 304 * 305 * @param spi Pointer to SPI registers (selects the SPI block used.) 306 * 307 * @return mxc_spi_mode_t \ref mxc_spi_mode_t 308 */ 309 mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi); 310 311 /** 312 * @brief Starts a SPI Transmission 313 * 314 * This function is applicable in Master mode only 315 * 316 * The user must ensure that there are no ongoing transmissions before 317 * calling this function 318 * 319 * @param spi Pointer to SPI registers (selects the SPI block used.) 320 * 321 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 322 */ 323 int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi); 324 325 /** 326 * @brief Checks the SPI Peripheral for an ongoing transmission 327 * 328 * This function is applicable in Master mode only 329 * 330 * @param spi Pointer to SPI registers (selects the SPI block used.) 331 * 332 * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. 333 */ 334 int MXC_SPI_GetActive(mxc_spi_regs_t *spi); 335 336 /** 337 * @brief Aborts an ongoing SPI Transmission 338 * 339 * This function is applicable in Master mode only 340 * 341 * @param spi Pointer to SPI registers (selects the SPI block used.) 342 * 343 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 344 */ 345 int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi); 346 347 /** 348 * @brief Unloads bytes from the receive FIFO. 349 * 350 * @param spi Pointer to SPI registers (selects the SPI block used.) 351 * @param bytes The buffer to read the data into. 352 * @param len The number of bytes to read. 353 * 354 * @return The number of bytes actually read. 355 */ 356 unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); 357 358 /** 359 * @brief Get the number of bytes currently available in the receive FIFO. 360 * 361 * @param spi Pointer to SPI registers (selects the SPI block used.) 362 * 363 * @return The number of bytes available. 364 */ 365 unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi); 366 367 /** 368 * @brief Loads bytes into the transmit FIFO. 369 * 370 * @param spi Pointer to SPI registers (selects the SPI block used.) 371 * @param bytes The buffer containing the bytes to write 372 * @param len The number of bytes to write. 373 * 374 * @return The number of bytes actually written. 375 */ 376 unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); 377 378 /** 379 * @brief Get the amount of free space available in the transmit FIFO. 380 * 381 * @param spi Pointer to SPI registers (selects the SPI block used.) 382 * 383 * @return The number of bytes available. 384 */ 385 unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi); 386 387 /** 388 * @brief Removes and discards all bytes currently in the receive FIFO. 389 * 390 * @param spi Pointer to SPI registers (selects the SPI block used.) 391 */ 392 void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi); 393 394 /** 395 * @brief Removes and discards all bytes currently in the transmit FIFO. 396 * 397 * @param spi Pointer to SPI registers (selects the SPI block used.) 398 */ 399 void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); 400 401 /** 402 * @brief Set the receive threshold level. 403 * 404 * RX FIFO Receive threshold. Smaller values will cause 405 * interrupts to occur more often, but reduce the possibility 406 * of losing data because of a FIFO overflow. Larger values 407 * will reduce the time required by the ISR, but increase the 408 * possibility of data loss. Passing an invalid value will 409 * cause the driver to use the value already set in the 410 * appropriate register. 411 * 412 * @param spi Pointer to SPI registers (selects the SPI block used.) 413 * @param numBytes The threshold level to set. This value must be 414 * between 0 and 8 inclusive. 415 * 416 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 417 */ 418 int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); 419 420 /** 421 * @brief Get the current receive threshold level. 422 * 423 * @param spi Pointer to SPI registers (selects the SPI block used.) 424 * 425 * @return The receive threshold value (in bytes). 426 */ 427 unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); 428 429 /** 430 * @brief Set the transmit threshold level. 431 * 432 * TX FIFO threshold. Smaller values will cause interrupts 433 * to occur more often, but reduce the possibility of terminating 434 * a transaction early in master mode, or transmitting invalid data 435 * in slave mode. Larger values will reduce the time required by 436 * the ISR, but increase the possibility errors occurring. Passing 437 * an invalid value will cause the driver to use the value already 438 * set in the appropriate register. 439 * 440 * @param spi Pointer to SPI registers (selects the SPI block used.) 441 * @param numBytes The threshold level to set. This value must be 442 * between 0 and 8 inclusive. 443 * 444 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 445 */ 446 int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); 447 448 /** 449 * @brief Get the current transmit threshold level. 450 * 451 * @param spi Pointer to SPI registers (selects the SPI block used.) 452 * 453 * @return The transmit threshold value (in bytes). 454 */ 455 unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); 456 457 /** 458 * @brief Gets the interrupt flags that are currently set 459 * 460 * These functions should not be used while using non-blocking Transaction Level 461 * functions (Async or DMA) 462 * 463 * @param spi Pointer to SPI registers (selects the SPI block used.) 464 * 465 * @return The interrupt flags 466 */ 467 unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi); 468 469 /** 470 * @brief Clears the interrupt flags that are currently set 471 * 472 * These functions should not be used while using non-blocking Transaction Level 473 * functions (Async or DMA) 474 * 475 * @param spi Pointer to SPI registers (selects the SPI block used.) 476 */ 477 void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi); 478 479 /** 480 * @brief Enables specific interrupts 481 * 482 * These functions should not be used while using non-blocking Transaction Level 483 * functions (Async or DMA) 484 * 485 * @param spi Pointer to SPI registers (selects the SPI block used.) 486 * @param mask The interrupts to be enabled 487 */ 488 void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int mask); 489 490 /** 491 * @brief Disables specific interrupts 492 * 493 * These functions should not be used while using non-blocking Transaction Level 494 * functions (Async or DMA) 495 * 496 * @param spi Pointer to SPI registers (selects the SPI block used.) 497 * @param mask The interrupts to be disabled 498 */ 499 void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int mask); 500 501 /* ************************************************************************* */ 502 /* Transaction level functions */ 503 /* ************************************************************************* */ 504 505 /** 506 * @brief Performs a blocking SPI transaction. 507 * 508 * Performs a blocking SPI transaction. 509 * These actions will be performed in Master Mode: 510 * 1. Assert the specified SS 511 * 2. In Full Duplex Modes, send TX data while receiving RX Data 512 * if rxLen > txLen, pad txData with DefaultTXData 513 * if txLen > rxLen, discard rxData where rxCnt > rxLen 514 * 3. In Half Duplex Modes, send TX Data, then receive RX Data 515 * 4. Deassert the specified SS 516 * 517 * These actions will be performed in Slave Mode: 518 * 1. Fill FIFO with txData 519 * 2. Wait for SS Assert 520 * 3. If needed, pad txData with DefaultTXData 521 * 4. Unload RX FIFO as needed 522 * 5. On SS Deassert, return 523 * 524 * @param req Pointer to details of the transaction 525 * 526 * @return See \ref MXC_Error_Codes for the list of error return codes. 527 */ 528 int MXC_SPI_MasterTransaction(mxc_spi_req_t *req); 529 530 /** 531 * @brief Setup an interrupt-driven SPI transaction 532 * 533 * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary 534 * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) 535 * 536 * @param req Pointer to details of the transaction 537 * 538 * @return See \ref MXC_Error_Codes for the list of error return codes. 539 */ 540 int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req); 541 542 /** 543 * @brief Setup a DMA driven SPI transaction 544 * 545 * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary 546 * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) 547 * 548 * The lowest-indexed unused DMA channel will be acquired (using the DMA API) and 549 * set up to load/unload the FIFOs with as few interrupt-based events as 550 * possible. The channel will be reset and returned to the system at the end of 551 * the transaction. 552 * 553 * @param req Pointer to details of the transaction 554 * 555 * @return See \ref MXC_Error_Codes for the list of error return codes. 556 */ 557 int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req); 558 559 /** 560 * @brief Performs a blocking SPI transaction. 561 * 562 * Performs a blocking SPI transaction. 563 * These actions will be performed in Slave Mode: 564 * 1. Fill FIFO with txData 565 * 2. Wait for SS Assert 566 * 3. If needed, pad txData with DefaultTXData 567 * 4. Unload RX FIFO as needed 568 * 5. On SS Deassert, return 569 * 570 * @param req Pointer to details of the transaction 571 * 572 * @return See \ref MXC_Error_Codes for the list of error return codes. 573 */ 574 int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req); 575 576 /** 577 * @brief Setup an interrupt-driven SPI transaction 578 * 579 * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary 580 * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) 581 * 582 * @param req Pointer to details of the transactionz 583 * 584 * @return See \ref MXC_Error_Codes for the list of error return codes. 585 */ 586 int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req); 587 588 /** 589 * @brief Setup a DMA driven SPI transaction 590 * 591 * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary 592 * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) 593 * 594 * The lowest-indexed unused DMA channel will be acquired (using the DMA API) and 595 * set up to load/unload the FIFOs with as few interrupt-based events as 596 * possible. The channel will be reset and returned to the system at the end of 597 * the transaction. 598 * 599 * @param req Pointer to details of the transaction 600 * 601 * @return See \ref MXC_Error_Codes for the list of error return codes. 602 */ 603 int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req); 604 605 /** 606 * @brief Sets the TX data to transmit as a 'dummy' byte 607 * 608 * In single wire master mode, this data is transmitted on MOSI when performing 609 * an RX (MISO) only transaction. This defaults to 0. 610 * 611 * @param spi Pointer to SPI registers (selects the SPI block used.) 612 * @param defaultTXData Data to shift out in RX-only transactions 613 * 614 * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 615 */ 616 int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData); 617 618 /** 619 * @brief Abort any asynchronous requests in progress. 620 * 621 * Abort any asynchronous requests in progress. Any callbacks associated with 622 * the active transaction will be executed to indicate when the transaction 623 * has been terminated. 624 * 625 * @param spi Pointer to SPI registers (selects the SPI block used.) 626 */ 627 void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi); 628 629 /** 630 * @brief The processing function for asynchronous transactions. 631 * 632 * When using the asynchronous functions, the application must call this 633 * function periodically. This can be done from within the SPI interrupt 634 * handler or periodically by the application if SPI interrupts are disabled. 635 * 636 * @param spi Pointer to SPI registers (selects the SPI block used.) 637 */ 638 void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi); 639 640 /** 641 * @brief Enable/Disable HW CS control feature. 642 * 643 * Depending on the application, the user might need to manually drive the slave select pin. 644 * The SPI driver automatically drives the SS pin and this function enables/disables this 645 * feature. 646 * 647 * @param spi Pointer to SPI registers (selects the SPI block used.) 648 * @param state Non-zero values: enable HW SS mode. Zero: disable HW SS mode. 649 */ 650 void MXC_SPI_HWSSControl(mxc_spi_regs_t *spi, int state); 651 652 /**@} end of group spi */ 653 654 #ifdef __cplusplus 655 } 656 #endif 657 658 #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPI_H_ 659
