1 /** 2 * @file hpb.h 3 * @brief HyperBus (HPB) function prototypes and data types. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 /* Define to prevent redundant inclusion */ 27 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32650_HPB_H_ 28 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32650_HPB_H_ 29 30 /* **** Includes **** */ 31 #include "hpb_regs.h" 32 #include "mxc_sys.h" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /** 39 * @defgroup hpb HyperBus (HPB) 40 * @ingroup periphlibs 41 * @{ 42 */ 43 44 /* **** Definitions **** */ 45 /** 46 * Structure type containing register offset-value pairs. 47 */ 48 typedef struct { 49 uint32_t addr; /**< Offset from port base */ 50 uint32_t val; /* < Value */ 51 } mxc_hpb_cfg_reg_val_t; 52 53 /** 54 * Enumeration type to select the number of cycles CS is high. 55 */ 56 typedef enum { 57 MXC_HPB_CS_HIGH_1_5 = 0, /**< CS High 1.5 clock cycles */ 58 MXC_HPB_CS_HIGH_2_5, /**< CS High 2.5 clock cycles */ 59 MXC_HPB_CS_HIGH_3_5, /**< CS High 3.5 clock cycles */ 60 MXC_HPB_CS_HIGH_4_5, /**< CS High 4.5 clock cycles */ 61 MXC_HPB_CS_HIGH_5_5, /**< CS High 5.5 clock cycles */ 62 MXC_HPB_CS_HIGH_6_5, /**< CS High 6.5 clock cycles */ 63 MXC_HPB_CS_HIGH_7_5, /**< CS High 7.5 clock cycles */ 64 MXC_HPB_CS_HIGH_8_5, /**< CS High 8.5 clock cycles */ 65 MXC_HPB_CS_HIGH_9_5, /**< CS High 9.5 clock cycles */ 66 MXC_HPB_CS_HIGH_10_5, /**< CS High 10.5 clock cycles */ 67 MXC_HPB_CS_HIGH_11_5, /**< CS High 11.5 clock cycles */ 68 MXC_HPB_CS_HIGH_12_5, /**< CS High 12.5 clock cycles */ 69 MXC_HPB_CS_HIGH_13_5, /**< CS High 13.5 clock cycles */ 70 MXC_HPB_CS_HIGH_14_5, /**< CS High 14.5 clock cycles */ 71 MXC_HPB_CS_HIGH_15_5, /**< CS High 15.5 clock cycles */ 72 MXC_HPB_CS_HIGH_16_5, /**< CS High 16.5 clock cycles */ 73 } mxc_hpb_cs_high_t; 74 75 /** 76 * Enumeration type to select the number of clock cycles between asserting the CS signal and the first clock cycle. 77 */ 78 typedef enum { 79 MXC_HPB_CS_SETUP_HOLD_1 = 0x0, /**< CS Setup/Hold 1 clock cycles */ 80 MXC_HPB_CS_SETUP_HOLD_2, /**< CS Setup/Hold 2 clock cycles */ 81 MXC_HPB_CS_SETUP_HOLD_3, /**< CS Setup/Hold 3 clock cycles */ 82 MXC_HPB_CS_SETUP_HOLD_4, /**< CS Setup/Hold 4 clock cycles */ 83 MXC_HPB_CS_SETUP_HOLD_5, /**< CS Setup/Hold 5 clock cycles */ 84 MXC_HPB_CS_SETUP_HOLD_6, /**< CS Setup/Hold 6 clock cycles */ 85 MXC_HPB_CS_SETUP_HOLD_7, /**< CS Setup/Hold 7 clock cycles */ 86 MXC_HPB_CS_SETUP_HOLD_8, /**< CS Setup/Hold 8 clock cycles */ 87 MXC_HPB_CS_SETUP_HOLD_9, /**< CS Setup/Hold 9 clock cycles */ 88 MXC_HPB_CS_SETUP_HOLD_10, /**< CS Setup/Hold 10 clock cycles */ 89 MXC_HPB_CS_SETUP_HOLD_11, /**< CS Setup/Hold 11 clock cycles */ 90 MXC_HPB_CS_SETUP_HOLD_12, /**< CS Setup/Hold 12 clock cycles */ 91 MXC_HPB_CS_SETUP_HOLD_13, /**< CS Setup/Hold 13 clock cycles */ 92 MXC_HPB_CS_SETUP_HOLD_14, /**< CS Setup/Hold 14 clock cycles */ 93 MXC_HPB_CS_SETUP_HOLD_15, /**< CS Setup/Hold 15 clock cycles */ 94 MXC_HPB_CS_SETUP_HOLD_16, /**< CS Setup/Hold 16 clock cycles */ 95 } mxc_hpb_cs_setup_hold_t; 96 97 /** 98 * Enumeration type to select the number of clock cycles for the latency of RAM operations. 99 */ 100 typedef enum { 101 MXC_HPB_LATENCY_5 = MXC_V_HPB_MTR_LATENCY_5CLK, /**< 5 clock latency for RAM */ 102 MXC_HPB_LATENCY_6 = MXC_V_HPB_MTR_LATENCY_6CLK, /**< 6 clock latency for RAM */ 103 MXC_HPB_LATENCY_3 = MXC_V_HPB_MTR_LATENCY_3CLK, /**< 3 clock latency for RAM */ 104 MXC_HPB_LATENCY_4 = MXC_V_HPB_MTR_LATENCY_4CLK, /**< 4 clock latency for RAM */ 105 } mxc_hpb_latency_t; 106 107 /** 108 * Enumeration type to select the type of device connected to the HPB controller. 109 */ 110 typedef enum { 111 MXC_HPB_DEV_HYPER_FLASH = MXC_V_HPB_MCR_DEV_TYPE_HYPERFLASH, 112 MXC_HPB_DEV_XCCELA_PSRAM = MXC_V_HPB_MCR_DEV_TYPE_XCCELAPSRAM, 113 MXC_HPB_DEV_HYPER_RAM = MXC_V_HPB_MCR_DEV_TYPE_HYPERRAM, 114 } mxc_hpb_device_t; 115 116 /** 117 * Structure type to configure the HPB controller. 118 */ 119 typedef struct { 120 /** The base address for memory space */ 121 uint32_t base_addr; 122 123 /** Type of device attached to controller */ 124 mxc_hpb_device_t device_type; 125 126 /** Pointer to array of address offset/value pairs */ 127 mxc_hpb_cfg_reg_val_t *cfg_reg_val; 128 129 /** number of configuration pairs */ 130 unsigned int cfg_reg_val_len; 131 132 /** Before the read access, this setting inserts the CK cycles to the chip select */ 133 /** high period. */ 134 mxc_hpb_cs_high_t read_cs_high; 135 136 /** Before the write access, this setting inserts the CK cycles to the chip select */ 137 /** high period. */ 138 mxc_hpb_cs_high_t write_cs_high; 139 140 /** In the read access, this setting inserts the CK cycles, between the falling edge */ 141 /** of chip select and the rising edge of first CK. */ 142 mxc_hpb_cs_setup_hold_t read_cs_setup; 143 144 /** In the write access, this setting inserts the CK cycles, between the falling */ 145 /** edge of chip select and the rising edge of first CK. */ 146 mxc_hpb_cs_setup_hold_t write_cs_setup; 147 148 /** In the read access, this setting inserts the CK cycles, between the falling */ 149 /** edge of last CK and the rising edge of chip select. */ 150 mxc_hpb_cs_setup_hold_t read_cs_hold; 151 152 /** In the write access, this setting inserts the CK cycles, between the falling */ 153 /** edge of last CK and the rising edge of chip select */ 154 mxc_hpb_cs_setup_hold_t write_cs_hold; 155 156 /** Latency Cycle for HyperRAM mode, ignored when the connected device is HyperFlash */ 157 mxc_hpb_latency_t latency_cycle; 158 159 unsigned int fixed_latency; 160 } mxc_hpb_mem_config_t; 161 162 /* **** Function Prototypes **** */ 163 /** 164 * @brief Read a variable 165 * @param cfg_reg_val Pointer to configuration struct to read a variable 166 * @param base_addr Base address 167 * @param index 0 or 1 to determine which configuration settings 168 */ 169 void MXC_HPB_RegRead8(mxc_hpb_cfg_reg_val_t *cfg_reg_val, uint32_t base_addr, unsigned int index); 170 171 /** 172 * @brief Read a variable 173 * @param cfg_reg_val Pointer to configuration struct to read a variable 174 * @param base_addr Base address 175 * @param index 0 or 1 to determine which configuration settings 176 */ 177 void MXC_HPB_RegWrite8(mxc_hpb_cfg_reg_val_t *cfg_reg_val, uint32_t base_addr, unsigned int index); 178 179 /** 180 * @brief Read a variable 181 * @param cfg_reg_val Pointer to configuration struct to read a variable 182 * @param base_addr Base address 183 * @param index 0 or 1 to determine which configuration settings 184 */ 185 void MXC_HPB_RegRead16(mxc_hpb_cfg_reg_val_t *cfg_reg_val, uint32_t base_addr, unsigned int index); 186 187 /** 188 * @brief Read a variable 189 * @param cfg_reg_val Pointer to configuration struct to read a variable 190 * @param base_addr Base address 191 * @param index 0 or 1 to determine which configuration settings 192 */ 193 void MXC_HPB_RegWrite16(mxc_hpb_cfg_reg_val_t *cfg_reg_val, uint32_t base_addr, unsigned int index); 194 195 /** 196 * @brief Configure the HyperBus peripheral. 197 * @param mem0 Pointer to configuration struct for mem0 (may be NULL if 198 * this memory not used) 199 * @param mem1 Pointer to configuration struct for mem1 (may be NULL if 200 * this memory not used) 201 * @return #E_BAD_PARAM if configuration error, #E_NO_ERROR otherwise 202 */ 203 int MXC_HPB_Init(mxc_hpb_mem_config_t *mem0, mxc_hpb_mem_config_t *mem1); 204 205 /** 206 * @brief Returns the contents of the status register. 207 * @note Use MXC_F_HPB_CSR macros to filter out specific status bits. 208 * @return HPB status register. 209 */ 210 uint32_t MXC_HPB_GetStatus(void); 211 212 /** 213 * @brief Enable HPB interrupt. 214 * @param polarity 1 to use active high, 0 to use active low. 215 */ 216 void MXC_HPB_EnableInt(unsigned polarity); 217 218 /** 219 * @brief Get HPB interrupt status. 220 * @return 1 if flag is set, 0 if not. 221 */ 222 unsigned MXC_HPB_GetFlag(void); 223 224 /**@} end of group hpb */ 225 226 #ifdef __cplusplus 227 } 228 #endif 229 230 #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32650_HPB_H_ 231
