1 /** 2 * @file dma.h 3 * @brief Direct Memory Access (DMA) driver function prototypes and data types. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32572_DMA_H_ 27 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32572_DMA_H_ 28 29 /* **** Includes **** */ 30 #include <stdbool.h> 31 #include "mxc_device.h" 32 #include "dma_regs.h" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /** 39 * @defgroup dma Direct Memory Access (DMA) 40 * @ingroup periphlibs 41 * @{ 42 */ 43 44 /* **** Definitions **** */ 45 46 /** 47 * @brief Enumeration for the DMA Channel's priority level. 48 * 49 */ 50 typedef enum { 51 MXC_DMA_PRIO_HIGH = MXC_V_DMA_CTRL_PRI_HIGH, ///< High Priority 52 MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CTRL_PRI_MEDHIGH, ///< Medium High Priority 53 MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CTRL_PRI_MEDLOW, ///< Medium Low Priority 54 MXC_DMA_PRIO_LOW = MXC_V_DMA_CTRL_PRI_LOW, ///< Low Priority 55 } mxc_dma_priority_t; 56 57 /** @brief DMA request select */ 58 typedef enum { 59 MXC_DMA_REQUEST_MEMTOMEM = 60 MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection 61 MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX, ///< SPI0 Receive DMA Request Selection 62 MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX, ///< SPI1 Receive DMA Request Selection 63 MXC_DMA_REQUEST_UART0RX = 64 MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection 65 MXC_DMA_REQUEST_UART1RX = 66 MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection 67 MXC_DMA_REQUEST_SC0RX = MXC_S_DMA_CTRL_REQUEST_SC0RX, ///< SC0 Receive DMA Request Selection 68 MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CTRL_REQUEST_I2C0RX, ///< I2C0 Receive DMA Request Selection 69 MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CTRL_REQUEST_I2C1RX, ///< I2C1 Receive DMA Request Selection 70 MXC_DMA_REQUEST_ADC = MXC_S_DMA_CTRL_REQUEST_ADC, ///< ADC DMA Request Selection 71 MXC_DMA_REQUEST_MSRADC = MXC_S_DMA_CTRL_REQUEST_MSRADC, ///< MSR ADC DMA Request Selection 72 MXC_DMA_REQUEST_UART2RX = 73 MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection 74 MXC_DMA_REQUEST_SPI3RX = MXC_S_DMA_CTRL_REQUEST_SPI3RX, ///< SPI3 Receive DMA Request Selection 75 MXC_DMA_REQUEST_USBRXEP1 = 76 MXC_S_DMA_CTRL_REQUEST_USBRXEP1, ///< USB Receive Endpoint 1 DMA Request Selection 77 MXC_DMA_REQUEST_USBRXEP2 = 78 MXC_S_DMA_CTRL_REQUEST_USBRXEP2, ///< USB Receive Endpoint 2 DMA Request Selection 79 MXC_DMA_REQUEST_USBRXEP3 = 80 MXC_S_DMA_CTRL_REQUEST_USBRXEP3, ///< USB Receive Endpoint 3 DMA Request Selection 81 MXC_DMA_REQUEST_USBRXEP4 = 82 MXC_S_DMA_CTRL_REQUEST_USBRXEP4, ///< USB Receive Endpoint 4 DMA Request Selection 83 MXC_DMA_REQUEST_USBRXEP5 = 84 MXC_S_DMA_CTRL_REQUEST_USBRXEP5, ///< USB Receive Endpoint 5 DMA Request Selection 85 MXC_DMA_REQUEST_USBRXEP6 = 86 MXC_S_DMA_CTRL_REQUEST_USBRXEP6, ///< USB Receive Endpoint 6 DMA Request Selection 87 MXC_DMA_REQUEST_USBRXEP7 = 88 MXC_S_DMA_CTRL_REQUEST_USBRXEP7, ///< USB Receive Endpoint 7 DMA Request Selection 89 MXC_DMA_REQUEST_USBRXEP8 = 90 MXC_S_DMA_CTRL_REQUEST_USBRXEP8, ///< USB Receive Endpoint 8 DMA Request Selection 91 MXC_DMA_REQUEST_USBRXEP9 = 92 MXC_S_DMA_CTRL_REQUEST_USBRXEP9, ///< USB Receive Endpoint 9 DMA Request Selection 93 MXC_DMA_REQUEST_USBRXEP10 = 94 MXC_S_DMA_CTRL_REQUEST_USBRXEP10, ///< USB Receive Endpoint 10 DMA Request Selection 95 MXC_DMA_REQUEST_USBRXEP11 = 96 MXC_S_DMA_CTRL_REQUEST_USBRXEP11, ///< USB Receive Endpoint 11 DMA Request Selection 97 MXC_DMA_REQUEST_UART3RX = 98 MXC_S_DMA_CTRL_REQUEST_UART3RX, ///< UART3 Receive DMA Request Selection 99 MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection 100 MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection 101 MXC_DMA_REQUEST_UART0TX = 102 MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection 103 MXC_DMA_REQUEST_UART1TX = 104 MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection 105 MXC_DMA_REQUEST_SC0TX = MXC_S_DMA_CTRL_REQUEST_SC0TX, ///< SC0 Transmit DMA Request Selection 106 MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CTRL_REQUEST_I2C0TX, ///< I2C0 Transmit DMA Request Selection 107 MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CTRL_REQUEST_I2C1TX, ///< I2C1 Transmit DMA Request Selection 108 MXC_DMA_REQUEST_UART2TX = 109 MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART 2 Transmit DMA Request Selection 110 MXC_DMA_REQUEST_SPI3TX = MXC_S_DMA_CTRL_REQUEST_SPI3TX, ///< SPI3 Transmit DMA Request Selection 111 MXC_DMA_REQUEST_USBTXEP1 = 112 MXC_S_DMA_CTRL_REQUEST_USBTXEP1, ///< USB TX Endpoint 1 DMA Request Selection 113 MXC_DMA_REQUEST_USBTXEP2 = 114 MXC_S_DMA_CTRL_REQUEST_USBTXEP2, ///< USB TX Endpoint 2 DMA Request Selection 115 MXC_DMA_REQUEST_USBTXEP3 = 116 MXC_S_DMA_CTRL_REQUEST_USBTXEP3, ///< USB TX Endpoint 3 DMA Request Selection 117 MXC_DMA_REQUEST_USBTXEP4 = 118 MXC_S_DMA_CTRL_REQUEST_USBTXEP4, ///< USB TX Endpoint 4 DMA Request Selection 119 MXC_DMA_REQUEST_USBTXEP5 = 120 MXC_S_DMA_CTRL_REQUEST_USBTXEP5, ///< USB TX Endpoint 5 DMA Request Selection 121 MXC_DMA_REQUEST_USBTXEP6 = 122 MXC_S_DMA_CTRL_REQUEST_USBTXEP6, ///< USB TX Endpoint 6 DMA Request Selection 123 MXC_DMA_REQUEST_USBTXEP7 = 124 MXC_S_DMA_CTRL_REQUEST_USBTXEP7, ///< USB TX Endpoint 7 DMA Request Selection 125 MXC_DMA_REQUEST_USBTXEP8 = 126 MXC_S_DMA_CTRL_REQUEST_USBTXEP8, ///< USB TX Endpoint 8 DMA Request Selection 127 MXC_DMA_REQUEST_USBTXEP9 = 128 MXC_S_DMA_CTRL_REQUEST_USBTXEP9, ///< USB TX Endpoint 9 DMA Request Selection 129 MXC_DMA_REQUEST_USBTXEP10 = 130 MXC_S_DMA_CTRL_REQUEST_USBTXEP10, ///< USB TX Endpoint 10 DMA Request Selection 131 MXC_DMA_REQUEST_USBTXEP11 = 132 MXC_S_DMA_CTRL_REQUEST_USBTXEP11, ///< USB TX Endpoint 11 DMA Request Selection 133 MXC_DMA_REQUEST_UART3TX = 134 MXC_S_DMA_CTRL_REQUEST_UART3TX, ///< UART3 Transmit DMA Request Selection 135 } mxc_dma_reqsel_t; 136 137 /** @brief Enumeration for the DMA prescaler */ 138 typedef enum { 139 MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CTRL_TO_CLKDIV_DIS, ///< Prescaler disabled 140 MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CTRL_TO_CLKDIV_DIV256, ///< Divide by 256 141 MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K, ///< Divide by 65,536 142 MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M, ///< Divide by 16,777,216 143 } mxc_dma_prescale_t; 144 145 /** @brief Enumeration for the DMA timeout value */ 146 typedef enum { 147 MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CTRL_TO_PER_TO4, ///< DMA timeout of 4 clocks 148 MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CTRL_TO_PER_TO8, ///< DMA timeout of 8 clocks 149 MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CTRL_TO_PER_TO16, ///< DMA timeout of 16 clocks 150 MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CTRL_TO_PER_TO32, ///< DMA timeout of 32 clocks 151 MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CTRL_TO_PER_TO64, ///< DMA timeout of 64 clocks 152 MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CTRL_TO_PER_TO128, ///< DMA timeout of 128 clocks 153 MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CTRL_TO_PER_TO256, ///< DMA timeout of 256 clocks 154 MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CTRL_TO_PER_TO512, ///< DMA timeout of 512 clocks 155 } mxc_dma_timeout_t; 156 157 /** @brief DMA transfer data width */ 158 typedef enum { 159 /* Using the '_V_' define instead of the '_S_' since these same values will be used to 160 specify the DSTWD also. The API functions will shift the value the correct amount 161 prior to writing the cfg register. */ 162 MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CTRL_SRCWD_BYTE, ///< DMA transfer in bytes 163 MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CTRL_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words 164 MXC_DMA_WIDTH_WORD = MXC_V_DMA_CTRL_SRCWD_WORD, ///< DMA transfer in 32-bit words 165 } mxc_dma_width_t; 166 167 /** 168 * @brief The basic configuration information to set up a DMA channel 169 * and prepare it for transfers. 170 * 171 */ 172 typedef struct { 173 int ch; ///< The channel to load the configuration data into 174 mxc_dma_reqsel_t reqsel; ///< The request select line to be used (mem2mem, peripheral) 175 mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width) 176 mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width) 177 int srcinc_en; ///< Whether to increment the source address during the transfer 178 int dstinc_en; ///< Whether to increment the source address during the transfer 179 } mxc_dma_config_t; 180 181 /** 182 * @brief The information needed to complete a DMA transfer 183 * 184 */ 185 typedef struct { 186 int ch; ///< The channel to use for the transfer 187 void *source; ///< Pointer to the source address, if applicable 188 void *dest; ///< Pointer to the destination address, if applicable 189 int len; ///< Number of bytes to transfer 190 } mxc_dma_srcdst_t; 191 192 /** 193 * @brief The advanced configuration options, these are optional but could 194 * be needed in cases where multiple DMA channels are running concurrently 195 * or DMA is being used with low bandwidth peripherals. 196 * 197 */ 198 typedef struct { 199 int ch; ///< The channel to use for the transfer 200 mxc_dma_priority_t prio; ///< The DMA priority for the channel 201 unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer 202 mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout 203 mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer 204 unsigned int burst_size; ///< Number of bytes moved in a single burst 205 } mxc_dma_adv_config_t; 206 207 /** 208 * @brief The callback called on completion of a DMA_MemCpy() transfer 209 * 210 * @param dest Pointer to the destination of the copy 211 */ 212 typedef void (*mxc_dma_complete_cb_t)(void *dest); 213 214 /** 215 * @brief The callback called on completion of a transfer, 216 * @note This callback is used with MXC_DMA_DoTransfer() 217 * to allow the user to chain an unlimited number of 218 * DMA Transfers. 219 * 220 * @param trans Struct of the completed transfer 221 * 222 * @return Returns the next transfer to be completed, or NULL 223 * if no more transfers will be done 224 */ 225 typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); 226 227 /* **** Function Prototypes **** */ 228 /*************************/ 229 /* Low Level Functions */ 230 /*************************/ 231 /** 232 * @brief Initialize DMA resources 233 * @details This initialization is required before using the DMA driver functions. 234 * @note On default this function enables DMA peripheral clock. 235 * if you wish to manage clock and gpio related things in upper level instead of here. 236 * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. 237 * By this flag this function will remove clock and gpio related codes from file. 238 * @return #E_NO_ERROR if successful 239 */ 240 int MXC_DMA_Init(void); 241 242 /** 243 * @brief De-Initialize DMA resources. 244 */ 245 void MXC_DMA_DeInit(void); 246 247 /** 248 * @brief Request DMA channel 249 * @details Returns a handle to the first free DMA channel, which can be used via API calls 250 * or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function. 251 * @return Non-negative channel handle (inclusive of zero). 252 * @return #E_NONE_AVAIL All channels in use. 253 * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. 254 * @return #E_BUSY DMA is currently busy (locked), try again later. 255 */ 256 int MXC_DMA_AcquireChannel(void); 257 258 /** 259 * @brief Release DMA channel 260 * @details Stops any DMA operation on the channel and returns it to the pool of free channels. 261 * 262 * @param ch channel handle to release 263 * 264 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 265 */ 266 int MXC_DMA_ReleaseChannel(int ch); 267 268 /** 269 * @brief Configure the DMA channel 270 * @details Configures the channel, which was previously requested by MXC_DMA_Getchannel() 271 * 272 * @param config Struct containing DMA configuration parameters 273 * @param srcdst Struct containing pointers and length of DMA operation 274 * 275 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 276 */ 277 int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); 278 279 /** 280 * @brief Configure the DMA channel with more advanced parameters 281 * 282 * @param advConfig Struct containing advanced DMA parameters 283 * 284 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 285 */ 286 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig); 287 288 /** 289 * @brief Set channel source, destination, and count for the transfer 290 * @param srcdst Struct containing the channel, source, destination, and count for the channel 291 * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, 292 * either src_addr or dst_addr will be ignored by the DMA engine. 293 * In these cases, the address is a don't-care. See the User's 294 * Guide for more information. 295 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 296 */ 297 int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst); 298 299 /** 300 * @brief Get channel source, destination, and count for transfer 301 * 302 * @param srcdst Pointer to struct with the correct channel number 303 * 304 * @return See \ref MXC_Error_Codes for a list of return values 305 */ 306 int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst); 307 308 /** 309 * @brief Set channel reload source, destination, and count for the transfer 310 * @param srcdstReload Struct containing the channel, source, destination, and count for the channel 311 * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, 312 * either src_addr or dst_addr will be ignored by the DMA engine. 313 * In these cases, the address is a don't-care. See the User's 314 * Guide for more information. 315 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 316 */ 317 int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdstReload); 318 319 /** 320 * @brief Get channel reload source, destination, and count for transfer 321 * 322 * @param srcdstReload Pointer to struct with the correct channel number 323 * 324 * @return See \ref MXC_Error_Codes for a list of return values 325 */ 326 int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload); 327 328 /** 329 * @brief Set channel interrupt callback 330 * @param ch channel handle 331 * @param callback Pointer to a function to call when the channel 332 * interrupt flag is set and interrupts are enabled or 333 * when DMA is shutdown by the driver. 334 * @details Configures the channel interrupt callback. The @p callback 335 * function is called for two conditions: 336 * -# When the channel's interrupt flag is set and DMA interrupts 337 * are enabled. 338 * -# If the driver calls the MXC_DMA_Shutdown() function. The 339 * callback function prototype is: 340 * @code 341 * void callback_fn(int ch, int reason); 342 * @endcode 343 * @p ch indicates the channel that generated the callback, @p 344 * reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN 345 * if the DMA is being shutdown. 346 * 347 * @return #E_BAD_PARAM if an unused or invalid channel handle, 348 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 349 */ 350 int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)); 351 352 /** 353 * @brief Set channel interrupt 354 * @note Each channel has two interrupts (complete, and count to zero). 355 * To enable complete, pass true for chdis. To enable count to zero, 356 * pass true for ctz. 357 * @param ch Channel Handle 358 * @param chdis Enable channel complete interrupt 359 * @param ctz Enable channel count to zero interrupt. 360 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 361 */ 362 int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz); 363 364 /** 365 * @brief Enable channel interrupt 366 * @note Each channel has two interrupts (complete, and count to zero) 367 which must also be enabled with MXC_DMA_SetChannelInterruptEn() 368 * @param ch channel handle 369 * @param flags The flags to enable 370 * @return #E_BAD_PARAM if an unused or invalid channel handle, 371 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 372 */ 373 int MXC_DMA_ChannelEnableInt(int ch, int flags); 374 375 /** 376 * @brief Disable channel interrupt 377 * @param ch channel handle 378 * @param flags The flags to disable 379 * @return #E_BAD_PARAM if an unused or invalid channel handle, 380 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 381 */ 382 int MXC_DMA_ChannelDisableInt(int ch, int flags); 383 384 /** 385 * @brief Read channel interrupt flags 386 * @param ch channel handle 387 * @return #E_BAD_PARAM if an unused or invalid channel handle, 388 * flags otherwise, \ref MXC_Error_Codes 389 */ 390 int MXC_DMA_ChannelGetFlags(int ch); 391 392 /** 393 * @brief Clear channel interrupt flags 394 * @param ch channel handle 395 * @param flags The flags to clear 396 * @return #E_BAD_PARAM if an unused or invalid channel handle, 397 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 398 */ 399 int MXC_DMA_ChannelClearFlags(int ch, int flags); 400 401 /** 402 * @brief Enable channel interrupt 403 * @note Each channel has two interrupts (complete, and count to zero) 404 which must also be enabled with MXC_DMA_SetChannelInterruptEn() 405 * @param ch channel handle 406 * @return #E_BAD_PARAM if an unused or invalid channel handle, 407 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 408 */ 409 int MXC_DMA_EnableInt(int ch); 410 411 /** 412 * @brief Disable channel interrupt 413 * @param ch channel handle 414 * @return #E_BAD_PARAM if an unused or invalid channel handle, 415 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 416 */ 417 int MXC_DMA_DisableInt(int ch); 418 419 /** 420 * @brief Start transfer 421 * @param ch channel handle 422 * @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. 423 * @return #E_BAD_PARAM if an unused or invalid channel handle, 424 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 425 */ 426 int MXC_DMA_Start(int ch); 427 428 /** 429 * @brief Stop DMA transfer, irrespective of status (complete or in-progress) 430 * @param ch channel handle 431 * @return #E_BAD_PARAM if an unused or invalid channel handle, 432 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 433 */ 434 int MXC_DMA_Stop(int ch); 435 436 /** 437 * @brief Get a pointer to the DMA channel registers 438 * @param ch channel handle 439 * @details If direct access to DMA channel registers is required, this 440 * function can be used on a channel handle returned by MXC_DMA_AcquireChannel(). 441 * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise 442 */ 443 mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch); 444 445 /** 446 * @brief Interrupt handler function 447 * @details Call this function as the ISR for each DMA channel under driver control. 448 * Interrupt flags for channel ch will be automatically cleared before return. 449 */ 450 void MXC_DMA_Handler(void); 451 452 /*************************/ 453 /* High Level Functions */ 454 /*************************/ 455 456 /** 457 * @brief Performs a memcpy, using DMA, optionally asynchronous 458 * @note The user must have the DMA interrupt enabled and call 459 * MXC_DMA_Handler() from the ISR. 460 * 461 * @param dest pointer to destination memory 462 * @param src pointer to source memory 463 * @param len number of bytes to copy 464 * @param callback function to call when transfer is complete 465 * 466 * @return see \ref MXC_Error_Codes 467 */ 468 int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback); 469 470 /** 471 * @brief Performs a memcpy, using DMA, optionally asynchronous 472 * @note The user must have the DMA interrupt enabled and call 473 * MXC_DMA_Handler() from the ISR. 474 * 475 * @param config The channel config struct 476 * @param firstSrcDst The source, destination, and count for the first transfer 477 * @param callback function is called when transfer is complete 478 * 479 * @return see \ref MXC_Error_Codes 480 */ 481 int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, 482 mxc_dma_trans_chain_t callback); 483 /** 484 * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver 485 */ 486 487 /**@} end of group dma */ 488 #ifdef __cplusplus 489 } 490 #endif 491 492 #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32572_DMA_H_ 493
