1 /** 2 * @file mxc_pins.h 3 * @brief This file contains constant pin configurations for the peripherals. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32570_MXC_PINS_H_ 27 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32570_MXC_PINS_H_ 28 29 #include "gpio.h" 30 31 /***** Global Variables *****/ 32 typedef enum { MAP_A, MAP_B } sys_map_t; 33 34 // Predefined GPIO Configurations 35 extern const mxc_gpio_cfg_t gpio_cfg_i2c0; 36 extern const mxc_gpio_cfg_t gpio_cfg_i2c1; 37 extern const mxc_gpio_cfg_t gpio_cfg_i2c2; 38 extern const mxc_gpio_cfg_t gpio_cfg_i2c2b; 39 extern const mxc_gpio_cfg_t gpio_cfg_i2c2c; 40 41 extern const mxc_gpio_cfg_t gpio_cfg_uart0; 42 extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow; 43 extern const mxc_gpio_cfg_t gpio_cfg_uart1; 44 extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow; 45 extern const mxc_gpio_cfg_t gpio_cfg_uart2; 46 extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow; 47 extern const mxc_gpio_cfg_t gpio_cfg_uart3; 48 extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow; 49 extern const mxc_gpio_cfg_t gpio_cfg_uart4; 50 extern const mxc_gpio_cfg_t gpio_cfg_uart4b; 51 extern const mxc_gpio_cfg_t gpio_cfg_uart4c; 52 extern const mxc_gpio_cfg_t gpio_cfg_uart4_flow; 53 extern const mxc_gpio_cfg_t gpio_cfg_uart4b_flow; 54 extern const mxc_gpio_cfg_t gpio_cfg_uart4c_flow; 55 extern const mxc_gpio_cfg_t gpio_cfg_uart5; 56 extern const mxc_gpio_cfg_t gpio_cfg_uart5b; 57 extern const mxc_gpio_cfg_t gpio_cfg_uart5_flow; 58 extern const mxc_gpio_cfg_t gpio_cfg_uart5b_flow; 59 // NOTE: uart5b flow control is split across port pins 0.31 and 1.0 60 extern const mxc_gpio_cfg_t gpio_cfg_uart5c_P1_flow; 61 extern const mxc_gpio_cfg_t gpio_cfg_uart5c_P0_flow; 62 63 extern const mxc_gpio_cfg_t gpio_cfg_spi0; 64 // NOTE: SPI1 definied here with SS1 only, SS0 is on port0 by itself. 65 extern const mxc_gpio_cfg_t gpio_cfg_spi1; 66 // NOTE: SPI2 defined here with SS0 only, and NOT SS1 and SS2 67 extern const mxc_gpio_cfg_t gpio_cfg_spi2; 68 extern const mxc_gpio_cfg_t gpio_cfg_spi2b; 69 // NOTE: SPI3 defined here with SS0 only, and NOT SS1, SS2, or SS3 70 extern const mxc_gpio_cfg_t gpio_cfg_spi3; 71 72 // Timers are only defined once, depending on package, each timer could be mapped to other pins 73 extern const mxc_gpio_cfg_t gpio_cfg_tmr0; 74 extern const mxc_gpio_cfg_t gpio_cfg_tmr1; 75 extern const mxc_gpio_cfg_t gpio_cfg_tmr2; 76 extern const mxc_gpio_cfg_t gpio_cfg_tmr3; 77 extern const mxc_gpio_cfg_t gpio_cfg_tmr4; 78 extern const mxc_gpio_cfg_t gpio_cfg_tmr5; 79 80 // Pulse trains are only defined once, depending on package, each PT could be mapped to other pins 81 extern const mxc_gpio_cfg_t gpio_cfg_pt0; 82 extern const mxc_gpio_cfg_t gpio_cfg_pt1; 83 extern const mxc_gpio_cfg_t gpio_cfg_pt2; 84 extern const mxc_gpio_cfg_t gpio_cfg_pt3; 85 extern const mxc_gpio_cfg_t gpio_cfg_pt4; 86 extern const mxc_gpio_cfg_t gpio_cfg_pt5; 87 extern const mxc_gpio_cfg_t gpio_cfg_pt6; 88 extern const mxc_gpio_cfg_t gpio_cfg_pt7; 89 90 extern const mxc_gpio_cfg_t gpio_cfg_owm; 91 extern const mxc_gpio_cfg_t gpio_cfg_owmb; 92 93 // Port 0 Pins 6-14, Port 1 Pins 1-5 and 16-19, Port 2 Pins 10-19 94 // Other configurations are available, depending on package, to allow the use of EMAC or SDHC 95 // Note that both P1a and P1b must be configured for proper operation 96 extern const mxc_gpio_cfg_t gpio_cfg_P0_clcd; 97 extern const mxc_gpio_cfg_t gpio_cfg_P1a_clcd; 98 extern const mxc_gpio_cfg_t gpio_cfg_P1b_clcd; 99 extern const mxc_gpio_cfg_t gpio_cfg_P2_clcd; 100 101 extern const mxc_gpio_cfg_t gpio_cfg_rtcsqw; 102 extern const mxc_gpio_cfg_t gpio_cfg_rtcsqwb; 103 104 extern const mxc_gpio_cfg_t gpio_cfg_sdhc; 105 extern const mxc_gpio_cfg_t gpio_cfg_sdhcb; 106 107 extern const mxc_gpio_cfg_t gpio_cfg_sc0; 108 extern const mxc_gpio_cfg_t gpio_cfg_sc1; 109 110 // Note that both P0 and P1 must be configured for proper operation 111 extern const mxc_gpio_cfg_t gpio_cfg_spixf; 112 extern const mxc_gpio_cfg_t gpio_cfg_spixr_P0; 113 extern const mxc_gpio_cfg_t gpio_cfg_spixr_P1; 114 115 // Note that both P2a and P2b must be configured for proper operation 116 extern const mxc_gpio_cfg_t gpio_cfg_emac_P2a; 117 extern const mxc_gpio_cfg_t gpio_cfg_emac_P2b; 118 119 // Note that all of the following must be configured for proper operation 120 extern const mxc_gpio_cfg_t gpio_cfg_kbd_P2; 121 122 // Note that both P0 and P1 must be configured for proper operation 123 extern const mxc_gpio_cfg_t gpio_cfg_pcif_P0_BITS_0_7; 124 extern const mxc_gpio_cfg_t gpio_cfg_pcif_P0_BITS_8; 125 extern const mxc_gpio_cfg_t gpio_cfg_pcif_P1_BITS_9; 126 extern const mxc_gpio_cfg_t gpio_cfg_pcif_P1_BITS_10_11; 127 extern const mxc_gpio_cfg_t gpio_cfg_pcif_hsync; 128 extern const mxc_gpio_cfg_t gpio_cfg_pcif_vsync; 129 extern const mxc_gpio_cfg_t gpio_cfg_pcif_pclk; 130 extern const mxc_gpio_cfg_t gpio_cfg_pcif_pwrdwn; 131 132 #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32570_MXC_PINS_H_ 133
