1 /** 2 * @file sdhc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SDHC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup sdhc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_SDHC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_SDHC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup sdhc 67 * @defgroup sdhc_registers SDHC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SDHC Peripheral Module. 69 * @details SDHC/SDIO Controller 70 */ 71 72 /** 73 * @ingroup sdhc_registers 74 * Structure type to access the SDHC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t sdma; /**< <tt>\b 0x00:</tt> SDHC SDMA Register */ 78 __IO uint16_t blk_size; /**< <tt>\b 0x04:</tt> SDHC BLK_SIZE Register */ 79 __IO uint16_t blk_cnt; /**< <tt>\b 0x06:</tt> SDHC BLK_CNT Register */ 80 __IO uint32_t arg_1; /**< <tt>\b 0x08:</tt> SDHC ARG_1 Register */ 81 __IO uint16_t trans; /**< <tt>\b 0x0C:</tt> SDHC TRANS Register */ 82 __IO uint16_t cmd; /**< <tt>\b 0x0E:</tt> SDHC CMD Register */ 83 __IO uint32_t resp[4]; /**< <tt>\b 0x010:</tt> SDHC RESP Register */ 84 __IO uint32_t buffer; /**< <tt>\b 0x20:</tt> SDHC BUFFER Register */ 85 __I uint32_t present; /**< <tt>\b 0x024:</tt> SDHC PRESENT Register */ 86 __IO uint8_t host_cn_1; /**< <tt>\b 0x028:</tt> SDHC HOST_CN_1 Register */ 87 __IO uint8_t pwr; /**< <tt>\b 0x029:</tt> SDHC PWR Register */ 88 __IO uint8_t blk_gap; /**< <tt>\b 0x02A:</tt> SDHC BLK_GAP Register */ 89 __IO uint8_t wakeup; /**< <tt>\b 0x02B:</tt> SDHC WAKEUP Register */ 90 __IO uint16_t clk_cn; /**< <tt>\b 0x02C:</tt> SDHC CLK_CN Register */ 91 __IO uint8_t to; /**< <tt>\b 0x02E:</tt> SDHC TO Register */ 92 __IO uint8_t sw_reset; /**< <tt>\b 0x02F:</tt> SDHC SW_RESET Register */ 93 __IO uint16_t int_stat; /**< <tt>\b 0x030:</tt> SDHC INT_STAT Register */ 94 __IO uint16_t er_int_stat; /**< <tt>\b 0x032:</tt> SDHC ER_INT_STAT Register */ 95 __IO uint16_t int_en; /**< <tt>\b 0x034:</tt> SDHC INT_EN Register */ 96 __IO uint16_t er_int_en; /**< <tt>\b 0x36:</tt> SDHC ER_INT_EN Register */ 97 __IO uint16_t int_signal; /**< <tt>\b 0x038:</tt> SDHC INT_SIGNAL Register */ 98 __IO uint16_t er_int_signal; /**< <tt>\b 0x03A:</tt> SDHC ER_INT_SIGNAL Register */ 99 __IO uint16_t auto_cmd_er; /**< <tt>\b 0x03C:</tt> SDHC AUTO_CMD_ER Register */ 100 __IO uint16_t host_cn_2; /**< <tt>\b 0x03E:</tt> SDHC HOST_CN_2 Register */ 101 __I uint32_t cfg_0; /**< <tt>\b 0x040:</tt> SDHC CFG_0 Register */ 102 __I uint32_t cfg_1; /**< <tt>\b 0x044:</tt> SDHC CFG_1 Register */ 103 __I uint32_t max_curr_cfg; /**< <tt>\b 0x048:</tt> SDHC MAX_CURR_CFG Register */ 104 __R uint32_t rsv_0x4c; 105 __O uint16_t force_cmd; /**< <tt>\b 0x050:</tt> SDHC FORCE_CMD Register */ 106 __IO uint16_t force_event_int_stat; /**< <tt>\b 0x052:</tt> SDHC FORCE_EVENT_INT_STAT Register */ 107 __IO uint8_t adma_er; /**< <tt>\b 0x054:</tt> SDHC ADMA_ER Register */ 108 __R uint8_t rsv_0x55_0x57[3]; 109 __IO uint32_t adma_addr_0; /**< <tt>\b 0x058:</tt> SDHC ADMA_ADDR_0 Register */ 110 __IO uint32_t adma_addr_1; /**< <tt>\b 0x05C:</tt> SDHC ADMA_ADDR_1 Register */ 111 __I uint16_t preset_0; /**< <tt>\b 0x060:</tt> SDHC PRESET_0 Register */ 112 __I uint16_t preset_1; /**< <tt>\b 0x062:</tt> SDHC PRESET_1 Register */ 113 __I uint16_t preset_2; /**< <tt>\b 0x064:</tt> SDHC PRESET_2 Register */ 114 __I uint16_t preset_3; /**< <tt>\b 0x066:</tt> SDHC PRESET_3 Register */ 115 __I uint16_t preset_4; /**< <tt>\b 0x068:</tt> SDHC PRESET_4 Register */ 116 __I uint16_t preset_5; /**< <tt>\b 0x06A:</tt> SDHC PRESET_5 Register */ 117 __I uint16_t preset_6; /**< <tt>\b 0x06C:</tt> SDHC PRESET_6 Register */ 118 __I uint16_t preset_7; /**< <tt>\b 0x06E:</tt> SDHC PRESET_7 Register */ 119 __R uint32_t rsv_0x70_0xdf[28]; 120 __IO uint32_t shared_bus; /**< <tt>\b 0x0E0:</tt> SDHC SHARED_BUS Register */ 121 __R uint32_t rsv_0xe4_0xfb[6]; 122 __I uint16_t slot_int; /**< <tt>\b 0x0FC:</tt> SDHC SLOT_INT Register */ 123 __IO uint16_t host_cn_ver; /**< <tt>\b 0x0FE:</tt> SDHC HOST_CN_VER Register */ 124 } mxc_sdhc_regs_t; 125 126 /* Register offsets for module SDHC */ 127 /** 128 * @ingroup sdhc_registers 129 * @defgroup SDHC_Register_Offsets Register Offsets 130 * @brief SDHC Peripheral Register Offsets from the SDHC Base Peripheral Address. 131 * @{ 132 */ 133 #define MXC_R_SDHC_SDMA ((uint32_t)0x00000000UL) /**< Offset from SDHC Base Address: <tt> 0x0000</tt> */ 134 #define MXC_R_SDHC_BLK_SIZE ((uint32_t)0x00000004UL) /**< Offset from SDHC Base Address: <tt> 0x0004</tt> */ 135 #define MXC_R_SDHC_BLK_CNT ((uint32_t)0x00000006UL) /**< Offset from SDHC Base Address: <tt> 0x0006</tt> */ 136 #define MXC_R_SDHC_ARG_1 ((uint32_t)0x00000008UL) /**< Offset from SDHC Base Address: <tt> 0x0008</tt> */ 137 #define MXC_R_SDHC_TRANS ((uint32_t)0x0000000CUL) /**< Offset from SDHC Base Address: <tt> 0x000C</tt> */ 138 #define MXC_R_SDHC_CMD ((uint32_t)0x0000000EUL) /**< Offset from SDHC Base Address: <tt> 0x000E</tt> */ 139 #define MXC_R_SDHC_RESP ((uint32_t)0x00000010UL) /**< Offset from SDHC Base Address: <tt> 0x0010</tt> */ 140 #define MXC_R_SDHC_BUFFER ((uint32_t)0x00000020UL) /**< Offset from SDHC Base Address: <tt> 0x0020</tt> */ 141 #define MXC_R_SDHC_PRESENT ((uint32_t)0x00000024UL) /**< Offset from SDHC Base Address: <tt> 0x0024</tt> */ 142 #define MXC_R_SDHC_HOST_CN_1 ((uint32_t)0x00000028UL) /**< Offset from SDHC Base Address: <tt> 0x0028</tt> */ 143 #define MXC_R_SDHC_PWR ((uint32_t)0x00000029UL) /**< Offset from SDHC Base Address: <tt> 0x0029</tt> */ 144 #define MXC_R_SDHC_BLK_GAP ((uint32_t)0x0000002AUL) /**< Offset from SDHC Base Address: <tt> 0x002A</tt> */ 145 #define MXC_R_SDHC_WAKEUP ((uint32_t)0x0000002BUL) /**< Offset from SDHC Base Address: <tt> 0x002B</tt> */ 146 #define MXC_R_SDHC_CLK_CN ((uint32_t)0x0000002CUL) /**< Offset from SDHC Base Address: <tt> 0x002C</tt> */ 147 #define MXC_R_SDHC_TO ((uint32_t)0x0000002EUL) /**< Offset from SDHC Base Address: <tt> 0x002E</tt> */ 148 #define MXC_R_SDHC_SW_RESET ((uint32_t)0x0000002FUL) /**< Offset from SDHC Base Address: <tt> 0x002F</tt> */ 149 #define MXC_R_SDHC_INT_STAT ((uint32_t)0x00000030UL) /**< Offset from SDHC Base Address: <tt> 0x0030</tt> */ 150 #define MXC_R_SDHC_ER_INT_STAT ((uint32_t)0x00000032UL) /**< Offset from SDHC Base Address: <tt> 0x0032</tt> */ 151 #define MXC_R_SDHC_INT_EN ((uint32_t)0x00000034UL) /**< Offset from SDHC Base Address: <tt> 0x0034</tt> */ 152 #define MXC_R_SDHC_ER_INT_EN ((uint32_t)0x00000036UL) /**< Offset from SDHC Base Address: <tt> 0x0036</tt> */ 153 #define MXC_R_SDHC_INT_SIGNAL ((uint32_t)0x00000038UL) /**< Offset from SDHC Base Address: <tt> 0x0038</tt> */ 154 #define MXC_R_SDHC_ER_INT_SIGNAL ((uint32_t)0x0000003AUL) /**< Offset from SDHC Base Address: <tt> 0x003A</tt> */ 155 #define MXC_R_SDHC_AUTO_CMD_ER ((uint32_t)0x0000003CUL) /**< Offset from SDHC Base Address: <tt> 0x003C</tt> */ 156 #define MXC_R_SDHC_HOST_CN_2 ((uint32_t)0x0000003EUL) /**< Offset from SDHC Base Address: <tt> 0x003E</tt> */ 157 #define MXC_R_SDHC_CFG_0 ((uint32_t)0x00000040UL) /**< Offset from SDHC Base Address: <tt> 0x0040</tt> */ 158 #define MXC_R_SDHC_CFG_1 ((uint32_t)0x00000044UL) /**< Offset from SDHC Base Address: <tt> 0x0044</tt> */ 159 #define MXC_R_SDHC_MAX_CURR_CFG ((uint32_t)0x00000048UL) /**< Offset from SDHC Base Address: <tt> 0x0048</tt> */ 160 #define MXC_R_SDHC_FORCE_CMD ((uint32_t)0x00000050UL) /**< Offset from SDHC Base Address: <tt> 0x0050</tt> */ 161 #define MXC_R_SDHC_FORCE_EVENT_INT_STAT ((uint32_t)0x00000052UL) /**< Offset from SDHC Base Address: <tt> 0x0052</tt> */ 162 #define MXC_R_SDHC_ADMA_ER ((uint32_t)0x00000054UL) /**< Offset from SDHC Base Address: <tt> 0x0054</tt> */ 163 #define MXC_R_SDHC_ADMA_ADDR_0 ((uint32_t)0x00000058UL) /**< Offset from SDHC Base Address: <tt> 0x0058</tt> */ 164 #define MXC_R_SDHC_ADMA_ADDR_1 ((uint32_t)0x0000005CUL) /**< Offset from SDHC Base Address: <tt> 0x005C</tt> */ 165 #define MXC_R_SDHC_PRESET_0 ((uint32_t)0x00000060UL) /**< Offset from SDHC Base Address: <tt> 0x0060</tt> */ 166 #define MXC_R_SDHC_PRESET_1 ((uint32_t)0x00000062UL) /**< Offset from SDHC Base Address: <tt> 0x0062</tt> */ 167 #define MXC_R_SDHC_PRESET_2 ((uint32_t)0x00000064UL) /**< Offset from SDHC Base Address: <tt> 0x0064</tt> */ 168 #define MXC_R_SDHC_PRESET_3 ((uint32_t)0x00000066UL) /**< Offset from SDHC Base Address: <tt> 0x0066</tt> */ 169 #define MXC_R_SDHC_PRESET_4 ((uint32_t)0x00000068UL) /**< Offset from SDHC Base Address: <tt> 0x0068</tt> */ 170 #define MXC_R_SDHC_PRESET_5 ((uint32_t)0x0000006AUL) /**< Offset from SDHC Base Address: <tt> 0x006A</tt> */ 171 #define MXC_R_SDHC_PRESET_6 ((uint32_t)0x0000006CUL) /**< Offset from SDHC Base Address: <tt> 0x006C</tt> */ 172 #define MXC_R_SDHC_PRESET_7 ((uint32_t)0x0000006EUL) /**< Offset from SDHC Base Address: <tt> 0x006E</tt> */ 173 #define MXC_R_SDHC_SHARED_BUS ((uint32_t)0x000000E0UL) /**< Offset from SDHC Base Address: <tt> 0x00E0</tt> */ 174 #define MXC_R_SDHC_SLOT_INT ((uint32_t)0x000000FCUL) /**< Offset from SDHC Base Address: <tt> 0x00FC</tt> */ 175 #define MXC_R_SDHC_HOST_CN_VER ((uint32_t)0x000000FEUL) /**< Offset from SDHC Base Address: <tt> 0x00FE</tt> */ 176 /**@} end of group sdhc_registers */ 177 178 /** 179 * @ingroup sdhc_registers 180 * @defgroup SDHC_SDMA SDHC_SDMA 181 * @brief SDMA System Address / Argument 2. 182 * @{ 183 */ 184 #define MXC_F_SDHC_SDMA_ADDR_POS 0 /**< SDMA_ADDR Position */ 185 #define MXC_F_SDHC_SDMA_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_SDMA_ADDR_POS)) /**< SDMA_ADDR Mask */ 186 187 /**@} end of group SDHC_SDMA_Register */ 188 189 /** 190 * @ingroup sdhc_registers 191 * @defgroup SDHC_BLK_SIZE SDHC_BLK_SIZE 192 * @brief Block Size. 193 * @{ 194 */ 195 #define MXC_F_SDHC_BLK_SIZE_TRANS_POS 0 /**< BLK_SIZE_TRANS Position */ 196 #define MXC_F_SDHC_BLK_SIZE_TRANS ((uint16_t)(0xFFFUL << MXC_F_SDHC_BLK_SIZE_TRANS_POS)) /**< BLK_SIZE_TRANS Mask */ 197 198 #define MXC_F_SDHC_BLK_SIZE_HOST_BUFF_POS 12 /**< BLK_SIZE_HOST_BUFF Position */ 199 #define MXC_F_SDHC_BLK_SIZE_HOST_BUFF ((uint16_t)(0x7UL << MXC_F_SDHC_BLK_SIZE_HOST_BUFF_POS)) /**< BLK_SIZE_HOST_BUFF Mask */ 200 201 /**@} end of group SDHC_BLK_SIZE_Register */ 202 203 /** 204 * @ingroup sdhc_registers 205 * @defgroup SDHC_BLK_CNT SDHC_BLK_CNT 206 * @brief Block Count. 207 * @{ 208 */ 209 #define MXC_F_SDHC_BLK_CNT_COUNT_POS 0 /**< BLK_CNT_COUNT Position */ 210 #define MXC_F_SDHC_BLK_CNT_COUNT ((uint16_t)(0xFFFFUL << MXC_F_SDHC_BLK_CNT_COUNT_POS)) /**< BLK_CNT_COUNT Mask */ 211 212 /**@} end of group SDHC_BLK_CNT_Register */ 213 214 /** 215 * @ingroup sdhc_registers 216 * @defgroup SDHC_ARG_1 SDHC_ARG_1 217 * @brief Argument 1. 218 * @{ 219 */ 220 #define MXC_F_SDHC_ARG_1_CMD_POS 0 /**< ARG_1_CMD Position */ 221 #define MXC_F_SDHC_ARG_1_CMD ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_ARG_1_CMD_POS)) /**< ARG_1_CMD Mask */ 222 223 /**@} end of group SDHC_ARG_1_Register */ 224 225 /** 226 * @ingroup sdhc_registers 227 * @defgroup SDHC_TRANS SDHC_TRANS 228 * @brief Transfer Mode. 229 * @{ 230 */ 231 #define MXC_F_SDHC_TRANS_DMA_EN_POS 0 /**< TRANS_DMA_EN Position */ 232 #define MXC_F_SDHC_TRANS_DMA_EN ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_DMA_EN_POS)) /**< TRANS_DMA_EN Mask */ 233 234 #define MXC_F_SDHC_TRANS_BLK_CNT_EN_POS 1 /**< TRANS_BLK_CNT_EN Position */ 235 #define MXC_F_SDHC_TRANS_BLK_CNT_EN ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_BLK_CNT_EN_POS)) /**< TRANS_BLK_CNT_EN Mask */ 236 237 #define MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS 2 /**< TRANS_AUTO_CMD_EN Position */ 238 #define MXC_F_SDHC_TRANS_AUTO_CMD_EN ((uint16_t)(0x3UL << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS)) /**< TRANS_AUTO_CMD_EN Mask */ 239 #define MXC_V_SDHC_TRANS_AUTO_CMD_EN_DISABLE ((uint16_t)0x0UL) /**< TRANS_AUTO_CMD_EN_DISABLE Value */ 240 #define MXC_S_SDHC_TRANS_AUTO_CMD_EN_DISABLE (MXC_V_SDHC_TRANS_AUTO_CMD_EN_DISABLE << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS) /**< TRANS_AUTO_CMD_EN_DISABLE Setting */ 241 #define MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD12 ((uint16_t)0x1UL) /**< TRANS_AUTO_CMD_EN_CMD12 Value */ 242 #define MXC_S_SDHC_TRANS_AUTO_CMD_EN_CMD12 (MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD12 << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS) /**< TRANS_AUTO_CMD_EN_CMD12 Setting */ 243 #define MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD23 ((uint16_t)0x2UL) /**< TRANS_AUTO_CMD_EN_CMD23 Value */ 244 #define MXC_S_SDHC_TRANS_AUTO_CMD_EN_CMD23 (MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD23 << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS) /**< TRANS_AUTO_CMD_EN_CMD23 Setting */ 245 246 #define MXC_F_SDHC_TRANS_READ_WRITE_POS 4 /**< TRANS_READ_WRITE Position */ 247 #define MXC_F_SDHC_TRANS_READ_WRITE ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_READ_WRITE_POS)) /**< TRANS_READ_WRITE Mask */ 248 249 #define MXC_F_SDHC_TRANS_MULTI_POS 5 /**< TRANS_MULTI Position */ 250 #define MXC_F_SDHC_TRANS_MULTI ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_MULTI_POS)) /**< TRANS_MULTI Mask */ 251 252 /**@} end of group SDHC_TRANS_Register */ 253 254 /** 255 * @ingroup sdhc_registers 256 * @defgroup SDHC_CMD SDHC_CMD 257 * @brief Command. 258 * @{ 259 */ 260 #define MXC_F_SDHC_CMD_RESP_TYPE_POS 0 /**< CMD_RESP_TYPE Position */ 261 #define MXC_F_SDHC_CMD_RESP_TYPE ((uint16_t)(0x3UL << MXC_F_SDHC_CMD_RESP_TYPE_POS)) /**< CMD_RESP_TYPE Mask */ 262 263 #define MXC_F_SDHC_CMD_CRC_CHK_EN_POS 3 /**< CMD_CRC_CHK_EN Position */ 264 #define MXC_F_SDHC_CMD_CRC_CHK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CMD_CRC_CHK_EN_POS)) /**< CMD_CRC_CHK_EN Mask */ 265 266 #define MXC_F_SDHC_CMD_IDX_CHK_EN_POS 4 /**< CMD_IDX_CHK_EN Position */ 267 #define MXC_F_SDHC_CMD_IDX_CHK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CMD_IDX_CHK_EN_POS)) /**< CMD_IDX_CHK_EN Mask */ 268 269 #define MXC_F_SDHC_CMD_DATA_PRES_SEL_POS 5 /**< CMD_DATA_PRES_SEL Position */ 270 #define MXC_F_SDHC_CMD_DATA_PRES_SEL ((uint16_t)(0x1UL << MXC_F_SDHC_CMD_DATA_PRES_SEL_POS)) /**< CMD_DATA_PRES_SEL Mask */ 271 272 #define MXC_F_SDHC_CMD_TYPE_POS 6 /**< CMD_TYPE Position */ 273 #define MXC_F_SDHC_CMD_TYPE ((uint16_t)(0x3UL << MXC_F_SDHC_CMD_TYPE_POS)) /**< CMD_TYPE Mask */ 274 275 #define MXC_F_SDHC_CMD_IDX_POS 8 /**< CMD_IDX Position */ 276 #define MXC_F_SDHC_CMD_IDX ((uint16_t)(0x3FUL << MXC_F_SDHC_CMD_IDX_POS)) /**< CMD_IDX Mask */ 277 278 /**@} end of group SDHC_CMD_Register */ 279 280 /** 281 * @ingroup sdhc_registers 282 * @defgroup SDHC_RESP SDHC_RESP 283 * @brief Response 0 Register 0-15. 284 * @{ 285 */ 286 #define MXC_F_SDHC_RESP_CMD_RESP_POS 0 /**< RESP_CMD_RESP Position */ 287 #define MXC_F_SDHC_RESP_CMD_RESP ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_RESP_CMD_RESP_POS)) /**< RESP_CMD_RESP Mask */ 288 289 /**@} end of group SDHC_RESP_Register */ 290 291 /** 292 * @ingroup sdhc_registers 293 * @defgroup SDHC_BUFFER SDHC_BUFFER 294 * @brief Buffer Data Port. 295 * @{ 296 */ 297 #define MXC_F_SDHC_BUFFER_DATA_POS 0 /**< BUFFER_DATA Position */ 298 #define MXC_F_SDHC_BUFFER_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_BUFFER_DATA_POS)) /**< BUFFER_DATA Mask */ 299 300 /**@} end of group SDHC_BUFFER_Register */ 301 302 /** 303 * @ingroup sdhc_registers 304 * @defgroup SDHC_PRESENT SDHC_PRESENT 305 * @brief Present State. 306 * @{ 307 */ 308 #define MXC_F_SDHC_PRESENT_CMD_POS 0 /**< PRESENT_CMD Position */ 309 #define MXC_F_SDHC_PRESENT_CMD ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CMD_POS)) /**< PRESENT_CMD Mask */ 310 311 #define MXC_F_SDHC_PRESENT_DAT_POS 1 /**< PRESENT_DAT Position */ 312 #define MXC_F_SDHC_PRESENT_DAT ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_DAT_POS)) /**< PRESENT_DAT Mask */ 313 314 #define MXC_F_SDHC_PRESENT_DAT_LINE_ACTIVE_POS 2 /**< PRESENT_DAT_LINE_ACTIVE Position */ 315 #define MXC_F_SDHC_PRESENT_DAT_LINE_ACTIVE ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_DAT_LINE_ACTIVE_POS)) /**< PRESENT_DAT_LINE_ACTIVE Mask */ 316 317 #define MXC_F_SDHC_PRESENT_RETUNING_POS 3 /**< PRESENT_RETUNING Position */ 318 #define MXC_F_SDHC_PRESENT_RETUNING ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_RETUNING_POS)) /**< PRESENT_RETUNING Mask */ 319 320 #define MXC_F_SDHC_PRESENT_WRITE_TRANSFER_POS 8 /**< PRESENT_WRITE_TRANSFER Position */ 321 #define MXC_F_SDHC_PRESENT_WRITE_TRANSFER ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_WRITE_TRANSFER_POS)) /**< PRESENT_WRITE_TRANSFER Mask */ 322 323 #define MXC_F_SDHC_PRESENT_READ_TRANSFER_POS 9 /**< PRESENT_READ_TRANSFER Position */ 324 #define MXC_F_SDHC_PRESENT_READ_TRANSFER ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_READ_TRANSFER_POS)) /**< PRESENT_READ_TRANSFER Mask */ 325 326 #define MXC_F_SDHC_PRESENT_BUFFER_WRITE_POS 10 /**< PRESENT_BUFFER_WRITE Position */ 327 #define MXC_F_SDHC_PRESENT_BUFFER_WRITE ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_BUFFER_WRITE_POS)) /**< PRESENT_BUFFER_WRITE Mask */ 328 329 #define MXC_F_SDHC_PRESENT_BUFFER_READ_POS 11 /**< PRESENT_BUFFER_READ Position */ 330 #define MXC_F_SDHC_PRESENT_BUFFER_READ ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_BUFFER_READ_POS)) /**< PRESENT_BUFFER_READ Mask */ 331 332 #define MXC_F_SDHC_PRESENT_CARD_INSERTED_POS 16 /**< PRESENT_CARD_INSERTED Position */ 333 #define MXC_F_SDHC_PRESENT_CARD_INSERTED ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CARD_INSERTED_POS)) /**< PRESENT_CARD_INSERTED Mask */ 334 335 #define MXC_F_SDHC_PRESENT_CARD_STATE_POS 17 /**< PRESENT_CARD_STATE Position */ 336 #define MXC_F_SDHC_PRESENT_CARD_STATE ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CARD_STATE_POS)) /**< PRESENT_CARD_STATE Mask */ 337 338 #define MXC_F_SDHC_PRESENT_CARD_DETECT_POS 18 /**< PRESENT_CARD_DETECT Position */ 339 #define MXC_F_SDHC_PRESENT_CARD_DETECT ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CARD_DETECT_POS)) /**< PRESENT_CARD_DETECT Mask */ 340 341 #define MXC_F_SDHC_PRESENT_WP_POS 19 /**< PRESENT_WP Position */ 342 #define MXC_F_SDHC_PRESENT_WP ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_WP_POS)) /**< PRESENT_WP Mask */ 343 344 #define MXC_F_SDHC_PRESENT_DAT_SIGNAL_LEVEL_POS 20 /**< PRESENT_DAT_SIGNAL_LEVEL Position */ 345 #define MXC_F_SDHC_PRESENT_DAT_SIGNAL_LEVEL ((uint32_t)(0xFUL << MXC_F_SDHC_PRESENT_DAT_SIGNAL_LEVEL_POS)) /**< PRESENT_DAT_SIGNAL_LEVEL Mask */ 346 347 #define MXC_F_SDHC_PRESENT_CMD_SIGNAL_LEVEL_POS 24 /**< PRESENT_CMD_SIGNAL_LEVEL Position */ 348 #define MXC_F_SDHC_PRESENT_CMD_SIGNAL_LEVEL ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CMD_SIGNAL_LEVEL_POS)) /**< PRESENT_CMD_SIGNAL_LEVEL Mask */ 349 350 /**@} end of group SDHC_PRESENT_Register */ 351 352 /** 353 * @ingroup sdhc_registers 354 * @defgroup SDHC_HOST_CN_1 SDHC_HOST_CN_1 355 * @brief Host Control 1. 356 * @{ 357 */ 358 #define MXC_F_SDHC_HOST_CN_1_LED_CN_POS 0 /**< HOST_CN_1_LED_CN Position */ 359 #define MXC_F_SDHC_HOST_CN_1_LED_CN ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_LED_CN_POS)) /**< HOST_CN_1_LED_CN Mask */ 360 361 #define MXC_F_SDHC_HOST_CN_1_DATA_TRANSFER_WIDTH_POS 1 /**< HOST_CN_1_DATA_TRANSFER_WIDTH Position */ 362 #define MXC_F_SDHC_HOST_CN_1_DATA_TRANSFER_WIDTH ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_DATA_TRANSFER_WIDTH_POS)) /**< HOST_CN_1_DATA_TRANSFER_WIDTH Mask */ 363 364 #define MXC_F_SDHC_HOST_CN_1_HS_EN_POS 2 /**< HOST_CN_1_HS_EN Position */ 365 #define MXC_F_SDHC_HOST_CN_1_HS_EN ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_HS_EN_POS)) /**< HOST_CN_1_HS_EN Mask */ 366 367 #define MXC_F_SDHC_HOST_CN_1_DMA_SELECT_POS 3 /**< HOST_CN_1_DMA_SELECT Position */ 368 #define MXC_F_SDHC_HOST_CN_1_DMA_SELECT ((uint8_t)(0x3UL << MXC_F_SDHC_HOST_CN_1_DMA_SELECT_POS)) /**< HOST_CN_1_DMA_SELECT Mask */ 369 370 #define MXC_F_SDHC_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH_POS 5 /**< HOST_CN_1_EXT_DATA_TRANSFER_WIDTH Position */ 371 #define MXC_F_SDHC_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH_POS)) /**< HOST_CN_1_EXT_DATA_TRANSFER_WIDTH Mask */ 372 373 #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_TEST_POS 6 /**< HOST_CN_1_CARD_DETECT_TEST Position */ 374 #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_TEST ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_CARD_DETECT_TEST_POS)) /**< HOST_CN_1_CARD_DETECT_TEST Mask */ 375 376 #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_SIGNAL_POS 7 /**< HOST_CN_1_CARD_DETECT_SIGNAL Position */ 377 #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_SIGNAL ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_CARD_DETECT_SIGNAL_POS)) /**< HOST_CN_1_CARD_DETECT_SIGNAL Mask */ 378 379 /**@} end of group SDHC_HOST_CN_1_Register */ 380 381 /** 382 * @ingroup sdhc_registers 383 * @defgroup SDHC_PWR SDHC_PWR 384 * @brief Power Control. 385 * @{ 386 */ 387 #define MXC_F_SDHC_PWR_BUS_POWER_POS 0 /**< PWR_BUS_POWER Position */ 388 #define MXC_F_SDHC_PWR_BUS_POWER ((uint8_t)(0x1UL << MXC_F_SDHC_PWR_BUS_POWER_POS)) /**< PWR_BUS_POWER Mask */ 389 390 #define MXC_F_SDHC_PWR_BUS_VOLT_SEL_POS 1 /**< PWR_BUS_VOLT_SEL Position */ 391 #define MXC_F_SDHC_PWR_BUS_VOLT_SEL ((uint8_t)(0x7UL << MXC_F_SDHC_PWR_BUS_VOLT_SEL_POS)) /**< PWR_BUS_VOLT_SEL Mask */ 392 393 /**@} end of group SDHC_PWR_Register */ 394 395 /** 396 * @ingroup sdhc_registers 397 * @defgroup SDHC_BLK_GAP SDHC_BLK_GAP 398 * @brief Block Gap Control. 399 * @{ 400 */ 401 #define MXC_F_SDHC_BLK_GAP_STOP_POS 0 /**< BLK_GAP_STOP Position */ 402 #define MXC_F_SDHC_BLK_GAP_STOP ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_STOP_POS)) /**< BLK_GAP_STOP Mask */ 403 404 #define MXC_F_SDHC_BLK_GAP_CONT_POS 1 /**< BLK_GAP_CONT Position */ 405 #define MXC_F_SDHC_BLK_GAP_CONT ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_CONT_POS)) /**< BLK_GAP_CONT Mask */ 406 407 #define MXC_F_SDHC_BLK_GAP_READ_WAIT_POS 2 /**< BLK_GAP_READ_WAIT Position */ 408 #define MXC_F_SDHC_BLK_GAP_READ_WAIT ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_READ_WAIT_POS)) /**< BLK_GAP_READ_WAIT Mask */ 409 410 #define MXC_F_SDHC_BLK_GAP_INTR_POS 3 /**< BLK_GAP_INTR Position */ 411 #define MXC_F_SDHC_BLK_GAP_INTR ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_INTR_POS)) /**< BLK_GAP_INTR Mask */ 412 413 /**@} end of group SDHC_BLK_GAP_Register */ 414 415 /** 416 * @ingroup sdhc_registers 417 * @defgroup SDHC_WAKEUP SDHC_WAKEUP 418 * @brief Wakeup Control. 419 * @{ 420 */ 421 #define MXC_F_SDHC_WAKEUP_CARD_INT_POS 0 /**< WAKEUP_CARD_INT Position */ 422 #define MXC_F_SDHC_WAKEUP_CARD_INT ((uint8_t)(0x1UL << MXC_F_SDHC_WAKEUP_CARD_INT_POS)) /**< WAKEUP_CARD_INT Mask */ 423 424 #define MXC_F_SDHC_WAKEUP_CARD_INS_POS 1 /**< WAKEUP_CARD_INS Position */ 425 #define MXC_F_SDHC_WAKEUP_CARD_INS ((uint8_t)(0x1UL << MXC_F_SDHC_WAKEUP_CARD_INS_POS)) /**< WAKEUP_CARD_INS Mask */ 426 427 #define MXC_F_SDHC_WAKEUP_CARD_REM_POS 2 /**< WAKEUP_CARD_REM Position */ 428 #define MXC_F_SDHC_WAKEUP_CARD_REM ((uint8_t)(0x1UL << MXC_F_SDHC_WAKEUP_CARD_REM_POS)) /**< WAKEUP_CARD_REM Mask */ 429 430 /**@} end of group SDHC_WAKEUP_Register */ 431 432 /** 433 * @ingroup sdhc_registers 434 * @defgroup SDHC_CLK_CN SDHC_CLK_CN 435 * @brief Clock Control. 436 * @{ 437 */ 438 #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_EN_POS 0 /**< CLK_CN_INTERNAL_CLK_EN Position */ 439 #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_INTERNAL_CLK_EN_POS)) /**< CLK_CN_INTERNAL_CLK_EN Mask */ 440 441 #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_STABLE_POS 1 /**< CLK_CN_INTERNAL_CLK_STABLE Position */ 442 #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_STABLE ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_INTERNAL_CLK_STABLE_POS)) /**< CLK_CN_INTERNAL_CLK_STABLE Mask */ 443 444 #define MXC_F_SDHC_CLK_CN_SD_CLK_EN_POS 2 /**< CLK_CN_SD_CLK_EN Position */ 445 #define MXC_F_SDHC_CLK_CN_SD_CLK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_SD_CLK_EN_POS)) /**< CLK_CN_SD_CLK_EN Mask */ 446 447 #define MXC_F_SDHC_CLK_CN_CLK_GEN_SEL_POS 5 /**< CLK_CN_CLK_GEN_SEL Position */ 448 #define MXC_F_SDHC_CLK_CN_CLK_GEN_SEL ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_CLK_GEN_SEL_POS)) /**< CLK_CN_CLK_GEN_SEL Mask */ 449 450 #define MXC_F_SDHC_CLK_CN_UPPER_SDCLK_FREQ_SEL_POS 6 /**< CLK_CN_UPPER_SDCLK_FREQ_SEL Position */ 451 #define MXC_F_SDHC_CLK_CN_UPPER_SDCLK_FREQ_SEL ((uint16_t)(0x3UL << MXC_F_SDHC_CLK_CN_UPPER_SDCLK_FREQ_SEL_POS)) /**< CLK_CN_UPPER_SDCLK_FREQ_SEL Mask */ 452 453 #define MXC_F_SDHC_CLK_CN_SDCLK_FREQ_SEL_POS 8 /**< CLK_CN_SDCLK_FREQ_SEL Position */ 454 #define MXC_F_SDHC_CLK_CN_SDCLK_FREQ_SEL ((uint16_t)(0xFFUL << MXC_F_SDHC_CLK_CN_SDCLK_FREQ_SEL_POS)) /**< CLK_CN_SDCLK_FREQ_SEL Mask */ 455 456 /**@} end of group SDHC_CLK_CN_Register */ 457 458 /** 459 * @ingroup sdhc_registers 460 * @defgroup SDHC_TO SDHC_TO 461 * @brief Timeout Control. 462 * @{ 463 */ 464 #define MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS 0 /**< TO_DATA_COUNT_VALUE Position */ 465 #define MXC_F_SDHC_TO_DATA_COUNT_VALUE ((uint8_t)(0x7UL << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS)) /**< TO_DATA_COUNT_VALUE Mask */ 466 467 /**@} end of group SDHC_TO_Register */ 468 469 /** 470 * @ingroup sdhc_registers 471 * @defgroup SDHC_SW_RESET SDHC_SW_RESET 472 * @brief Software Reset. 473 * @{ 474 */ 475 #define MXC_F_SDHC_SW_RESET_RESET_ALL_POS 0 /**< SW_RESET_RESET_ALL Position */ 476 #define MXC_F_SDHC_SW_RESET_RESET_ALL ((uint8_t)(0x1UL << MXC_F_SDHC_SW_RESET_RESET_ALL_POS)) /**< SW_RESET_RESET_ALL Mask */ 477 478 #define MXC_F_SDHC_SW_RESET_RESET_CMD_POS 1 /**< SW_RESET_RESET_CMD Position */ 479 #define MXC_F_SDHC_SW_RESET_RESET_CMD ((uint8_t)(0x1UL << MXC_F_SDHC_SW_RESET_RESET_CMD_POS)) /**< SW_RESET_RESET_CMD Mask */ 480 481 #define MXC_F_SDHC_SW_RESET_RESET_DAT_POS 2 /**< SW_RESET_RESET_DAT Position */ 482 #define MXC_F_SDHC_SW_RESET_RESET_DAT ((uint8_t)(0x1UL << MXC_F_SDHC_SW_RESET_RESET_DAT_POS)) /**< SW_RESET_RESET_DAT Mask */ 483 484 /**@} end of group SDHC_SW_RESET_Register */ 485 486 /** 487 * @ingroup sdhc_registers 488 * @defgroup SDHC_INT_STAT SDHC_INT_STAT 489 * @brief Normal Interrupt Status. 490 * @{ 491 */ 492 #define MXC_F_SDHC_INT_STAT_CMD_COMP_POS 0 /**< INT_STAT_CMD_COMP Position */ 493 #define MXC_F_SDHC_INT_STAT_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CMD_COMP_POS)) /**< INT_STAT_CMD_COMP Mask */ 494 495 #define MXC_F_SDHC_INT_STAT_TRANS_COMP_POS 1 /**< INT_STAT_TRANS_COMP Position */ 496 #define MXC_F_SDHC_INT_STAT_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_TRANS_COMP_POS)) /**< INT_STAT_TRANS_COMP Mask */ 497 498 #define MXC_F_SDHC_INT_STAT_BLK_GAP_EVENT_POS 2 /**< INT_STAT_BLK_GAP_EVENT Position */ 499 #define MXC_F_SDHC_INT_STAT_BLK_GAP_EVENT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_BLK_GAP_EVENT_POS)) /**< INT_STAT_BLK_GAP_EVENT Mask */ 500 501 #define MXC_F_SDHC_INT_STAT_DMA_POS 3 /**< INT_STAT_DMA Position */ 502 #define MXC_F_SDHC_INT_STAT_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_DMA_POS)) /**< INT_STAT_DMA Mask */ 503 504 #define MXC_F_SDHC_INT_STAT_BUFF_WR_READY_POS 4 /**< INT_STAT_BUFF_WR_READY Position */ 505 #define MXC_F_SDHC_INT_STAT_BUFF_WR_READY ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_BUFF_WR_READY_POS)) /**< INT_STAT_BUFF_WR_READY Mask */ 506 507 #define MXC_F_SDHC_INT_STAT_BUFF_RD_READY_POS 5 /**< INT_STAT_BUFF_RD_READY Position */ 508 #define MXC_F_SDHC_INT_STAT_BUFF_RD_READY ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_BUFF_RD_READY_POS)) /**< INT_STAT_BUFF_RD_READY Mask */ 509 510 #define MXC_F_SDHC_INT_STAT_CARD_INSERTION_POS 6 /**< INT_STAT_CARD_INSERTION Position */ 511 #define MXC_F_SDHC_INT_STAT_CARD_INSERTION ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CARD_INSERTION_POS)) /**< INT_STAT_CARD_INSERTION Mask */ 512 513 #define MXC_F_SDHC_INT_STAT_CARD_REMOVAL_POS 7 /**< INT_STAT_CARD_REMOVAL Position */ 514 #define MXC_F_SDHC_INT_STAT_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CARD_REMOVAL_POS)) /**< INT_STAT_CARD_REMOVAL Mask */ 515 516 #define MXC_F_SDHC_INT_STAT_CARD_INTR_POS 8 /**< INT_STAT_CARD_INTR Position */ 517 #define MXC_F_SDHC_INT_STAT_CARD_INTR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CARD_INTR_POS)) /**< INT_STAT_CARD_INTR Mask */ 518 519 #define MXC_F_SDHC_INT_STAT_RETUNING_POS 12 /**< INT_STAT_RETUNING Position */ 520 #define MXC_F_SDHC_INT_STAT_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_RETUNING_POS)) /**< INT_STAT_RETUNING Mask */ 521 522 #define MXC_F_SDHC_INT_STAT_ERR_INTR_POS 15 /**< INT_STAT_ERR_INTR Position */ 523 #define MXC_F_SDHC_INT_STAT_ERR_INTR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_ERR_INTR_POS)) /**< INT_STAT_ERR_INTR Mask */ 524 525 /**@} end of group SDHC_INT_STAT_Register */ 526 527 /** 528 * @ingroup sdhc_registers 529 * @defgroup SDHC_ER_INT_STAT SDHC_ER_INT_STAT 530 * @brief Error Interrupt Status. 531 * @{ 532 */ 533 #define MXC_F_SDHC_ER_INT_STAT_CMD_TO_POS 0 /**< ER_INT_STAT_CMD_TO Position */ 534 #define MXC_F_SDHC_ER_INT_STAT_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_TO_POS)) /**< ER_INT_STAT_CMD_TO Mask */ 535 536 #define MXC_F_SDHC_ER_INT_STAT_CMD_CRC_POS 1 /**< ER_INT_STAT_CMD_CRC Position */ 537 #define MXC_F_SDHC_ER_INT_STAT_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_CRC_POS)) /**< ER_INT_STAT_CMD_CRC Mask */ 538 539 #define MXC_F_SDHC_ER_INT_STAT_CMD_END_BIT_POS 2 /**< ER_INT_STAT_CMD_END_BIT Position */ 540 #define MXC_F_SDHC_ER_INT_STAT_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_END_BIT_POS)) /**< ER_INT_STAT_CMD_END_BIT Mask */ 541 542 #define MXC_F_SDHC_ER_INT_STAT_CMD_IDX_POS 3 /**< ER_INT_STAT_CMD_IDX Position */ 543 #define MXC_F_SDHC_ER_INT_STAT_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_IDX_POS)) /**< ER_INT_STAT_CMD_IDX Mask */ 544 545 #define MXC_F_SDHC_ER_INT_STAT_DATA_TO_POS 4 /**< ER_INT_STAT_DATA_TO Position */ 546 #define MXC_F_SDHC_ER_INT_STAT_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DATA_TO_POS)) /**< ER_INT_STAT_DATA_TO Mask */ 547 548 #define MXC_F_SDHC_ER_INT_STAT_DATA_CRC_POS 5 /**< ER_INT_STAT_DATA_CRC Position */ 549 #define MXC_F_SDHC_ER_INT_STAT_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DATA_CRC_POS)) /**< ER_INT_STAT_DATA_CRC Mask */ 550 551 #define MXC_F_SDHC_ER_INT_STAT_DATA_END_BIT_POS 6 /**< ER_INT_STAT_DATA_END_BIT Position */ 552 #define MXC_F_SDHC_ER_INT_STAT_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DATA_END_BIT_POS)) /**< ER_INT_STAT_DATA_END_BIT Mask */ 553 554 #define MXC_F_SDHC_ER_INT_STAT_CURRENT_LIMIT_POS 7 /**< ER_INT_STAT_CURRENT_LIMIT Position */ 555 #define MXC_F_SDHC_ER_INT_STAT_CURRENT_LIMIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CURRENT_LIMIT_POS)) /**< ER_INT_STAT_CURRENT_LIMIT Mask */ 556 557 #define MXC_F_SDHC_ER_INT_STAT_AUTO_CMD_12_POS 8 /**< ER_INT_STAT_AUTO_CMD_12 Position */ 558 #define MXC_F_SDHC_ER_INT_STAT_AUTO_CMD_12 ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_AUTO_CMD_12_POS)) /**< ER_INT_STAT_AUTO_CMD_12 Mask */ 559 560 #define MXC_F_SDHC_ER_INT_STAT_ADMA_POS 9 /**< ER_INT_STAT_ADMA Position */ 561 #define MXC_F_SDHC_ER_INT_STAT_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_ADMA_POS)) /**< ER_INT_STAT_ADMA Mask */ 562 563 #define MXC_F_SDHC_ER_INT_STAT_DMA_POS 12 /**< ER_INT_STAT_DMA Position */ 564 #define MXC_F_SDHC_ER_INT_STAT_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DMA_POS)) /**< ER_INT_STAT_DMA Mask */ 565 566 /**@} end of group SDHC_ER_INT_STAT_Register */ 567 568 /** 569 * @ingroup sdhc_registers 570 * @defgroup SDHC_INT_EN SDHC_INT_EN 571 * @brief Normal Interrupt Status Enable. 572 * @{ 573 */ 574 #define MXC_F_SDHC_INT_EN_CMD_COMP_POS 0 /**< INT_EN_CMD_COMP Position */ 575 #define MXC_F_SDHC_INT_EN_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CMD_COMP_POS)) /**< INT_EN_CMD_COMP Mask */ 576 577 #define MXC_F_SDHC_INT_EN_TRANS_COMP_POS 1 /**< INT_EN_TRANS_COMP Position */ 578 #define MXC_F_SDHC_INT_EN_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_TRANS_COMP_POS)) /**< INT_EN_TRANS_COMP Mask */ 579 580 #define MXC_F_SDHC_INT_EN_BLK_GAP_POS 2 /**< INT_EN_BLK_GAP Position */ 581 #define MXC_F_SDHC_INT_EN_BLK_GAP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_BLK_GAP_POS)) /**< INT_EN_BLK_GAP Mask */ 582 583 #define MXC_F_SDHC_INT_EN_DMA_POS 3 /**< INT_EN_DMA Position */ 584 #define MXC_F_SDHC_INT_EN_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_DMA_POS)) /**< INT_EN_DMA Mask */ 585 586 #define MXC_F_SDHC_INT_EN_BUFFER_WR_POS 4 /**< INT_EN_BUFFER_WR Position */ 587 #define MXC_F_SDHC_INT_EN_BUFFER_WR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_BUFFER_WR_POS)) /**< INT_EN_BUFFER_WR Mask */ 588 589 #define MXC_F_SDHC_INT_EN_BUFFER_RD_POS 5 /**< INT_EN_BUFFER_RD Position */ 590 #define MXC_F_SDHC_INT_EN_BUFFER_RD ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_BUFFER_RD_POS)) /**< INT_EN_BUFFER_RD Mask */ 591 592 #define MXC_F_SDHC_INT_EN_CARD_INSERT_POS 6 /**< INT_EN_CARD_INSERT Position */ 593 #define MXC_F_SDHC_INT_EN_CARD_INSERT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CARD_INSERT_POS)) /**< INT_EN_CARD_INSERT Mask */ 594 595 #define MXC_F_SDHC_INT_EN_CARD_REMOVAL_POS 7 /**< INT_EN_CARD_REMOVAL Position */ 596 #define MXC_F_SDHC_INT_EN_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CARD_REMOVAL_POS)) /**< INT_EN_CARD_REMOVAL Mask */ 597 598 #define MXC_F_SDHC_INT_EN_CARD_INT_POS 8 /**< INT_EN_CARD_INT Position */ 599 #define MXC_F_SDHC_INT_EN_CARD_INT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CARD_INT_POS)) /**< INT_EN_CARD_INT Mask */ 600 601 #define MXC_F_SDHC_INT_EN_RETUNING_POS 12 /**< INT_EN_RETUNING Position */ 602 #define MXC_F_SDHC_INT_EN_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_RETUNING_POS)) /**< INT_EN_RETUNING Mask */ 603 604 /**@} end of group SDHC_INT_EN_Register */ 605 606 /** 607 * @ingroup sdhc_registers 608 * @defgroup SDHC_ER_INT_EN SDHC_ER_INT_EN 609 * @brief Error Interrupt Status Enable. 610 * @{ 611 */ 612 #define MXC_F_SDHC_ER_INT_EN_CMD_TO_POS 0 /**< ER_INT_EN_CMD_TO Position */ 613 #define MXC_F_SDHC_ER_INT_EN_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_TO_POS)) /**< ER_INT_EN_CMD_TO Mask */ 614 615 #define MXC_F_SDHC_ER_INT_EN_CMD_CRC_POS 1 /**< ER_INT_EN_CMD_CRC Position */ 616 #define MXC_F_SDHC_ER_INT_EN_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_CRC_POS)) /**< ER_INT_EN_CMD_CRC Mask */ 617 618 #define MXC_F_SDHC_ER_INT_EN_CMD_END_BIT_POS 2 /**< ER_INT_EN_CMD_END_BIT Position */ 619 #define MXC_F_SDHC_ER_INT_EN_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_END_BIT_POS)) /**< ER_INT_EN_CMD_END_BIT Mask */ 620 621 #define MXC_F_SDHC_ER_INT_EN_CMD_IDX_POS 3 /**< ER_INT_EN_CMD_IDX Position */ 622 #define MXC_F_SDHC_ER_INT_EN_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_IDX_POS)) /**< ER_INT_EN_CMD_IDX Mask */ 623 624 #define MXC_F_SDHC_ER_INT_EN_DATA_TO_POS 4 /**< ER_INT_EN_DATA_TO Position */ 625 #define MXC_F_SDHC_ER_INT_EN_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_DATA_TO_POS)) /**< ER_INT_EN_DATA_TO Mask */ 626 627 #define MXC_F_SDHC_ER_INT_EN_DATA_CRC_POS 5 /**< ER_INT_EN_DATA_CRC Position */ 628 #define MXC_F_SDHC_ER_INT_EN_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_DATA_CRC_POS)) /**< ER_INT_EN_DATA_CRC Mask */ 629 630 #define MXC_F_SDHC_ER_INT_EN_DATA_END_BIT_POS 6 /**< ER_INT_EN_DATA_END_BIT Position */ 631 #define MXC_F_SDHC_ER_INT_EN_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_DATA_END_BIT_POS)) /**< ER_INT_EN_DATA_END_BIT Mask */ 632 633 #define MXC_F_SDHC_ER_INT_EN_AUTO_CMD_POS 8 /**< ER_INT_EN_AUTO_CMD Position */ 634 #define MXC_F_SDHC_ER_INT_EN_AUTO_CMD ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_AUTO_CMD_POS)) /**< ER_INT_EN_AUTO_CMD Mask */ 635 636 #define MXC_F_SDHC_ER_INT_EN_ADMA_POS 9 /**< ER_INT_EN_ADMA Position */ 637 #define MXC_F_SDHC_ER_INT_EN_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_ADMA_POS)) /**< ER_INT_EN_ADMA Mask */ 638 639 #define MXC_F_SDHC_ER_INT_EN_TUNING_POS 10 /**< ER_INT_EN_TUNING Position */ 640 #define MXC_F_SDHC_ER_INT_EN_TUNING ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_TUNING_POS)) /**< ER_INT_EN_TUNING Mask */ 641 642 #define MXC_F_SDHC_ER_INT_EN_VENDOR_POS 12 /**< ER_INT_EN_VENDOR Position */ 643 #define MXC_F_SDHC_ER_INT_EN_VENDOR ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_VENDOR_POS)) /**< ER_INT_EN_VENDOR Mask */ 644 645 /**@} end of group SDHC_ER_INT_EN_Register */ 646 647 /** 648 * @ingroup sdhc_registers 649 * @defgroup SDHC_INT_SIGNAL SDHC_INT_SIGNAL 650 * @brief Normal Interrupt Signal Enable. 651 * @{ 652 */ 653 #define MXC_F_SDHC_INT_SIGNAL_CMD_COMP_POS 0 /**< INT_SIGNAL_CMD_COMP Position */ 654 #define MXC_F_SDHC_INT_SIGNAL_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CMD_COMP_POS)) /**< INT_SIGNAL_CMD_COMP Mask */ 655 656 #define MXC_F_SDHC_INT_SIGNAL_TRANS_COMP_POS 1 /**< INT_SIGNAL_TRANS_COMP Position */ 657 #define MXC_F_SDHC_INT_SIGNAL_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_TRANS_COMP_POS)) /**< INT_SIGNAL_TRANS_COMP Mask */ 658 659 #define MXC_F_SDHC_INT_SIGNAL_BLK_GAP_POS 2 /**< INT_SIGNAL_BLK_GAP Position */ 660 #define MXC_F_SDHC_INT_SIGNAL_BLK_GAP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_BLK_GAP_POS)) /**< INT_SIGNAL_BLK_GAP Mask */ 661 662 #define MXC_F_SDHC_INT_SIGNAL_DMA_POS 3 /**< INT_SIGNAL_DMA Position */ 663 #define MXC_F_SDHC_INT_SIGNAL_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_DMA_POS)) /**< INT_SIGNAL_DMA Mask */ 664 665 #define MXC_F_SDHC_INT_SIGNAL_BUFFER_WR_POS 4 /**< INT_SIGNAL_BUFFER_WR Position */ 666 #define MXC_F_SDHC_INT_SIGNAL_BUFFER_WR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_BUFFER_WR_POS)) /**< INT_SIGNAL_BUFFER_WR Mask */ 667 668 #define MXC_F_SDHC_INT_SIGNAL_BUFFER_RD_POS 5 /**< INT_SIGNAL_BUFFER_RD Position */ 669 #define MXC_F_SDHC_INT_SIGNAL_BUFFER_RD ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_BUFFER_RD_POS)) /**< INT_SIGNAL_BUFFER_RD Mask */ 670 671 #define MXC_F_SDHC_INT_SIGNAL_CARD_INSERT_POS 6 /**< INT_SIGNAL_CARD_INSERT Position */ 672 #define MXC_F_SDHC_INT_SIGNAL_CARD_INSERT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CARD_INSERT_POS)) /**< INT_SIGNAL_CARD_INSERT Mask */ 673 674 #define MXC_F_SDHC_INT_SIGNAL_CARD_REMOVAL_POS 7 /**< INT_SIGNAL_CARD_REMOVAL Position */ 675 #define MXC_F_SDHC_INT_SIGNAL_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CARD_REMOVAL_POS)) /**< INT_SIGNAL_CARD_REMOVAL Mask */ 676 677 #define MXC_F_SDHC_INT_SIGNAL_CARD_INT_POS 8 /**< INT_SIGNAL_CARD_INT Position */ 678 #define MXC_F_SDHC_INT_SIGNAL_CARD_INT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CARD_INT_POS)) /**< INT_SIGNAL_CARD_INT Mask */ 679 680 #define MXC_F_SDHC_INT_SIGNAL_RETUNING_POS 12 /**< INT_SIGNAL_RETUNING Position */ 681 #define MXC_F_SDHC_INT_SIGNAL_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_RETUNING_POS)) /**< INT_SIGNAL_RETUNING Mask */ 682 683 /**@} end of group SDHC_INT_SIGNAL_Register */ 684 685 /** 686 * @ingroup sdhc_registers 687 * @defgroup SDHC_ER_INT_SIGNAL SDHC_ER_INT_SIGNAL 688 * @brief Error Interrupt Signal Enable. 689 * @{ 690 */ 691 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_TO_POS 0 /**< ER_INT_SIGNAL_CMD_TO Position */ 692 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_TO_POS)) /**< ER_INT_SIGNAL_CMD_TO Mask */ 693 694 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_CRC_POS 1 /**< ER_INT_SIGNAL_CMD_CRC Position */ 695 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_CRC_POS)) /**< ER_INT_SIGNAL_CMD_CRC Mask */ 696 697 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_END_BIT_POS 2 /**< ER_INT_SIGNAL_CMD_END_BIT Position */ 698 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_END_BIT_POS)) /**< ER_INT_SIGNAL_CMD_END_BIT Mask */ 699 700 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_IDX_POS 3 /**< ER_INT_SIGNAL_CMD_IDX Position */ 701 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_IDX_POS)) /**< ER_INT_SIGNAL_CMD_IDX Mask */ 702 703 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_TO_POS 4 /**< ER_INT_SIGNAL_DATA_TO Position */ 704 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_DATA_TO_POS)) /**< ER_INT_SIGNAL_DATA_TO Mask */ 705 706 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_CRC_POS 5 /**< ER_INT_SIGNAL_DATA_CRC Position */ 707 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_DATA_CRC_POS)) /**< ER_INT_SIGNAL_DATA_CRC Mask */ 708 709 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_END_BIT_POS 6 /**< ER_INT_SIGNAL_DATA_END_BIT Position */ 710 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_DATA_END_BIT_POS)) /**< ER_INT_SIGNAL_DATA_END_BIT Mask */ 711 712 #define MXC_F_SDHC_ER_INT_SIGNAL_CURR_LIM_POS 7 /**< ER_INT_SIGNAL_CURR_LIM Position */ 713 #define MXC_F_SDHC_ER_INT_SIGNAL_CURR_LIM ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CURR_LIM_POS)) /**< ER_INT_SIGNAL_CURR_LIM Mask */ 714 715 #define MXC_F_SDHC_ER_INT_SIGNAL_AUTO_CMD_POS 8 /**< ER_INT_SIGNAL_AUTO_CMD Position */ 716 #define MXC_F_SDHC_ER_INT_SIGNAL_AUTO_CMD ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_AUTO_CMD_POS)) /**< ER_INT_SIGNAL_AUTO_CMD Mask */ 717 718 #define MXC_F_SDHC_ER_INT_SIGNAL_ADMA_POS 9 /**< ER_INT_SIGNAL_ADMA Position */ 719 #define MXC_F_SDHC_ER_INT_SIGNAL_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_ADMA_POS)) /**< ER_INT_SIGNAL_ADMA Mask */ 720 721 #define MXC_F_SDHC_ER_INT_SIGNAL_TUNING_POS 10 /**< ER_INT_SIGNAL_TUNING Position */ 722 #define MXC_F_SDHC_ER_INT_SIGNAL_TUNING ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_TUNING_POS)) /**< ER_INT_SIGNAL_TUNING Mask */ 723 724 #define MXC_F_SDHC_ER_INT_SIGNAL_TAR_RESP_POS 12 /**< ER_INT_SIGNAL_TAR_RESP Position */ 725 #define MXC_F_SDHC_ER_INT_SIGNAL_TAR_RESP ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_TAR_RESP_POS)) /**< ER_INT_SIGNAL_TAR_RESP Mask */ 726 727 /**@} end of group SDHC_ER_INT_SIGNAL_Register */ 728 729 /** 730 * @ingroup sdhc_registers 731 * @defgroup SDHC_AUTO_CMD_ER SDHC_AUTO_CMD_ER 732 * @brief Auto CMD Error Status. 733 * @{ 734 */ 735 #define MXC_F_SDHC_AUTO_CMD_ER_NOT_EXCUTED_POS 0 /**< AUTO_CMD_ER_NOT_EXCUTED Position */ 736 #define MXC_F_SDHC_AUTO_CMD_ER_NOT_EXCUTED ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_NOT_EXCUTED_POS)) /**< AUTO_CMD_ER_NOT_EXCUTED Mask */ 737 738 #define MXC_F_SDHC_AUTO_CMD_ER_TO_POS 1 /**< AUTO_CMD_ER_TO Position */ 739 #define MXC_F_SDHC_AUTO_CMD_ER_TO ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_TO_POS)) /**< AUTO_CMD_ER_TO Mask */ 740 741 #define MXC_F_SDHC_AUTO_CMD_ER_CRC_POS 2 /**< AUTO_CMD_ER_CRC Position */ 742 #define MXC_F_SDHC_AUTO_CMD_ER_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_CRC_POS)) /**< AUTO_CMD_ER_CRC Mask */ 743 744 #define MXC_F_SDHC_AUTO_CMD_ER_END_BIT_POS 3 /**< AUTO_CMD_ER_END_BIT Position */ 745 #define MXC_F_SDHC_AUTO_CMD_ER_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_END_BIT_POS)) /**< AUTO_CMD_ER_END_BIT Mask */ 746 747 #define MXC_F_SDHC_AUTO_CMD_ER_INDEX_POS 4 /**< AUTO_CMD_ER_INDEX Position */ 748 #define MXC_F_SDHC_AUTO_CMD_ER_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_INDEX_POS)) /**< AUTO_CMD_ER_INDEX Mask */ 749 750 #define MXC_F_SDHC_AUTO_CMD_ER_NOT_ISSUED_POS 7 /**< AUTO_CMD_ER_NOT_ISSUED Position */ 751 #define MXC_F_SDHC_AUTO_CMD_ER_NOT_ISSUED ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_NOT_ISSUED_POS)) /**< AUTO_CMD_ER_NOT_ISSUED Mask */ 752 753 /**@} end of group SDHC_AUTO_CMD_ER_Register */ 754 755 /** 756 * @ingroup sdhc_registers 757 * @defgroup SDHC_HOST_CN_2 SDHC_HOST_CN_2 758 * @brief Host Control 2. 759 * @{ 760 */ 761 #define MXC_F_SDHC_HOST_CN_2_UHS_POS 0 /**< HOST_CN_2_UHS Position */ 762 #define MXC_F_SDHC_HOST_CN_2_UHS ((uint16_t)(0x3UL << MXC_F_SDHC_HOST_CN_2_UHS_POS)) /**< HOST_CN_2_UHS Mask */ 763 764 #define MXC_F_SDHC_HOST_CN_2_SIGNAL_V1_8_POS 3 /**< HOST_CN_2_SIGNAL_V1_8 Position */ 765 #define MXC_F_SDHC_HOST_CN_2_SIGNAL_V1_8 ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_SIGNAL_V1_8_POS)) /**< HOST_CN_2_SIGNAL_V1_8 Mask */ 766 767 #define MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH_POS 4 /**< HOST_CN_2_DRIVER_STRENGTH Position */ 768 #define MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH_POS)) /**< HOST_CN_2_DRIVER_STRENGTH Mask */ 769 770 #define MXC_F_SDHC_HOST_CN_2_EXCUTE_POS 6 /**< HOST_CN_2_EXCUTE Position */ 771 #define MXC_F_SDHC_HOST_CN_2_EXCUTE ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_EXCUTE_POS)) /**< HOST_CN_2_EXCUTE Mask */ 772 773 #define MXC_F_SDHC_HOST_CN_2_SAMPLING_CLK_POS 7 /**< HOST_CN_2_SAMPLING_CLK Position */ 774 #define MXC_F_SDHC_HOST_CN_2_SAMPLING_CLK ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_SAMPLING_CLK_POS)) /**< HOST_CN_2_SAMPLING_CLK Mask */ 775 776 #define MXC_F_SDHC_HOST_CN_2_ASYNCH_INT_POS 14 /**< HOST_CN_2_ASYNCH_INT Position */ 777 #define MXC_F_SDHC_HOST_CN_2_ASYNCH_INT ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_ASYNCH_INT_POS)) /**< HOST_CN_2_ASYNCH_INT Mask */ 778 779 #define MXC_F_SDHC_HOST_CN_2_PRESET_VAL_EN_POS 15 /**< HOST_CN_2_PRESET_VAL_EN Position */ 780 #define MXC_F_SDHC_HOST_CN_2_PRESET_VAL_EN ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_PRESET_VAL_EN_POS)) /**< HOST_CN_2_PRESET_VAL_EN Mask */ 781 782 /**@} end of group SDHC_HOST_CN_2_Register */ 783 784 /** 785 * @ingroup sdhc_registers 786 * @defgroup SDHC_CFG_0 SDHC_CFG_0 787 * @brief Capabilities 0-31. 788 * @{ 789 */ 790 #define MXC_F_SDHC_CFG_0_TO_CLK_FREQ_POS 0 /**< CFG_0_TO_CLK_FREQ Position */ 791 #define MXC_F_SDHC_CFG_0_TO_CLK_FREQ ((uint32_t)(0x3FUL << MXC_F_SDHC_CFG_0_TO_CLK_FREQ_POS)) /**< CFG_0_TO_CLK_FREQ Mask */ 792 793 #define MXC_F_SDHC_CFG_0_TO_CLK_UNIT_POS 7 /**< CFG_0_TO_CLK_UNIT Position */ 794 #define MXC_F_SDHC_CFG_0_TO_CLK_UNIT ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_TO_CLK_UNIT_POS)) /**< CFG_0_TO_CLK_UNIT Mask */ 795 796 #define MXC_F_SDHC_CFG_0_CLK_FREQ_POS 8 /**< CFG_0_CLK_FREQ Position */ 797 #define MXC_F_SDHC_CFG_0_CLK_FREQ ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_0_CLK_FREQ_POS)) /**< CFG_0_CLK_FREQ Mask */ 798 799 #define MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS 16 /**< CFG_0_MAX_BLK_LEN Position */ 800 #define MXC_F_SDHC_CFG_0_MAX_BLK_LEN ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS)) /**< CFG_0_MAX_BLK_LEN Mask */ 801 802 #define MXC_F_SDHC_CFG_0_BIT_8_POS 18 /**< CFG_0_BIT_8 Position */ 803 #define MXC_F_SDHC_CFG_0_BIT_8 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_BIT_8_POS)) /**< CFG_0_BIT_8 Mask */ 804 805 #define MXC_F_SDHC_CFG_0_ADMA2_POS 19 /**< CFG_0_ADMA2 Position */ 806 #define MXC_F_SDHC_CFG_0_ADMA2 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ADMA2_POS)) /**< CFG_0_ADMA2 Mask */ 807 808 #define MXC_F_SDHC_CFG_0_HS_POS 21 /**< CFG_0_HS Position */ 809 #define MXC_F_SDHC_CFG_0_HS ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_HS_POS)) /**< CFG_0_HS Mask */ 810 811 #define MXC_F_SDHC_CFG_0_SDMA_POS 22 /**< CFG_0_SDMA Position */ 812 #define MXC_F_SDHC_CFG_0_SDMA ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SDMA_POS)) /**< CFG_0_SDMA Mask */ 813 814 #define MXC_F_SDHC_CFG_0_SUSPEND_POS 23 /**< CFG_0_SUSPEND Position */ 815 #define MXC_F_SDHC_CFG_0_SUSPEND ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SUSPEND_POS)) /**< CFG_0_SUSPEND Mask */ 816 817 #define MXC_F_SDHC_CFG_0_V3_3_POS 24 /**< CFG_0_V3_3 Position */ 818 #define MXC_F_SDHC_CFG_0_V3_3 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_V3_3_POS)) /**< CFG_0_V3_3 Mask */ 819 820 #define MXC_F_SDHC_CFG_0_V3_0_POS 25 /**< CFG_0_V3_0 Position */ 821 #define MXC_F_SDHC_CFG_0_V3_0 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_V3_0_POS)) /**< CFG_0_V3_0 Mask */ 822 823 #define MXC_F_SDHC_CFG_0_V1_8_POS 26 /**< CFG_0_V1_8 Position */ 824 #define MXC_F_SDHC_CFG_0_V1_8 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_V1_8_POS)) /**< CFG_0_V1_8 Mask */ 825 826 #define MXC_F_SDHC_CFG_0_BIT_64_SYS_BUS_POS 28 /**< CFG_0_BIT_64_SYS_BUS Position */ 827 #define MXC_F_SDHC_CFG_0_BIT_64_SYS_BUS ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_BIT_64_SYS_BUS_POS)) /**< CFG_0_BIT_64_SYS_BUS Mask */ 828 829 #define MXC_F_SDHC_CFG_0_ASYNC_INT_POS 29 /**< CFG_0_ASYNC_INT Position */ 830 #define MXC_F_SDHC_CFG_0_ASYNC_INT ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ASYNC_INT_POS)) /**< CFG_0_ASYNC_INT Mask */ 831 832 #define MXC_F_SDHC_CFG_0_SLOT_TYPE_POS 30 /**< CFG_0_SLOT_TYPE Position */ 833 #define MXC_F_SDHC_CFG_0_SLOT_TYPE ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_SLOT_TYPE_POS)) /**< CFG_0_SLOT_TYPE Mask */ 834 835 /**@} end of group SDHC_CFG_0_Register */ 836 837 /** 838 * @ingroup sdhc_registers 839 * @defgroup SDHC_CFG_1 SDHC_CFG_1 840 * @brief Capabilities 32-63. 841 * @{ 842 */ 843 #define MXC_F_SDHC_CFG_1_SDR50_POS 0 /**< CFG_1_SDR50 Position */ 844 #define MXC_F_SDHC_CFG_1_SDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_SDR50_POS)) /**< CFG_1_SDR50 Mask */ 845 846 #define MXC_F_SDHC_CFG_1_SDR104_POS 1 /**< CFG_1_SDR104 Position */ 847 #define MXC_F_SDHC_CFG_1_SDR104 ((uint32_t)(0x0UL << MXC_F_SDHC_CFG_1_SDR104_POS)) /**< CFG_1_SDR104 Mask */ 848 849 #define MXC_F_SDHC_CFG_1_DDR50_POS 2 /**< CFG_1_DDR50 Position */ 850 #define MXC_F_SDHC_CFG_1_DDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DDR50_POS)) /**< CFG_1_DDR50 Mask */ 851 852 #define MXC_F_SDHC_CFG_1_DRIVER_A_POS 4 /**< CFG_1_DRIVER_A Position */ 853 #define MXC_F_SDHC_CFG_1_DRIVER_A ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_A_POS)) /**< CFG_1_DRIVER_A Mask */ 854 855 #define MXC_F_SDHC_CFG_1_DRIVER_C_POS 5 /**< CFG_1_DRIVER_C Position */ 856 #define MXC_F_SDHC_CFG_1_DRIVER_C ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_C_POS)) /**< CFG_1_DRIVER_C Mask */ 857 858 #define MXC_F_SDHC_CFG_1_DRIVER_D_POS 6 /**< CFG_1_DRIVER_D Position */ 859 #define MXC_F_SDHC_CFG_1_DRIVER_D ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_D_POS)) /**< CFG_1_DRIVER_D Mask */ 860 861 #define MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS 8 /**< CFG_1_TIMER_CNT_TUNING Position */ 862 #define MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING ((uint32_t)(0xFUL << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)) /**< CFG_1_TIMER_CNT_TUNING Mask */ 863 864 #define MXC_F_SDHC_CFG_1_TUNING_SDR50_POS 13 /**< CFG_1_TUNING_SDR50 Position */ 865 #define MXC_F_SDHC_CFG_1_TUNING_SDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_TUNING_SDR50_POS)) /**< CFG_1_TUNING_SDR50 Mask */ 866 867 #define MXC_F_SDHC_CFG_1_RETUNING_POS 14 /**< CFG_1_RETUNING Position */ 868 #define MXC_F_SDHC_CFG_1_RETUNING ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_1_RETUNING_POS)) /**< CFG_1_RETUNING Mask */ 869 870 #define MXC_F_SDHC_CFG_1_CLK_MULTI_POS 16 /**< CFG_1_CLK_MULTI Position */ 871 #define MXC_F_SDHC_CFG_1_CLK_MULTI ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_1_CLK_MULTI_POS)) /**< CFG_1_CLK_MULTI Mask */ 872 873 /**@} end of group SDHC_CFG_1_Register */ 874 875 /** 876 * @ingroup sdhc_registers 877 * @defgroup SDHC_MAX_CURR_CFG SDHC_MAX_CURR_CFG 878 * @brief Maximum Current Capabilities. 879 * @{ 880 */ 881 #define MXC_F_SDHC_MAX_CURR_CFG_V3_3_POS 0 /**< MAX_CURR_CFG_V3_3 Position */ 882 #define MXC_F_SDHC_MAX_CURR_CFG_V3_3 ((uint32_t)(0xFFUL << MXC_F_SDHC_MAX_CURR_CFG_V3_3_POS)) /**< MAX_CURR_CFG_V3_3 Mask */ 883 884 #define MXC_F_SDHC_MAX_CURR_CFG_V3_0_POS 8 /**< MAX_CURR_CFG_V3_0 Position */ 885 #define MXC_F_SDHC_MAX_CURR_CFG_V3_0 ((uint32_t)(0xFFUL << MXC_F_SDHC_MAX_CURR_CFG_V3_0_POS)) /**< MAX_CURR_CFG_V3_0 Mask */ 886 887 #define MXC_F_SDHC_MAX_CURR_CFG_V1_8_POS 16 /**< MAX_CURR_CFG_V1_8 Position */ 888 #define MXC_F_SDHC_MAX_CURR_CFG_V1_8 ((uint32_t)(0xFFUL << MXC_F_SDHC_MAX_CURR_CFG_V1_8_POS)) /**< MAX_CURR_CFG_V1_8 Mask */ 889 890 /**@} end of group SDHC_MAX_CURR_CFG_Register */ 891 892 /** 893 * @ingroup sdhc_registers 894 * @defgroup SDHC_FORCE_CMD SDHC_FORCE_CMD 895 * @brief Force Event for Auto CMD Error Status. 896 * @{ 897 */ 898 #define MXC_F_SDHC_FORCE_CMD_NOT_EXCU_POS 0 /**< FORCE_CMD_NOT_EXCU Position */ 899 #define MXC_F_SDHC_FORCE_CMD_NOT_EXCU ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_NOT_EXCU_POS)) /**< FORCE_CMD_NOT_EXCU Mask */ 900 901 #define MXC_F_SDHC_FORCE_CMD_TO_POS 1 /**< FORCE_CMD_TO Position */ 902 #define MXC_F_SDHC_FORCE_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_TO_POS)) /**< FORCE_CMD_TO Mask */ 903 904 #define MXC_F_SDHC_FORCE_CMD_CRC_POS 2 /**< FORCE_CMD_CRC Position */ 905 #define MXC_F_SDHC_FORCE_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_CRC_POS)) /**< FORCE_CMD_CRC Mask */ 906 907 #define MXC_F_SDHC_FORCE_CMD_END_BIT_POS 3 /**< FORCE_CMD_END_BIT Position */ 908 #define MXC_F_SDHC_FORCE_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_END_BIT_POS)) /**< FORCE_CMD_END_BIT Mask */ 909 910 #define MXC_F_SDHC_FORCE_CMD_INDEX_POS 4 /**< FORCE_CMD_INDEX Position */ 911 #define MXC_F_SDHC_FORCE_CMD_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_INDEX_POS)) /**< FORCE_CMD_INDEX Mask */ 912 913 #define MXC_F_SDHC_FORCE_CMD_NOT_ISSUED_POS 7 /**< FORCE_CMD_NOT_ISSUED Position */ 914 #define MXC_F_SDHC_FORCE_CMD_NOT_ISSUED ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_NOT_ISSUED_POS)) /**< FORCE_CMD_NOT_ISSUED Mask */ 915 916 /**@} end of group SDHC_FORCE_CMD_Register */ 917 918 /** 919 * @ingroup sdhc_registers 920 * @defgroup SDHC_FORCE_EVENT_INT_STAT SDHC_FORCE_EVENT_INT_STAT 921 * @brief Force Event for Error Interrupt Status. 922 * @{ 923 */ 924 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_TO_POS 0 /**< FORCE_EVENT_INT_STAT_CMD_TO Position */ 925 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_TO_POS)) /**< FORCE_EVENT_INT_STAT_CMD_TO Mask */ 926 927 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_CRC_POS 1 /**< FORCE_EVENT_INT_STAT_CMD_CRC Position */ 928 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_CRC_POS)) /**< FORCE_EVENT_INT_STAT_CMD_CRC Mask */ 929 930 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_END_BIT_POS 2 /**< FORCE_EVENT_INT_STAT_CMD_END_BIT Position */ 931 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_END_BIT_POS)) /**< FORCE_EVENT_INT_STAT_CMD_END_BIT Mask */ 932 933 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_INDEX_POS 3 /**< FORCE_EVENT_INT_STAT_CMD_INDEX Position */ 934 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_INDEX_POS)) /**< FORCE_EVENT_INT_STAT_CMD_INDEX Mask */ 935 936 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_TO_POS 4 /**< FORCE_EVENT_INT_STAT_DATA_TO Position */ 937 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_TO_POS)) /**< FORCE_EVENT_INT_STAT_DATA_TO Mask */ 938 939 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_CRC_POS 5 /**< FORCE_EVENT_INT_STAT_DATA_CRC Position */ 940 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_CRC_POS)) /**< FORCE_EVENT_INT_STAT_DATA_CRC Mask */ 941 942 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_END_BIT_POS 6 /**< FORCE_EVENT_INT_STAT_DATA_END_BIT Position */ 943 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_END_BIT_POS)) /**< FORCE_EVENT_INT_STAT_DATA_END_BIT Mask */ 944 945 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CURR_LIMIT_POS 7 /**< FORCE_EVENT_INT_STAT_CURR_LIMIT Position */ 946 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CURR_LIMIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CURR_LIMIT_POS)) /**< FORCE_EVENT_INT_STAT_CURR_LIMIT Mask */ 947 948 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_AUTO_CMD_POS 8 /**< FORCE_EVENT_INT_STAT_AUTO_CMD Position */ 949 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_AUTO_CMD ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_AUTO_CMD_POS)) /**< FORCE_EVENT_INT_STAT_AUTO_CMD Mask */ 950 951 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_ADMA_POS 9 /**< FORCE_EVENT_INT_STAT_ADMA Position */ 952 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_ADMA_POS)) /**< FORCE_EVENT_INT_STAT_ADMA Mask */ 953 954 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_VENDOR_POS 12 /**< FORCE_EVENT_INT_STAT_VENDOR Position */ 955 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_VENDOR ((uint16_t)(0x7UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_VENDOR_POS)) /**< FORCE_EVENT_INT_STAT_VENDOR Mask */ 956 957 /**@} end of group SDHC_FORCE_EVENT_INT_STAT_Register */ 958 959 /** 960 * @ingroup sdhc_registers 961 * @defgroup SDHC_ADMA_ER SDHC_ADMA_ER 962 * @brief ADMA Error Status. 963 * @{ 964 */ 965 #define MXC_F_SDHC_ADMA_ER_STATE_POS 0 /**< ADMA_ER_STATE Position */ 966 #define MXC_F_SDHC_ADMA_ER_STATE ((uint8_t)(0x3UL << MXC_F_SDHC_ADMA_ER_STATE_POS)) /**< ADMA_ER_STATE Mask */ 967 968 #define MXC_F_SDHC_ADMA_ER_LEN_MISMATCH_POS 2 /**< ADMA_ER_LEN_MISMATCH Position */ 969 #define MXC_F_SDHC_ADMA_ER_LEN_MISMATCH ((uint8_t)(0x1UL << MXC_F_SDHC_ADMA_ER_LEN_MISMATCH_POS)) /**< ADMA_ER_LEN_MISMATCH Mask */ 970 971 /**@} end of group SDHC_ADMA_ER_Register */ 972 973 /** 974 * @ingroup sdhc_registers 975 * @defgroup SDHC_ADMA_ADDR_0 SDHC_ADMA_ADDR_0 976 * @brief ADMA System Address 0-31. 977 * @{ 978 */ 979 #define MXC_F_SDHC_ADMA_ADDR_0_ADDR_POS 0 /**< ADMA_ADDR_0_ADDR Position */ 980 #define MXC_F_SDHC_ADMA_ADDR_0_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_ADMA_ADDR_0_ADDR_POS)) /**< ADMA_ADDR_0_ADDR Mask */ 981 982 /**@} end of group SDHC_ADMA_ADDR_0_Register */ 983 984 /** 985 * @ingroup sdhc_registers 986 * @defgroup SDHC_ADMA_ADDR_1 SDHC_ADMA_ADDR_1 987 * @brief ADMA System Address 32-63. 988 * @{ 989 */ 990 #define MXC_F_SDHC_ADMA_ADDR_1_ADDR_POS 0 /**< ADMA_ADDR_1_ADDR Position */ 991 #define MXC_F_SDHC_ADMA_ADDR_1_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_ADMA_ADDR_1_ADDR_POS)) /**< ADMA_ADDR_1_ADDR Mask */ 992 993 /**@} end of group SDHC_ADMA_ADDR_1_Register */ 994 995 /** 996 * @ingroup sdhc_registers 997 * @defgroup SDHC_PRESET_0 SDHC_PRESET_0 998 * @brief Preset Value for Initialization. 999 * @{ 1000 */ 1001 #define MXC_F_SDHC_PRESET_0_SDCLK_FREQ_POS 0 /**< PRESET_0_SDCLK_FREQ Position */ 1002 #define MXC_F_SDHC_PRESET_0_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_0_SDCLK_FREQ_POS)) /**< PRESET_0_SDCLK_FREQ Mask */ 1003 1004 #define MXC_F_SDHC_PRESET_0_CLK_GEN_POS 10 /**< PRESET_0_CLK_GEN Position */ 1005 #define MXC_F_SDHC_PRESET_0_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_0_CLK_GEN_POS)) /**< PRESET_0_CLK_GEN Mask */ 1006 1007 #define MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH_POS 14 /**< PRESET_0_DRIVER_STRENGTH Position */ 1008 #define MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH_POS)) /**< PRESET_0_DRIVER_STRENGTH Mask */ 1009 1010 /**@} end of group SDHC_PRESET_0_Register */ 1011 1012 /** 1013 * @ingroup sdhc_registers 1014 * @defgroup SDHC_PRESET_1 SDHC_PRESET_1 1015 * @brief Preset Value for Default Speed. 1016 * @{ 1017 */ 1018 #define MXC_F_SDHC_PRESET_1_SDCLK_FREQ_POS 0 /**< PRESET_1_SDCLK_FREQ Position */ 1019 #define MXC_F_SDHC_PRESET_1_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_1_SDCLK_FREQ_POS)) /**< PRESET_1_SDCLK_FREQ Mask */ 1020 1021 #define MXC_F_SDHC_PRESET_1_CLK_GEN_POS 10 /**< PRESET_1_CLK_GEN Position */ 1022 #define MXC_F_SDHC_PRESET_1_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_1_CLK_GEN_POS)) /**< PRESET_1_CLK_GEN Mask */ 1023 1024 #define MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH_POS 14 /**< PRESET_1_DRIVER_STRENGTH Position */ 1025 #define MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH_POS)) /**< PRESET_1_DRIVER_STRENGTH Mask */ 1026 1027 /**@} end of group SDHC_PRESET_1_Register */ 1028 1029 /** 1030 * @ingroup sdhc_registers 1031 * @defgroup SDHC_PRESET_2 SDHC_PRESET_2 1032 * @brief Preset Value for High Speed. 1033 * @{ 1034 */ 1035 #define MXC_F_SDHC_PRESET_2_SDCLK_FREQ_POS 0 /**< PRESET_2_SDCLK_FREQ Position */ 1036 #define MXC_F_SDHC_PRESET_2_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_2_SDCLK_FREQ_POS)) /**< PRESET_2_SDCLK_FREQ Mask */ 1037 1038 #define MXC_F_SDHC_PRESET_2_CLK_GEN_POS 10 /**< PRESET_2_CLK_GEN Position */ 1039 #define MXC_F_SDHC_PRESET_2_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_2_CLK_GEN_POS)) /**< PRESET_2_CLK_GEN Mask */ 1040 1041 #define MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH_POS 14 /**< PRESET_2_DRIVER_STRENGTH Position */ 1042 #define MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH_POS)) /**< PRESET_2_DRIVER_STRENGTH Mask */ 1043 1044 /**@} end of group SDHC_PRESET_2_Register */ 1045 1046 /** 1047 * @ingroup sdhc_registers 1048 * @defgroup SDHC_PRESET_3 SDHC_PRESET_3 1049 * @brief Preset Value for SDR12. 1050 * @{ 1051 */ 1052 #define MXC_F_SDHC_PRESET_3_SDCLK_FREQ_POS 0 /**< PRESET_3_SDCLK_FREQ Position */ 1053 #define MXC_F_SDHC_PRESET_3_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_3_SDCLK_FREQ_POS)) /**< PRESET_3_SDCLK_FREQ Mask */ 1054 1055 #define MXC_F_SDHC_PRESET_3_CLK_GEN_POS 10 /**< PRESET_3_CLK_GEN Position */ 1056 #define MXC_F_SDHC_PRESET_3_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_3_CLK_GEN_POS)) /**< PRESET_3_CLK_GEN Mask */ 1057 1058 #define MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH_POS 14 /**< PRESET_3_DRIVER_STRENGTH Position */ 1059 #define MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH_POS)) /**< PRESET_3_DRIVER_STRENGTH Mask */ 1060 1061 /**@} end of group SDHC_PRESET_3_Register */ 1062 1063 /** 1064 * @ingroup sdhc_registers 1065 * @defgroup SDHC_PRESET_4 SDHC_PRESET_4 1066 * @brief Preset Value for SDR25. 1067 * @{ 1068 */ 1069 #define MXC_F_SDHC_PRESET_4_SDCLK_FREQ_POS 0 /**< PRESET_4_SDCLK_FREQ Position */ 1070 #define MXC_F_SDHC_PRESET_4_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_4_SDCLK_FREQ_POS)) /**< PRESET_4_SDCLK_FREQ Mask */ 1071 1072 #define MXC_F_SDHC_PRESET_4_CLK_GEN_POS 10 /**< PRESET_4_CLK_GEN Position */ 1073 #define MXC_F_SDHC_PRESET_4_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_4_CLK_GEN_POS)) /**< PRESET_4_CLK_GEN Mask */ 1074 1075 #define MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH_POS 14 /**< PRESET_4_DRIVER_STRENGTH Position */ 1076 #define MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH_POS)) /**< PRESET_4_DRIVER_STRENGTH Mask */ 1077 1078 /**@} end of group SDHC_PRESET_4_Register */ 1079 1080 /** 1081 * @ingroup sdhc_registers 1082 * @defgroup SDHC_PRESET_5 SDHC_PRESET_5 1083 * @brief Preset Value for SDR50. 1084 * @{ 1085 */ 1086 #define MXC_F_SDHC_PRESET_5_SDCLK_FREQ_POS 0 /**< PRESET_5_SDCLK_FREQ Position */ 1087 #define MXC_F_SDHC_PRESET_5_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_5_SDCLK_FREQ_POS)) /**< PRESET_5_SDCLK_FREQ Mask */ 1088 1089 #define MXC_F_SDHC_PRESET_5_CLK_GEN_POS 10 /**< PRESET_5_CLK_GEN Position */ 1090 #define MXC_F_SDHC_PRESET_5_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_5_CLK_GEN_POS)) /**< PRESET_5_CLK_GEN Mask */ 1091 1092 #define MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH_POS 14 /**< PRESET_5_DRIVER_STRENGTH Position */ 1093 #define MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH_POS)) /**< PRESET_5_DRIVER_STRENGTH Mask */ 1094 1095 /**@} end of group SDHC_PRESET_5_Register */ 1096 1097 /** 1098 * @ingroup sdhc_registers 1099 * @defgroup SDHC_PRESET_6 SDHC_PRESET_6 1100 * @brief Preset Value for SDR104. 1101 * @{ 1102 */ 1103 #define MXC_F_SDHC_PRESET_6_SDCLK_FREQ_POS 0 /**< PRESET_6_SDCLK_FREQ Position */ 1104 #define MXC_F_SDHC_PRESET_6_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_6_SDCLK_FREQ_POS)) /**< PRESET_6_SDCLK_FREQ Mask */ 1105 1106 #define MXC_F_SDHC_PRESET_6_CLK_GEN_POS 10 /**< PRESET_6_CLK_GEN Position */ 1107 #define MXC_F_SDHC_PRESET_6_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_6_CLK_GEN_POS)) /**< PRESET_6_CLK_GEN Mask */ 1108 1109 #define MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH_POS 14 /**< PRESET_6_DRIVER_STRENGTH Position */ 1110 #define MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH_POS)) /**< PRESET_6_DRIVER_STRENGTH Mask */ 1111 1112 /**@} end of group SDHC_PRESET_6_Register */ 1113 1114 /** 1115 * @ingroup sdhc_registers 1116 * @defgroup SDHC_PRESET_7 SDHC_PRESET_7 1117 * @brief Preset Value for DDR50. 1118 * @{ 1119 */ 1120 #define MXC_F_SDHC_PRESET_7_SDCLK_FREQ_POS 0 /**< PRESET_7_SDCLK_FREQ Position */ 1121 #define MXC_F_SDHC_PRESET_7_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_7_SDCLK_FREQ_POS)) /**< PRESET_7_SDCLK_FREQ Mask */ 1122 1123 #define MXC_F_SDHC_PRESET_7_CLK_GEN_POS 10 /**< PRESET_7_CLK_GEN Position */ 1124 #define MXC_F_SDHC_PRESET_7_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_7_CLK_GEN_POS)) /**< PRESET_7_CLK_GEN Mask */ 1125 1126 #define MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH_POS 14 /**< PRESET_7_DRIVER_STRENGTH Position */ 1127 #define MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH_POS)) /**< PRESET_7_DRIVER_STRENGTH Mask */ 1128 1129 /**@} end of group SDHC_PRESET_7_Register */ 1130 1131 /** 1132 * @ingroup sdhc_registers 1133 * @defgroup SDHC_SLOT_INT SDHC_SLOT_INT 1134 * @brief Slot Interrupt Status. 1135 * @{ 1136 */ 1137 #define MXC_F_SDHC_SLOT_INT_INT_SIGNALS_POS 0 /**< SLOT_INT_INT_SIGNALS Position */ 1138 #define MXC_F_SDHC_SLOT_INT_INT_SIGNALS ((uint16_t)(0x1UL << MXC_F_SDHC_SLOT_INT_INT_SIGNALS_POS)) /**< SLOT_INT_INT_SIGNALS Mask */ 1139 1140 /**@} end of group SDHC_SLOT_INT_Register */ 1141 1142 /** 1143 * @ingroup sdhc_registers 1144 * @defgroup SDHC_HOST_CN_VER SDHC_HOST_CN_VER 1145 * @brief Host Controller Version. 1146 * @{ 1147 */ 1148 #define MXC_F_SDHC_HOST_CN_VER_SPEC_VER_POS 0 /**< HOST_CN_VER_SPEC_VER Position */ 1149 #define MXC_F_SDHC_HOST_CN_VER_SPEC_VER ((uint16_t)(0xFFUL << MXC_F_SDHC_HOST_CN_VER_SPEC_VER_POS)) /**< HOST_CN_VER_SPEC_VER Mask */ 1150 1151 #define MXC_F_SDHC_HOST_CN_VER_VEND_VER_POS 8 /**< HOST_CN_VER_VEND_VER Position */ 1152 #define MXC_F_SDHC_HOST_CN_VER_VEND_VER ((uint16_t)(0xFFUL << MXC_F_SDHC_HOST_CN_VER_VEND_VER_POS)) /**< HOST_CN_VER_VEND_VER Mask */ 1153 1154 /**@} end of group SDHC_HOST_CN_VER_Register */ 1155 1156 #ifdef __cplusplus 1157 } 1158 #endif 1159 1160 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_SDHC_REGS_H_ 1161
