1 /** 2 * @file pwrseq_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup pwrseq_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_PWRSEQ_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_PWRSEQ_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup pwrseq 67 * @defgroup pwrseq_registers PWRSEQ_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 69 * @details Power Sequencer / Low Power Control Register. 70 */ 71 72 /** 73 * @ingroup pwrseq_registers 74 * Structure type to access the PWRSEQ Registers. 75 */ 76 typedef struct { 77 __IO uint32_t lpcn; /**< <tt>\b 0x00:</tt> PWRSEQ LPCN Register */ 78 __IO uint32_t lpwkst0; /**< <tt>\b 0x04:</tt> PWRSEQ LPWKST0 Register */ 79 __IO uint32_t lpwken0; /**< <tt>\b 0x08:</tt> PWRSEQ LPWKEN0 Register */ 80 __IO uint32_t lpwkst1; /**< <tt>\b 0x0C:</tt> PWRSEQ LPWKST1 Register */ 81 __IO uint32_t lpwken1; /**< <tt>\b 0x10:</tt> PWRSEQ LPWKEN1 Register */ 82 __IO uint32_t lpwkst2; /**< <tt>\b 0x14:</tt> PWRSEQ LPWKST2 Register */ 83 __IO uint32_t lpwken2; /**< <tt>\b 0x18:</tt> PWRSEQ LPWKEN2 Register */ 84 __IO uint32_t lpwkst3; /**< <tt>\b 0x1C:</tt> PWRSEQ LPWKST3 Register */ 85 __IO uint32_t lpwken3; /**< <tt>\b 0x20:</tt> PWRSEQ LPWKEN3 Register */ 86 __R uint32_t rsv_0x24_0x2f[3]; 87 __IO uint32_t lppwst; /**< <tt>\b 0x30:</tt> PWRSEQ LPPWST Register */ 88 __IO uint32_t lppwen; /**< <tt>\b 0x34:</tt> PWRSEQ LPPWEN Register */ 89 __R uint32_t rsv_0x38_0x47[4]; 90 __IO uint32_t gp0; /**< <tt>\b 0x48:</tt> PWRSEQ GP0 Register */ 91 __IO uint32_t gp1; /**< <tt>\b 0x4C:</tt> PWRSEQ GP1 Register */ 92 } mxc_pwrseq_regs_t; 93 94 /* Register offsets for module PWRSEQ */ 95 /** 96 * @ingroup pwrseq_registers 97 * @defgroup PWRSEQ_Register_Offsets Register Offsets 98 * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. 99 * @{ 100 */ 101 #define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */ 102 #define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */ 103 #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */ 104 #define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x000C</tt> */ 105 #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0010</tt> */ 106 #define MXC_R_PWRSEQ_LPWKST2 ((uint32_t)0x00000014UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0014</tt> */ 107 #define MXC_R_PWRSEQ_LPWKEN2 ((uint32_t)0x00000018UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0018</tt> */ 108 #define MXC_R_PWRSEQ_LPWKST3 ((uint32_t)0x0000001CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x001C</tt> */ 109 #define MXC_R_PWRSEQ_LPWKEN3 ((uint32_t)0x00000020UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0020</tt> */ 110 #define MXC_R_PWRSEQ_LPPWST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */ 111 #define MXC_R_PWRSEQ_LPPWEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */ 112 #define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0048</tt> */ 113 #define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x004C</tt> */ 114 /**@} end of group pwrseq_registers */ 115 116 /** 117 * @ingroup pwrseq_registers 118 * @defgroup PWRSEQ_LPCN PWRSEQ_LPCN 119 * @brief Low Power Control Register. 120 * @{ 121 */ 122 #define MXC_F_PWRSEQ_LPCN_RAMRET0_POS 0 /**< LPCN_RAMRET0 Position */ 123 #define MXC_F_PWRSEQ_LPCN_RAMRET0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET0_POS)) /**< LPCN_RAMRET0 Mask */ 124 125 #define MXC_F_PWRSEQ_LPCN_RAMRET1_POS 1 /**< LPCN_RAMRET1 Position */ 126 #define MXC_F_PWRSEQ_LPCN_RAMRET1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET1_POS)) /**< LPCN_RAMRET1 Mask */ 127 128 #define MXC_F_PWRSEQ_LPCN_RAMRET2_POS 2 /**< LPCN_RAMRET2 Position */ 129 #define MXC_F_PWRSEQ_LPCN_RAMRET2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET2_POS)) /**< LPCN_RAMRET2 Mask */ 130 131 #define MXC_F_PWRSEQ_LPCN_RAMRET3_POS 3 /**< LPCN_RAMRET3 Position */ 132 #define MXC_F_PWRSEQ_LPCN_RAMRET3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET3_POS)) /**< LPCN_RAMRET3 Mask */ 133 134 #define MXC_F_PWRSEQ_LPCN_RAMRET4_POS 4 /**< LPCN_RAMRET4 Position */ 135 #define MXC_F_PWRSEQ_LPCN_RAMRET4 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET4_POS)) /**< LPCN_RAMRET4 Mask */ 136 137 #define MXC_F_PWRSEQ_LPCN_RAMRET5_POS 5 /**< LPCN_RAMRET5 Position */ 138 #define MXC_F_PWRSEQ_LPCN_RAMRET5 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET5_POS)) /**< LPCN_RAMRET5 Mask */ 139 140 #define MXC_F_PWRSEQ_LPCN_RAMRET6_POS 6 /**< LPCN_RAMRET6 Position */ 141 #define MXC_F_PWRSEQ_LPCN_RAMRET6 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET6_POS)) /**< LPCN_RAMRET6 Mask */ 142 143 #define MXC_F_PWRSEQ_LPCN_RAMRET7_POS 7 /**< LPCN_RAMRET7 Position */ 144 #define MXC_F_PWRSEQ_LPCN_RAMRET7 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET7_POS)) /**< LPCN_RAMRET7 Mask */ 145 146 #define MXC_F_PWRSEQ_LPCN_ISOCLK_SELECT_POS 8 /**< LPCN_ISOCLK_SELECT Position */ 147 #define MXC_F_PWRSEQ_LPCN_ISOCLK_SELECT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ISOCLK_SELECT_POS)) /**< LPCN_ISOCLK_SELECT Mask */ 148 149 #define MXC_F_PWRSEQ_LPCN_FAST_ENTRY_DIS_POS 9 /**< LPCN_FAST_ENTRY_DIS Position */ 150 #define MXC_F_PWRSEQ_LPCN_FAST_ENTRY_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FAST_ENTRY_DIS_POS)) /**< LPCN_FAST_ENTRY_DIS Mask */ 151 152 #define MXC_F_PWRSEQ_LPCN_BGOFF_POS 11 /**< LPCN_BGOFF Position */ 153 #define MXC_F_PWRSEQ_LPCN_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS)) /**< LPCN_BGOFF Mask */ 154 155 #define MXC_F_PWRSEQ_LPCN_WKRST_POS 31 /**< LPCN_WKRST Position */ 156 #define MXC_F_PWRSEQ_LPCN_WKRST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_WKRST_POS)) /**< LPCN_WKRST Mask */ 157 158 /**@} end of group PWRSEQ_LPCN_Register */ 159 160 /** 161 * @ingroup pwrseq_registers 162 * @defgroup PWRSEQ_LPWKST0 PWRSEQ_LPWKST0 163 * @brief Low Power I/O Wakeup Status Register 0. This register indicates the low power 164 * wakeup status for GPIO0. 165 * @{ 166 */ 167 #define MXC_F_PWRSEQ_LPWKST0_WAKEST_POS 0 /**< LPWKST0_WAKEST Position */ 168 #define MXC_F_PWRSEQ_LPWKST0_WAKEST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKST0_WAKEST_POS)) /**< LPWKST0_WAKEST Mask */ 169 170 /**@} end of group PWRSEQ_LPWKST0_Register */ 171 172 /** 173 * @ingroup pwrseq_registers 174 * @defgroup PWRSEQ_LPWKEN0 PWRSEQ_LPWKEN0 175 * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup 176 * functionality for GPIO0. 177 * @{ 178 */ 179 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS 0 /**< LPWKEN0_WAKEEN Position */ 180 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS)) /**< LPWKEN0_WAKEEN Mask */ 181 182 /**@} end of group PWRSEQ_LPWKEN0_Register */ 183 184 /** 185 * @ingroup pwrseq_registers 186 * @defgroup PWRSEQ_LPWKST1 PWRSEQ_LPWKST1 187 * @brief Low Power I/O Wakeup Status Register 1. This register indicates the low power 188 * wakeup status for GPIO1. 189 * @{ 190 */ 191 #define MXC_F_PWRSEQ_LPWKST1_WAKEST_POS 0 /**< LPWKST1_WAKEST Position */ 192 #define MXC_F_PWRSEQ_LPWKST1_WAKEST ((uint32_t)(0x3FFUL << MXC_F_PWRSEQ_LPWKST1_WAKEST_POS)) /**< LPWKST1_WAKEST Mask */ 193 194 /**@} end of group PWRSEQ_LPWKST1_Register */ 195 196 /** 197 * @ingroup pwrseq_registers 198 * @defgroup PWRSEQ_LPWKEN1 PWRSEQ_LPWKEN1 199 * @brief Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup 200 * functionality for GPIO1. 201 * @{ 202 */ 203 #define MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS 0 /**< LPWKEN1_WAKEEN Position */ 204 #define MXC_F_PWRSEQ_LPWKEN1_WAKEEN ((uint32_t)(0x3FFUL << MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS)) /**< LPWKEN1_WAKEEN Mask */ 205 206 /**@} end of group PWRSEQ_LPWKEN1_Register */ 207 208 /** 209 * @ingroup pwrseq_registers 210 * @defgroup PWRSEQ_LPWKST2 PWRSEQ_LPWKST2 211 * @brief Low Power I/O Wakeup Status Register 2. This register indicates the low power 212 * wakeup status for GPIO2. 213 * @{ 214 */ 215 #define MXC_F_PWRSEQ_LPWKST2_WAKEST_POS 0 /**< LPWKST2_WAKEST Position */ 216 #define MXC_F_PWRSEQ_LPWKST2_WAKEST ((uint32_t)(0xFFUL << MXC_F_PWRSEQ_LPWKST2_WAKEST_POS)) /**< LPWKST2_WAKEST Mask */ 217 218 /**@} end of group PWRSEQ_LPWKST2_Register */ 219 220 /** 221 * @ingroup pwrseq_registers 222 * @defgroup PWRSEQ_LPWKEN2 PWRSEQ_LPWKEN2 223 * @brief Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup 224 * functionality for GPIO2. 225 * @{ 226 */ 227 #define MXC_F_PWRSEQ_LPWKEN2_WAKEEN_POS 0 /**< LPWKEN2_WAKEEN Position */ 228 #define MXC_F_PWRSEQ_LPWKEN2_WAKEEN ((uint32_t)(0xFFUL << MXC_F_PWRSEQ_LPWKEN2_WAKEEN_POS)) /**< LPWKEN2_WAKEEN Mask */ 229 230 /**@} end of group PWRSEQ_LPWKEN2_Register */ 231 232 /** 233 * @ingroup pwrseq_registers 234 * @defgroup PWRSEQ_LPWKST3 PWRSEQ_LPWKST3 235 * @brief Low Power I/O Wakeup Status Register 3. This register indicates the low power 236 * wakeup status for GPIO3. 237 * @{ 238 */ 239 #define MXC_F_PWRSEQ_LPWKST3_WAKEST_POS 0 /**< LPWKST3_WAKEST Position */ 240 #define MXC_F_PWRSEQ_LPWKST3_WAKEST ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKST3_WAKEST_POS)) /**< LPWKST3_WAKEST Mask */ 241 242 /**@} end of group PWRSEQ_LPWKST3_Register */ 243 244 /** 245 * @ingroup pwrseq_registers 246 * @defgroup PWRSEQ_LPWKEN3 PWRSEQ_LPWKEN3 247 * @brief Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup 248 * functionality for GPIO3. 249 * @{ 250 */ 251 #define MXC_F_PWRSEQ_LPWKEN3_WAKEEN_POS 0 /**< LPWKEN3_WAKEEN Position */ 252 #define MXC_F_PWRSEQ_LPWKEN3_WAKEEN ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKEN3_WAKEEN_POS)) /**< LPWKEN3_WAKEEN Mask */ 253 254 /**@} end of group PWRSEQ_LPWKEN3_Register */ 255 256 /** 257 * @ingroup pwrseq_registers 258 * @defgroup PWRSEQ_LPPWST PWRSEQ_LPPWST 259 * @brief Low Power Peripheral Wakeup Status Register. 260 * @{ 261 */ 262 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0_POS 4 /**< LPPWST_AINCOMP0 Position */ 263 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP0_POS)) /**< LPPWST_AINCOMP0 Mask */ 264 265 #define MXC_F_PWRSEQ_LPPWST_BACKUP_POS 16 /**< LPPWST_BACKUP Position */ 266 #define MXC_F_PWRSEQ_LPPWST_BACKUP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_BACKUP_POS)) /**< LPPWST_BACKUP Mask */ 267 268 #define MXC_F_PWRSEQ_LPPWST_RESET_POS 17 /**< LPPWST_RESET Position */ 269 #define MXC_F_PWRSEQ_LPPWST_RESET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_RESET_POS)) /**< LPPWST_RESET Mask */ 270 271 /**@} end of group PWRSEQ_LPPWST_Register */ 272 273 /** 274 * @ingroup pwrseq_registers 275 * @defgroup PWRSEQ_LPPWEN PWRSEQ_LPPWEN 276 * @brief Low Power Peripheral Wakeup Enable Register. 277 * @{ 278 */ 279 #define MXC_F_PWRSEQ_LPPWEN_USBLS_POS 0 /**< LPPWEN_USBLS Position */ 280 #define MXC_F_PWRSEQ_LPPWEN_USBLS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWEN_USBLS_POS)) /**< LPPWEN_USBLS Mask */ 281 282 #define MXC_F_PWRSEQ_LPPWEN_USBVBUS_POS 2 /**< LPPWEN_USBVBUS Position */ 283 #define MXC_F_PWRSEQ_LPPWEN_USBVBUS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_USBVBUS_POS)) /**< LPPWEN_USBVBUS Mask */ 284 285 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0_POS 4 /**< LPPWEN_AINCOMP0 Position */ 286 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP0_POS)) /**< LPPWEN_AINCOMP0 Mask */ 287 288 #define MXC_F_PWRSEQ_LPPWEN_WDT0_POS 8 /**< LPPWEN_WDT0 Position */ 289 #define MXC_F_PWRSEQ_LPPWEN_WDT0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_WDT0_POS)) /**< LPPWEN_WDT0 Mask */ 290 291 #define MXC_F_PWRSEQ_LPPWEN_WDT1_POS 9 /**< LPPWEN_WDT1 Position */ 292 #define MXC_F_PWRSEQ_LPPWEN_WDT1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_WDT1_POS)) /**< LPPWEN_WDT1 Mask */ 293 294 #define MXC_F_PWRSEQ_LPPWEN_CPU1_POS 10 /**< LPPWEN_CPU1 Position */ 295 #define MXC_F_PWRSEQ_LPPWEN_CPU1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_CPU1_POS)) /**< LPPWEN_CPU1 Mask */ 296 297 #define MXC_F_PWRSEQ_LPPWEN_TMR0_POS 11 /**< LPPWEN_TMR0 Position */ 298 #define MXC_F_PWRSEQ_LPPWEN_TMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR0_POS)) /**< LPPWEN_TMR0 Mask */ 299 300 #define MXC_F_PWRSEQ_LPPWEN_TMR1_POS 12 /**< LPPWEN_TMR1 Position */ 301 #define MXC_F_PWRSEQ_LPPWEN_TMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR1_POS)) /**< LPPWEN_TMR1 Mask */ 302 303 #define MXC_F_PWRSEQ_LPPWEN_TMR2_POS 13 /**< LPPWEN_TMR2 Position */ 304 #define MXC_F_PWRSEQ_LPPWEN_TMR2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR2_POS)) /**< LPPWEN_TMR2 Mask */ 305 306 #define MXC_F_PWRSEQ_LPPWEN_TMR3_POS 14 /**< LPPWEN_TMR3 Position */ 307 #define MXC_F_PWRSEQ_LPPWEN_TMR3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR3_POS)) /**< LPPWEN_TMR3 Mask */ 308 309 #define MXC_F_PWRSEQ_LPPWEN_TMR4_POS 15 /**< LPPWEN_TMR4 Position */ 310 #define MXC_F_PWRSEQ_LPPWEN_TMR4 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR4_POS)) /**< LPPWEN_TMR4 Mask */ 311 312 #define MXC_F_PWRSEQ_LPPWEN_TMR5_POS 16 /**< LPPWEN_TMR5 Position */ 313 #define MXC_F_PWRSEQ_LPPWEN_TMR5 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR5_POS)) /**< LPPWEN_TMR5 Mask */ 314 315 #define MXC_F_PWRSEQ_LPPWEN_UART0_POS 17 /**< LPPWEN_UART0 Position */ 316 #define MXC_F_PWRSEQ_LPPWEN_UART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART0_POS)) /**< LPPWEN_UART0 Mask */ 317 318 #define MXC_F_PWRSEQ_LPPWEN_UART1_POS 18 /**< LPPWEN_UART1 Position */ 319 #define MXC_F_PWRSEQ_LPPWEN_UART1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART1_POS)) /**< LPPWEN_UART1 Mask */ 320 321 #define MXC_F_PWRSEQ_LPPWEN_UART2_POS 19 /**< LPPWEN_UART2 Position */ 322 #define MXC_F_PWRSEQ_LPPWEN_UART2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART2_POS)) /**< LPPWEN_UART2 Mask */ 323 324 #define MXC_F_PWRSEQ_LPPWEN_UART3_POS 20 /**< LPPWEN_UART3 Position */ 325 #define MXC_F_PWRSEQ_LPPWEN_UART3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART3_POS)) /**< LPPWEN_UART3 Mask */ 326 327 #define MXC_F_PWRSEQ_LPPWEN_I2C0_POS 21 /**< LPPWEN_I2C0 Position */ 328 #define MXC_F_PWRSEQ_LPPWEN_I2C0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2C0_POS)) /**< LPPWEN_I2C0 Mask */ 329 330 #define MXC_F_PWRSEQ_LPPWEN_I2C1_POS 22 /**< LPPWEN_I2C1 Position */ 331 #define MXC_F_PWRSEQ_LPPWEN_I2C1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2C1_POS)) /**< LPPWEN_I2C1 Mask */ 332 333 #define MXC_F_PWRSEQ_LPPWEN_I2C2_POS 23 /**< LPPWEN_I2C2 Position */ 334 #define MXC_F_PWRSEQ_LPPWEN_I2C2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2C2_POS)) /**< LPPWEN_I2C2 Mask */ 335 336 #define MXC_F_PWRSEQ_LPPWEN_I2S_POS 24 /**< LPPWEN_I2S Position */ 337 #define MXC_F_PWRSEQ_LPPWEN_I2S ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2S_POS)) /**< LPPWEN_I2S Mask */ 338 339 #define MXC_F_PWRSEQ_LPPWEN_SPI1_POS 25 /**< LPPWEN_SPI1 Position */ 340 #define MXC_F_PWRSEQ_LPPWEN_SPI1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_SPI1_POS)) /**< LPPWEN_SPI1 Mask */ 341 342 #define MXC_F_PWRSEQ_LPPWEN_LPCMP_POS 26 /**< LPPWEN_LPCMP Position */ 343 #define MXC_F_PWRSEQ_LPPWEN_LPCMP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_LPCMP_POS)) /**< LPPWEN_LPCMP Mask */ 344 345 /**@} end of group PWRSEQ_LPPWEN_Register */ 346 347 #ifdef __cplusplus 348 } 349 #endif 350 351 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_PWRSEQ_REGS_H_ 352
