1 /** 2 * @file mcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup mcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_MCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_MCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup mcr 67 * @defgroup mcr_registers MCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 69 * @details Misc Control. 70 */ 71 72 /** 73 * @ingroup mcr_registers 74 * Structure type to access the MCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t eccen; /**< <tt>\b 0x00:</tt> MCR ECCEN Register */ 78 __IO uint32_t ipo_mtrim; /**< <tt>\b 0x04:</tt> MCR IPO_MTRIM Register */ 79 __IO uint32_t outen; /**< <tt>\b 0x08:</tt> MCR OUTEN Register */ 80 __IO uint32_t cmp_ctrl; /**< <tt>\b 0x0C:</tt> MCR CMP_CTRL Register */ 81 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> MCR CTRL Register */ 82 __R uint32_t rsv_0x14_0x1f[3]; 83 __IO uint32_t gpio3_ctrl; /**< <tt>\b 0x20:</tt> MCR GPIO3_CTRL Register */ 84 __R uint32_t rsv_0x24_0x3f[7]; 85 __IO uint32_t cwd0; /**< <tt>\b 0x40:</tt> MCR CWD0 Register */ 86 __IO uint32_t cwd1; /**< <tt>\b 0x44:</tt> MCR CWD1 Register */ 87 __R uint32_t rsv_0x48_0x4f[2]; 88 __IO uint32_t adccfg0; /**< <tt>\b 0x50:</tt> MCR ADCCFG0 Register */ 89 __IO uint32_t adccfg1; /**< <tt>\b 0x54:</tt> MCR ADCCFG1 Register */ 90 __IO uint32_t adccfg2; /**< <tt>\b 0x58:</tt> MCR ADCCFG2 Register */ 91 __R uint32_t rsv_0x5c; 92 __IO uint32_t ldoctrl; /**< <tt>\b 0x60:</tt> MCR LDOCTRL Register */ 93 } mxc_mcr_regs_t; 94 95 /* Register offsets for module MCR */ 96 /** 97 * @ingroup mcr_registers 98 * @defgroup MCR_Register_Offsets Register Offsets 99 * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. 100 * @{ 101 */ 102 #define MXC_R_MCR_ECCEN ((uint32_t)0x00000000UL) /**< Offset from MCR Base Address: <tt> 0x0000</tt> */ 103 #define MXC_R_MCR_IPO_MTRIM ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: <tt> 0x0004</tt> */ 104 #define MXC_R_MCR_OUTEN ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: <tt> 0x0008</tt> */ 105 #define MXC_R_MCR_CMP_CTRL ((uint32_t)0x0000000CUL) /**< Offset from MCR Base Address: <tt> 0x000C</tt> */ 106 #define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: <tt> 0x0010</tt> */ 107 #define MXC_R_MCR_GPIO3_CTRL ((uint32_t)0x00000020UL) /**< Offset from MCR Base Address: <tt> 0x0020</tt> */ 108 #define MXC_R_MCR_CWD0 ((uint32_t)0x00000040UL) /**< Offset from MCR Base Address: <tt> 0x0040</tt> */ 109 #define MXC_R_MCR_CWD1 ((uint32_t)0x00000044UL) /**< Offset from MCR Base Address: <tt> 0x0044</tt> */ 110 #define MXC_R_MCR_ADCCFG0 ((uint32_t)0x00000050UL) /**< Offset from MCR Base Address: <tt> 0x0050</tt> */ 111 #define MXC_R_MCR_ADCCFG1 ((uint32_t)0x00000054UL) /**< Offset from MCR Base Address: <tt> 0x0054</tt> */ 112 #define MXC_R_MCR_ADCCFG2 ((uint32_t)0x00000058UL) /**< Offset from MCR Base Address: <tt> 0x0058</tt> */ 113 #define MXC_R_MCR_LDOCTRL ((uint32_t)0x00000060UL) /**< Offset from MCR Base Address: <tt> 0x0060</tt> */ 114 /**@} end of group mcr_registers */ 115 116 /** 117 * @ingroup mcr_registers 118 * @defgroup MCR_ECCEN MCR_ECCEN 119 * @brief ECC Enable Register 120 * @{ 121 */ 122 #define MXC_F_MCR_ECCEN_RAM0_POS 0 /**< ECCEN_RAM0 Position */ 123 #define MXC_F_MCR_ECCEN_RAM0 ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_RAM0_POS)) /**< ECCEN_RAM0 Mask */ 124 125 /**@} end of group MCR_ECCEN_Register */ 126 127 /** 128 * @ingroup mcr_registers 129 * @defgroup MCR_IPO_MTRIM MCR_IPO_MTRIM 130 * @brief IPO Manual Register 131 * @{ 132 */ 133 #define MXC_F_MCR_IPO_MTRIM_MTRIM_POS 0 /**< IPO_MTRIM_MTRIM Position */ 134 #define MXC_F_MCR_IPO_MTRIM_MTRIM ((uint32_t)(0xFFUL << MXC_F_MCR_IPO_MTRIM_MTRIM_POS)) /**< IPO_MTRIM_MTRIM Mask */ 135 136 #define MXC_F_MCR_IPO_MTRIM_TRIM_RANGE_POS 8 /**< IPO_MTRIM_TRIM_RANGE Position */ 137 #define MXC_F_MCR_IPO_MTRIM_TRIM_RANGE ((uint32_t)(0x1UL << MXC_F_MCR_IPO_MTRIM_TRIM_RANGE_POS)) /**< IPO_MTRIM_TRIM_RANGE Mask */ 138 139 /**@} end of group MCR_IPO_MTRIM_Register */ 140 141 /** 142 * @ingroup mcr_registers 143 * @defgroup MCR_OUTEN MCR_OUTEN 144 * @brief Output Enable Register 145 * @{ 146 */ 147 #define MXC_F_MCR_OUTEN_SQWOUT_EN_POS 0 /**< OUTEN_SQWOUT_EN Position */ 148 #define MXC_F_MCR_OUTEN_SQWOUT_EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_SQWOUT_EN_POS)) /**< OUTEN_SQWOUT_EN Mask */ 149 150 #define MXC_F_MCR_OUTEN_PDOWN_OUT_EN_POS 1 /**< OUTEN_PDOWN_OUT_EN Position */ 151 #define MXC_F_MCR_OUTEN_PDOWN_OUT_EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_PDOWN_OUT_EN_POS)) /**< OUTEN_PDOWN_OUT_EN Mask */ 152 153 /**@} end of group MCR_OUTEN_Register */ 154 155 /** 156 * @ingroup mcr_registers 157 * @defgroup MCR_CMP_CTRL MCR_CMP_CTRL 158 * @brief Comparator Control Register. 159 * @{ 160 */ 161 #define MXC_F_MCR_CMP_CTRL_EN_POS 0 /**< CMP_CTRL_EN Position */ 162 #define MXC_F_MCR_CMP_CTRL_EN ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_EN_POS)) /**< CMP_CTRL_EN Mask */ 163 164 #define MXC_F_MCR_CMP_CTRL_POL_POS 5 /**< CMP_CTRL_POL Position */ 165 #define MXC_F_MCR_CMP_CTRL_POL ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_POL_POS)) /**< CMP_CTRL_POL Mask */ 166 167 #define MXC_F_MCR_CMP_CTRL_INT_EN_POS 6 /**< CMP_CTRL_INT_EN Position */ 168 #define MXC_F_MCR_CMP_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_INT_EN_POS)) /**< CMP_CTRL_INT_EN Mask */ 169 170 #define MXC_F_MCR_CMP_CTRL_OUT_POS 14 /**< CMP_CTRL_OUT Position */ 171 #define MXC_F_MCR_CMP_CTRL_OUT ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_OUT_POS)) /**< CMP_CTRL_OUT Mask */ 172 173 #define MXC_F_MCR_CMP_CTRL_INT_FL_POS 15 /**< CMP_CTRL_INT_FL Position */ 174 #define MXC_F_MCR_CMP_CTRL_INT_FL ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_INT_FL_POS)) /**< CMP_CTRL_INT_FL Mask */ 175 176 /**@} end of group MCR_CMP_CTRL_Register */ 177 178 /** 179 * @ingroup mcr_registers 180 * @defgroup MCR_CTRL MCR_CTRL 181 * @brief Miscellaneous Control Register. 182 * @{ 183 */ 184 #define MXC_F_MCR_CTRL_CMPHYST_POS 0 /**< CTRL_CMPHYST Position */ 185 #define MXC_F_MCR_CTRL_CMPHYST ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_CMPHYST_POS)) /**< CTRL_CMPHYST Mask */ 186 187 #define MXC_F_MCR_CTRL_INRO_EN_POS 2 /**< CTRL_INRO_EN Position */ 188 #define MXC_F_MCR_CTRL_INRO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_INRO_EN_POS)) /**< CTRL_INRO_EN Mask */ 189 190 #define MXC_F_MCR_CTRL_ERTCO_EN_POS 3 /**< CTRL_ERTCO_EN Position */ 191 #define MXC_F_MCR_CTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_EN_POS)) /**< CTRL_ERTCO_EN Mask */ 192 193 #define MXC_F_MCR_CTRL_IBRO_EN_POS 4 /**< CTRL_IBRO_EN Position */ 194 #define MXC_F_MCR_CTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_IBRO_EN_POS)) /**< CTRL_IBRO_EN Mask */ 195 196 #define MXC_F_MCR_CTRL_SIMO_CLKSCL_EN_POS 8 /**< CTRL_SIMO_CLKSCL_EN Position */ 197 #define MXC_F_MCR_CTRL_SIMO_CLKSCL_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_SIMO_CLKSCL_EN_POS)) /**< CTRL_SIMO_CLKSCL_EN Mask */ 198 199 #define MXC_F_MCR_CTRL_SIMO_RSTD_POS 9 /**< CTRL_SIMO_RSTD Position */ 200 #define MXC_F_MCR_CTRL_SIMO_RSTD ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_SIMO_RSTD_POS)) /**< CTRL_SIMO_RSTD Mask */ 201 202 /**@} end of group MCR_CTRL_Register */ 203 204 /** 205 * @ingroup mcr_registers 206 * @defgroup MCR_GPIO3_CTRL MCR_GPIO3_CTRL 207 * @brief GPIO3 Pin Control Register. 208 * @{ 209 */ 210 #define MXC_F_MCR_GPIO3_CTRL_P30_DO_POS 0 /**< GPIO3_CTRL_P30_DO Position */ 211 #define MXC_F_MCR_GPIO3_CTRL_P30_DO ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_DO_POS)) /**< GPIO3_CTRL_P30_DO Mask */ 212 213 #define MXC_F_MCR_GPIO3_CTRL_P30_OE_POS 1 /**< GPIO3_CTRL_P30_OE Position */ 214 #define MXC_F_MCR_GPIO3_CTRL_P30_OE ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_OE_POS)) /**< GPIO3_CTRL_P30_OE Mask */ 215 216 #define MXC_F_MCR_GPIO3_CTRL_P30_PE_POS 2 /**< GPIO3_CTRL_P30_PE Position */ 217 #define MXC_F_MCR_GPIO3_CTRL_P30_PE ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_PE_POS)) /**< GPIO3_CTRL_P30_PE Mask */ 218 219 #define MXC_F_MCR_GPIO3_CTRL_P30_IN_POS 3 /**< GPIO3_CTRL_P30_IN Position */ 220 #define MXC_F_MCR_GPIO3_CTRL_P30_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_IN_POS)) /**< GPIO3_CTRL_P30_IN Mask */ 221 222 #define MXC_F_MCR_GPIO3_CTRL_P31_DO_POS 4 /**< GPIO3_CTRL_P31_DO Position */ 223 #define MXC_F_MCR_GPIO3_CTRL_P31_DO ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_DO_POS)) /**< GPIO3_CTRL_P31_DO Mask */ 224 225 #define MXC_F_MCR_GPIO3_CTRL_P31_OE_POS 5 /**< GPIO3_CTRL_P31_OE Position */ 226 #define MXC_F_MCR_GPIO3_CTRL_P31_OE ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_OE_POS)) /**< GPIO3_CTRL_P31_OE Mask */ 227 228 #define MXC_F_MCR_GPIO3_CTRL_P31_PE_POS 6 /**< GPIO3_CTRL_P31_PE Position */ 229 #define MXC_F_MCR_GPIO3_CTRL_P31_PE ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_PE_POS)) /**< GPIO3_CTRL_P31_PE Mask */ 230 231 #define MXC_F_MCR_GPIO3_CTRL_P31_IN_POS 7 /**< GPIO3_CTRL_P31_IN Position */ 232 #define MXC_F_MCR_GPIO3_CTRL_P31_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_IN_POS)) /**< GPIO3_CTRL_P31_IN Mask */ 233 234 /**@} end of group MCR_GPIO3_CTRL_Register */ 235 236 /** 237 * @ingroup mcr_registers 238 * @defgroup MCR_CWD0 MCR_CWD0 239 * @brief Code Word Data0 240 * @{ 241 */ 242 #define MXC_F_MCR_CWD0_DATA_POS 0 /**< CWD0_DATA Position */ 243 #define MXC_F_MCR_CWD0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_MCR_CWD0_DATA_POS)) /**< CWD0_DATA Mask */ 244 245 /**@} end of group MCR_CWD0_Register */ 246 247 /** 248 * @ingroup mcr_registers 249 * @defgroup MCR_CWD1 MCR_CWD1 250 * @brief Code Word Data1 251 * @{ 252 */ 253 #define MXC_F_MCR_CWD1_DATA_POS 0 /**< CWD1_DATA Position */ 254 #define MXC_F_MCR_CWD1_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_MCR_CWD1_DATA_POS)) /**< CWD1_DATA Mask */ 255 256 /**@} end of group MCR_CWD1_Register */ 257 258 /** 259 * @ingroup mcr_registers 260 * @defgroup MCR_ADCCFG0 MCR_ADCCFG0 261 * @brief ADC Config 0 262 * @{ 263 */ 264 #define MXC_F_MCR_ADCCFG0_LP_5K_DIS_POS 0 /**< ADCCFG0_LP_5K_DIS Position */ 265 #define MXC_F_MCR_ADCCFG0_LP_5K_DIS ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG0_LP_5K_DIS_POS)) /**< ADCCFG0_LP_5K_DIS Mask */ 266 267 #define MXC_F_MCR_ADCCFG0_LP_50K_DIS_POS 1 /**< ADCCFG0_LP_50K_DIS Position */ 268 #define MXC_F_MCR_ADCCFG0_LP_50K_DIS ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG0_LP_50K_DIS_POS)) /**< ADCCFG0_LP_50K_DIS Mask */ 269 270 #define MXC_F_MCR_ADCCFG0_EXT_REF_POS 2 /**< ADCCFG0_EXT_REF Position */ 271 #define MXC_F_MCR_ADCCFG0_EXT_REF ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG0_EXT_REF_POS)) /**< ADCCFG0_EXT_REF Mask */ 272 273 #define MXC_F_MCR_ADCCFG0_REF_SEL_POS 3 /**< ADCCFG0_REF_SEL Position */ 274 #define MXC_F_MCR_ADCCFG0_REF_SEL ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG0_REF_SEL_POS)) /**< ADCCFG0_REF_SEL Mask */ 275 276 /**@} end of group MCR_ADCCFG0_Register */ 277 278 /** 279 * @ingroup mcr_registers 280 * @defgroup MCR_ADCCFG1 MCR_ADCCFG1 281 * @brief ADC Config 1 282 * @{ 283 */ 284 #define MXC_F_MCR_ADCCFG1_CHX_PU_DYN_POS 0 /**< ADCCFG1_CHX_PU_DYN Position */ 285 #define MXC_F_MCR_ADCCFG1_CHX_PU_DYN ((uint32_t)(0x1FFFUL << MXC_F_MCR_ADCCFG1_CHX_PU_DYN_POS)) /**< ADCCFG1_CHX_PU_DYN Mask */ 286 287 /**@} end of group MCR_ADCCFG1_Register */ 288 289 /** 290 * @ingroup mcr_registers 291 * @defgroup MCR_ADCCFG2 MCR_ADCCFG2 292 * @brief ADC Config 2 293 * @{ 294 */ 295 #define MXC_F_MCR_ADCCFG2_CH0_POS 0 /**< ADCCFG2_CH0 Position */ 296 #define MXC_F_MCR_ADCCFG2_CH0 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH0_POS)) /**< ADCCFG2_CH0 Mask */ 297 #define MXC_V_MCR_ADCCFG2_CH0_DIV1 ((uint32_t)0x0UL) /**< ADCCFG2_CH0_DIV1 Value */ 298 #define MXC_S_MCR_ADCCFG2_CH0_DIV1 (MXC_V_MCR_ADCCFG2_CH0_DIV1 << MXC_F_MCR_ADCCFG2_CH0_POS) /**< ADCCFG2_CH0_DIV1 Setting */ 299 #define MXC_V_MCR_ADCCFG2_CH0_DIV2_5K ((uint32_t)0x1UL) /**< ADCCFG2_CH0_DIV2_5K Value */ 300 #define MXC_S_MCR_ADCCFG2_CH0_DIV2_5K (MXC_V_MCR_ADCCFG2_CH0_DIV2_5K << MXC_F_MCR_ADCCFG2_CH0_POS) /**< ADCCFG2_CH0_DIV2_5K Setting */ 301 #define MXC_V_MCR_ADCCFG2_CH0_DIV2_50K ((uint32_t)0x2UL) /**< ADCCFG2_CH0_DIV2_50K Value */ 302 #define MXC_S_MCR_ADCCFG2_CH0_DIV2_50K (MXC_V_MCR_ADCCFG2_CH0_DIV2_50K << MXC_F_MCR_ADCCFG2_CH0_POS) /**< ADCCFG2_CH0_DIV2_50K Setting */ 303 304 #define MXC_F_MCR_ADCCFG2_CH1_POS 2 /**< ADCCFG2_CH1 Position */ 305 #define MXC_F_MCR_ADCCFG2_CH1 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH1_POS)) /**< ADCCFG2_CH1 Mask */ 306 307 #define MXC_F_MCR_ADCCFG2_CH2_POS 4 /**< ADCCFG2_CH2 Position */ 308 #define MXC_F_MCR_ADCCFG2_CH2 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH2_POS)) /**< ADCCFG2_CH2 Mask */ 309 310 #define MXC_F_MCR_ADCCFG2_CH3_POS 6 /**< ADCCFG2_CH3 Position */ 311 #define MXC_F_MCR_ADCCFG2_CH3 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH3_POS)) /**< ADCCFG2_CH3 Mask */ 312 313 #define MXC_F_MCR_ADCCFG2_CH4_POS 8 /**< ADCCFG2_CH4 Position */ 314 #define MXC_F_MCR_ADCCFG2_CH4 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH4_POS)) /**< ADCCFG2_CH4 Mask */ 315 316 #define MXC_F_MCR_ADCCFG2_CH5_POS 10 /**< ADCCFG2_CH5 Position */ 317 #define MXC_F_MCR_ADCCFG2_CH5 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH5_POS)) /**< ADCCFG2_CH5 Mask */ 318 319 #define MXC_F_MCR_ADCCFG2_CH6_POS 12 /**< ADCCFG2_CH6 Position */ 320 #define MXC_F_MCR_ADCCFG2_CH6 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH6_POS)) /**< ADCCFG2_CH6 Mask */ 321 322 #define MXC_F_MCR_ADCCFG2_CH7_POS 14 /**< ADCCFG2_CH7 Position */ 323 #define MXC_F_MCR_ADCCFG2_CH7 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH7_POS)) /**< ADCCFG2_CH7 Mask */ 324 325 /**@} end of group MCR_ADCCFG2_Register */ 326 327 /** 328 * @ingroup mcr_registers 329 * @defgroup MCR_LDOCTRL MCR_LDOCTRL 330 * @brief LDO Control 331 * @{ 332 */ 333 #define MXC_F_MCR_LDOCTRL_0P9EN_POS 0 /**< LDOCTRL_0P9EN Position */ 334 #define MXC_F_MCR_LDOCTRL_0P9EN ((uint32_t)(0x1UL << MXC_F_MCR_LDOCTRL_0P9EN_POS)) /**< LDOCTRL_0P9EN Mask */ 335 336 #define MXC_F_MCR_LDOCTRL_2P5EN_POS 1 /**< LDOCTRL_2P5EN Position */ 337 #define MXC_F_MCR_LDOCTRL_2P5EN ((uint32_t)(0x1UL << MXC_F_MCR_LDOCTRL_2P5EN_POS)) /**< LDOCTRL_2P5EN Mask */ 338 339 /**@} end of group MCR_LDOCTRL_Register */ 340 341 #ifdef __cplusplus 342 } 343 #endif 344 345 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_MCR_REGS_H_ 346
