1 /** 2 * @file gcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_GCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_GCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gcr 67 * @defgroup gcr_registers GCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 69 * @details Global Control Registers. 70 */ 71 72 /** 73 * @ingroup gcr_registers 74 * Structure type to access the GCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t sysctrl; /**< <tt>\b 0x00:</tt> GCR SYSCTRL Register */ 78 __IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */ 79 __IO uint32_t clkctrl; /**< <tt>\b 0x08:</tt> GCR CLKCTRL Register */ 80 __IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */ 81 __IO uint32_t ipll_ctrl; /**< <tt>\b 0x10:</tt> GCR IPLL_CTRL Register */ 82 __R uint32_t rsv_0x14; 83 __IO uint32_t pclkdiv; /**< <tt>\b 0x18:</tt> GCR PCLKDIV Register */ 84 __R uint32_t rsv_0x1c_0x23[2]; 85 __IO uint32_t pclkdis0; /**< <tt>\b 0x24:</tt> GCR PCLKDIS0 Register */ 86 __IO uint32_t memctrl; /**< <tt>\b 0x28:</tt> GCR MEMCTRL Register */ 87 __IO uint32_t memz; /**< <tt>\b 0x2C:</tt> GCR MEMZ Register */ 88 __R uint32_t rsv_0x30_0x3f[4]; 89 __IO uint32_t sysst; /**< <tt>\b 0x40:</tt> GCR SYSST Register */ 90 __IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */ 91 __IO uint32_t pclkdis1; /**< <tt>\b 0x48:</tt> GCR PCLKDIS1 Register */ 92 __IO uint32_t eventen; /**< <tt>\b 0x4C:</tt> GCR EVENTEN Register */ 93 __I uint32_t revision; /**< <tt>\b 0x50:</tt> GCR REVISION Register */ 94 __IO uint32_t sysie; /**< <tt>\b 0x54:</tt> GCR SYSIE Register */ 95 __R uint32_t rsv_0x58_0x63[3]; 96 __IO uint32_t eccerr; /**< <tt>\b 0x64:</tt> GCR ECCERR Register */ 97 __IO uint32_t eccced; /**< <tt>\b 0x68:</tt> GCR ECCCED Register */ 98 __IO uint32_t eccie; /**< <tt>\b 0x6C:</tt> GCR ECCIE Register */ 99 __IO uint32_t eccaddr; /**< <tt>\b 0x70:</tt> GCR ECCADDR Register */ 100 __R uint32_t rsv_0x74_0x7f[3]; 101 __IO uint32_t gpr0; /**< <tt>\b 0x80:</tt> GCR GPR0 Register */ 102 } mxc_gcr_regs_t; 103 104 /* Register offsets for module GCR */ 105 /** 106 * @ingroup gcr_registers 107 * @defgroup GCR_Register_Offsets Register Offsets 108 * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. 109 * @{ 110 */ 111 #define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */ 112 #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */ 113 #define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */ 114 #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */ 115 #define MXC_R_GCR_IPLL_CTRL ((uint32_t)0x00000010UL) /**< Offset from GCR Base Address: <tt> 0x0010</tt> */ 116 #define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */ 117 #define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */ 118 #define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */ 119 #define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */ 120 #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */ 121 #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */ 122 #define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */ 123 #define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */ 124 #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */ 125 #define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */ 126 #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: <tt> 0x0064</tt> */ 127 #define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: <tt> 0x0068</tt> */ 128 #define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: <tt> 0x006C</tt> */ 129 #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: <tt> 0x0070</tt> */ 130 #define MXC_R_GCR_GPR0 ((uint32_t)0x00000080UL) /**< Offset from GCR Base Address: <tt> 0x0080</tt> */ 131 /**@} end of group gcr_registers */ 132 133 /** 134 * @ingroup gcr_registers 135 * @defgroup GCR_SYSCTRL GCR_SYSCTRL 136 * @brief System Control. 137 * @{ 138 */ 139 #define MXC_F_GCR_SYSCTRL_BSTAPEN_POS 0 /**< SYSCTRL_BSTAPEN Position */ 140 #define MXC_F_GCR_SYSCTRL_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_BSTAPEN_POS)) /**< SYSCTRL_BSTAPEN Mask */ 141 142 #define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS 4 /**< SYSCTRL_FLASH_PAGE_FLIP Position */ 143 #define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS)) /**< SYSCTRL_FLASH_PAGE_FLIP Mask */ 144 145 #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS 6 /**< SYSCTRL_ICC0_FLUSH Position */ 146 #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS)) /**< SYSCTRL_ICC0_FLUSH Mask */ 147 148 #define MXC_F_GCR_SYSCTRL_ROMDONE_POS 12 /**< SYSCTRL_ROMDONE Position */ 149 #define MXC_F_GCR_SYSCTRL_ROMDONE ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ROMDONE_POS)) /**< SYSCTRL_ROMDONE Mask */ 150 151 #define MXC_F_GCR_SYSCTRL_CCHK_POS 13 /**< SYSCTRL_CCHK Position */ 152 #define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */ 153 154 #define MXC_F_GCR_SYSCTRL_SWD_DIS_POS 14 /**< SYSCTRL_SWD_DIS Position */ 155 #define MXC_F_GCR_SYSCTRL_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS)) /**< SYSCTRL_SWD_DIS Mask */ 156 157 #define MXC_F_GCR_SYSCTRL_CHKRES_POS 15 /**< SYSCTRL_CHKRES Position */ 158 #define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */ 159 160 #define MXC_F_GCR_SYSCTRL_OVR_POS 16 /**< SYSCTRL_OVR Position */ 161 #define MXC_F_GCR_SYSCTRL_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_OVR_POS)) /**< SYSCTRL_OVR Mask */ 162 #define MXC_V_GCR_SYSCTRL_OVR_V0_9 ((uint32_t)0x0UL) /**< SYSCTRL_OVR_V0_9 Value */ 163 #define MXC_S_GCR_SYSCTRL_OVR_V0_9 (MXC_V_GCR_SYSCTRL_OVR_V0_9 << MXC_F_GCR_SYSCTRL_OVR_POS) /**< SYSCTRL_OVR_V0_9 Setting */ 164 #define MXC_V_GCR_SYSCTRL_OVR_V1_0 ((uint32_t)0x1UL) /**< SYSCTRL_OVR_V1_0 Value */ 165 #define MXC_S_GCR_SYSCTRL_OVR_V1_0 (MXC_V_GCR_SYSCTRL_OVR_V1_0 << MXC_F_GCR_SYSCTRL_OVR_POS) /**< SYSCTRL_OVR_V1_0 Setting */ 166 #define MXC_V_GCR_SYSCTRL_OVR_V1_1 ((uint32_t)0x2UL) /**< SYSCTRL_OVR_V1_1 Value */ 167 #define MXC_S_GCR_SYSCTRL_OVR_V1_1 (MXC_V_GCR_SYSCTRL_OVR_V1_1 << MXC_F_GCR_SYSCTRL_OVR_POS) /**< SYSCTRL_OVR_V1_1 Setting */ 168 169 /**@} end of group GCR_SYSCTRL_Register */ 170 171 /** 172 * @ingroup gcr_registers 173 * @defgroup GCR_RST0 GCR_RST0 174 * @brief Reset. 175 * @{ 176 */ 177 #define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ 178 #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ 179 180 #define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ 181 #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ 182 183 #define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ 184 #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ 185 186 #define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */ 187 #define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */ 188 189 #define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */ 190 #define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */ 191 192 #define MXC_F_GCR_RST0_TMR1_POS 6 /**< RST0_TMR1 Position */ 193 #define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */ 194 195 #define MXC_F_GCR_RST0_TMR2_POS 7 /**< RST0_TMR2 Position */ 196 #define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */ 197 198 #define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */ 199 #define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */ 200 201 #define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ 202 #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ 203 204 #define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ 205 #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ 206 207 #define MXC_F_GCR_RST0_SPI1_POS 13 /**< RST0_SPI1 Position */ 208 #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ 209 210 #define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ 211 #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ 212 213 #define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ 214 #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ 215 216 #define MXC_F_GCR_RST0_SMPHR_POS 22 /**< RST0_SMPHR Position */ 217 #define MXC_F_GCR_RST0_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SMPHR_POS)) /**< RST0_SMPHR Mask */ 218 219 #define MXC_F_GCR_RST0_USB_POS 23 /**< RST0_USB Position */ 220 #define MXC_F_GCR_RST0_USB ((uint32_t)(0x1UL << MXC_F_GCR_RST0_USB_POS)) /**< RST0_USB Mask */ 221 222 #define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */ 223 #define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */ 224 225 #define MXC_F_GCR_RST0_CNN_POS 25 /**< RST0_CNN Position */ 226 #define MXC_F_GCR_RST0_CNN ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CNN_POS)) /**< RST0_CNN Mask */ 227 228 #define MXC_F_GCR_RST0_ADC_POS 26 /**< RST0_ADC Position */ 229 #define MXC_F_GCR_RST0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_ADC_POS)) /**< RST0_ADC Mask */ 230 231 #define MXC_F_GCR_RST0_UART2_POS 28 /**< RST0_UART2 Position */ 232 #define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */ 233 234 #define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ 235 #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ 236 237 #define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ 238 #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ 239 240 #define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */ 241 #define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */ 242 243 /**@} end of group GCR_RST0_Register */ 244 245 /** 246 * @ingroup gcr_registers 247 * @defgroup GCR_CLKCTRL GCR_CLKCTRL 248 * @brief Clock Control. 249 * @{ 250 */ 251 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ 252 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ 253 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ 254 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */ 255 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */ 256 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */ 257 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */ 258 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */ 259 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */ 260 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */ 261 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */ 262 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */ 263 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */ 264 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */ 265 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */ 266 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */ 267 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */ 268 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */ 269 270 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ 271 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ 272 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_SEL_ISO Value */ 273 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ISO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ISO Setting */ 274 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPLL ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_SEL_IPLL Value */ 275 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPLL (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPLL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPLL Setting */ 276 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EBO ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_EBO Value */ 277 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EBO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EBO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_EBO Setting */ 278 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ 279 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */ 280 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ 281 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ 282 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */ 283 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ 284 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */ 285 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */ 286 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Value */ 287 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Setting */ 288 289 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ 290 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ 291 292 #define MXC_F_GCR_CLKCTRL_EBO_EN_POS 16 /**< CLKCTRL_EBO_EN Position */ 293 #define MXC_F_GCR_CLKCTRL_EBO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_EBO_EN_POS)) /**< CLKCTRL_EBO_EN Mask */ 294 295 #define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ 296 #define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ 297 298 #define MXC_F_GCR_CLKCTRL_ISO_EN_POS 18 /**< CLKCTRL_ISO_EN Position */ 299 #define MXC_F_GCR_CLKCTRL_ISO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_EN_POS)) /**< CLKCTRL_ISO_EN Mask */ 300 301 #define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ 302 #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ 303 304 #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ 305 #define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */ 306 307 #define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 /**< CLKCTRL_IBRO_VS Position */ 308 #define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */ 309 310 #define MXC_F_GCR_CLKCTRL_EBO_RDY_POS 24 /**< CLKCTRL_EBO_RDY Position */ 311 #define MXC_F_GCR_CLKCTRL_EBO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_EBO_RDY_POS)) /**< CLKCTRL_EBO_RDY Mask */ 312 313 #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ 314 #define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ 315 316 #define MXC_F_GCR_CLKCTRL_ISO_RDY_POS 26 /**< CLKCTRL_ISO_RDY Position */ 317 #define MXC_F_GCR_CLKCTRL_ISO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_RDY_POS)) /**< CLKCTRL_ISO_RDY Mask */ 318 319 #define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 /**< CLKCTRL_IPO_RDY Position */ 320 #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ 321 322 #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ 323 #define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */ 324 325 #define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */ 326 #define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */ 327 328 /**@} end of group GCR_CLKCTRL_Register */ 329 330 /** 331 * @ingroup gcr_registers 332 * @defgroup GCR_PM GCR_PM 333 * @brief Power Management. 334 * @{ 335 */ 336 #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ 337 #define MXC_F_GCR_PM_MODE ((uint32_t)(0xFUL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ 338 #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ 339 #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ 340 #define MXC_V_GCR_PM_MODE_SLEEP ((uint32_t)0x1UL) /**< PM_MODE_SLEEP Value */ 341 #define MXC_S_GCR_PM_MODE_SLEEP (MXC_V_GCR_PM_MODE_SLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SLEEP Setting */ 342 #define MXC_V_GCR_PM_MODE_STANDBY ((uint32_t)0x2UL) /**< PM_MODE_STANDBY Value */ 343 #define MXC_S_GCR_PM_MODE_STANDBY (MXC_V_GCR_PM_MODE_STANDBY << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_STANDBY Setting */ 344 #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ 345 #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ 346 #define MXC_V_GCR_PM_MODE_LPM ((uint32_t)0x8UL) /**< PM_MODE_LPM Value */ 347 #define MXC_S_GCR_PM_MODE_LPM (MXC_V_GCR_PM_MODE_LPM << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_LPM Setting */ 348 #define MXC_V_GCR_PM_MODE_UPM ((uint32_t)0x9UL) /**< PM_MODE_UPM Value */ 349 #define MXC_S_GCR_PM_MODE_UPM (MXC_V_GCR_PM_MODE_UPM << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_UPM Setting */ 350 #define MXC_V_GCR_PM_MODE_POWERDOWN ((uint32_t)0xAUL) /**< PM_MODE_POWERDOWN Value */ 351 #define MXC_S_GCR_PM_MODE_POWERDOWN (MXC_V_GCR_PM_MODE_POWERDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_POWERDOWN Setting */ 352 353 #define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */ 354 #define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */ 355 356 #define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */ 357 #define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */ 358 359 #define MXC_F_GCR_PM_USB_WE_POS 6 /**< PM_USB_WE Position */ 360 #define MXC_F_GCR_PM_USB_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_USB_WE_POS)) /**< PM_USB_WE Mask */ 361 362 #define MXC_F_GCR_PM_WUT_WE_POS 7 /**< PM_WUT_WE Position */ 363 #define MXC_F_GCR_PM_WUT_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_WUT_WE_POS)) /**< PM_WUT_WE Mask */ 364 365 #define MXC_F_GCR_PM_AINCOMP_WE_POS 9 /**< PM_AINCOMP_WE Position */ 366 #define MXC_F_GCR_PM_AINCOMP_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_AINCOMP_WE_POS)) /**< PM_AINCOMP_WE Mask */ 367 368 #define MXC_F_GCR_PM_ISO_PD_POS 15 /**< PM_ISO_PD Position */ 369 #define MXC_F_GCR_PM_ISO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ISO_PD_POS)) /**< PM_ISO_PD Mask */ 370 371 #define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */ 372 #define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */ 373 374 #define MXC_F_GCR_PM_IBRO_PD_POS 17 /**< PM_IBRO_PD Position */ 375 #define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */ 376 377 #define MXC_F_GCR_PM_EBO_BP_POS 20 /**< PM_EBO_BP Position */ 378 #define MXC_F_GCR_PM_EBO_BP ((uint32_t)(0x1UL << MXC_F_GCR_PM_EBO_BP_POS)) /**< PM_EBO_BP Mask */ 379 380 /**@} end of group GCR_PM_Register */ 381 382 /** 383 * @ingroup gcr_registers 384 * @defgroup GCR_IPLL_CTRL GCR_IPLL_CTRL 385 * @brief IPLL Control 386 * @{ 387 */ 388 #define MXC_F_GCR_IPLL_CTRL_EN_POS 0 /**< IPLL_CTRL_EN Position */ 389 #define MXC_F_GCR_IPLL_CTRL_EN ((uint32_t)(0x1UL << MXC_F_GCR_IPLL_CTRL_EN_POS)) /**< IPLL_CTRL_EN Mask */ 390 391 #define MXC_F_GCR_IPLL_CTRL_RDY_POS 1 /**< IPLL_CTRL_RDY Position */ 392 #define MXC_F_GCR_IPLL_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_GCR_IPLL_CTRL_RDY_POS)) /**< IPLL_CTRL_RDY Mask */ 393 394 /**@} end of group GCR_IPLL_CTRL_Register */ 395 396 /** 397 * @ingroup gcr_registers 398 * @defgroup GCR_PCLKDIV GCR_PCLKDIV 399 * @brief Peripheral Clock Divider. 400 * @{ 401 */ 402 #define MXC_F_GCR_PCLKDIV_SDIOCLKDIV_POS 7 /**< PCLKDIV_SDIOCLKDIV Position */ 403 #define MXC_F_GCR_PCLKDIV_SDIOCLKDIV ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_SDIOCLKDIV_POS)) /**< PCLKDIV_SDIOCLKDIV Mask */ 404 405 #define MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS 14 /**< PCLKDIV_CNNCLKDIV Position */ 406 #define MXC_F_GCR_PCLKDIV_CNNCLKDIV ((uint32_t)(0x7UL << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS)) /**< PCLKDIV_CNNCLKDIV Mask */ 407 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV2 ((uint32_t)0x0UL) /**< PCLKDIV_CNNCLKDIV_DIV2 Value */ 408 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV2 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV2 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV2 Setting */ 409 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV4 ((uint32_t)0x1UL) /**< PCLKDIV_CNNCLKDIV_DIV4 Value */ 410 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV4 Setting */ 411 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV8 ((uint32_t)0x2UL) /**< PCLKDIV_CNNCLKDIV_DIV8 Value */ 412 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV8 Setting */ 413 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV16 ((uint32_t)0x3UL) /**< PCLKDIV_CNNCLKDIV_DIV16 Value */ 414 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV16 Setting */ 415 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV1 ((uint32_t)0x4UL) /**< PCLKDIV_CNNCLKDIV_DIV1 Value */ 416 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV1 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV1 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV1 Setting */ 417 418 #define MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS 17 /**< PCLKDIV_CNNCLKSEL Position */ 419 #define MXC_F_GCR_PCLKDIV_CNNCLKSEL ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS)) /**< PCLKDIV_CNNCLKSEL Mask */ 420 #define MXC_V_GCR_PCLKDIV_CNNCLKSEL_PCLK ((uint32_t)0x0UL) /**< PCLKDIV_CNNCLKSEL_PCLK Value */ 421 #define MXC_S_GCR_PCLKDIV_CNNCLKSEL_PCLK (MXC_V_GCR_PCLKDIV_CNNCLKSEL_PCLK << MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS) /**< PCLKDIV_CNNCLKSEL_PCLK Setting */ 422 #define MXC_V_GCR_PCLKDIV_CNNCLKSEL_ISO ((uint32_t)0x1UL) /**< PCLKDIV_CNNCLKSEL_ISO Value */ 423 #define MXC_S_GCR_PCLKDIV_CNNCLKSEL_ISO (MXC_V_GCR_PCLKDIV_CNNCLKSEL_ISO << MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS) /**< PCLKDIV_CNNCLKSEL_ISO Setting */ 424 #define MXC_V_GCR_PCLKDIV_CNNCLKSEL_IPLL ((uint32_t)0x3UL) /**< PCLKDIV_CNNCLKSEL_IPLL Value */ 425 #define MXC_S_GCR_PCLKDIV_CNNCLKSEL_IPLL (MXC_V_GCR_PCLKDIV_CNNCLKSEL_IPLL << MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS) /**< PCLKDIV_CNNCLKSEL_IPLL Setting */ 426 427 /**@} end of group GCR_PCLKDIV_Register */ 428 429 /** 430 * @ingroup gcr_registers 431 * @defgroup GCR_PCLKDIS0 GCR_PCLKDIS0 432 * @brief Peripheral Clock Disable. 433 * @{ 434 */ 435 #define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */ 436 #define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */ 437 438 #define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */ 439 #define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */ 440 441 #define MXC_F_GCR_PCLKDIS0_USB_POS 3 /**< PCLKDIS0_USB Position */ 442 #define MXC_F_GCR_PCLKDIS0_USB ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_USB_POS)) /**< PCLKDIS0_USB Mask */ 443 444 #define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */ 445 #define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */ 446 447 #define MXC_F_GCR_PCLKDIS0_SPI1_POS 6 /**< PCLKDIS0_SPI1 Position */ 448 #define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */ 449 450 #define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */ 451 #define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */ 452 453 #define MXC_F_GCR_PCLKDIS0_UART1_POS 10 /**< PCLKDIS0_UART1 Position */ 454 #define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) /**< PCLKDIS0_UART1 Mask */ 455 456 #define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */ 457 #define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */ 458 459 #define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ 460 #define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ 461 462 #define MXC_F_GCR_PCLKDIS0_TMR1_POS 16 /**< PCLKDIS0_TMR1 Position */ 463 #define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */ 464 465 #define MXC_F_GCR_PCLKDIS0_TMR2_POS 17 /**< PCLKDIS0_TMR2 Position */ 466 #define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */ 467 468 #define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */ 469 #define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */ 470 471 #define MXC_F_GCR_PCLKDIS0_ADC_POS 23 /**< PCLKDIS0_ADC Position */ 472 #define MXC_F_GCR_PCLKDIS0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_ADC_POS)) /**< PCLKDIS0_ADC Mask */ 473 474 #define MXC_F_GCR_PCLKDIS0_CNN_POS 25 /**< PCLKDIS0_CNN Position */ 475 #define MXC_F_GCR_PCLKDIS0_CNN ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_CNN_POS)) /**< PCLKDIS0_CNN Mask */ 476 477 #define MXC_F_GCR_PCLKDIS0_I2C1_POS 28 /**< PCLKDIS0_I2C1 Position */ 478 #define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */ 479 480 #define MXC_F_GCR_PCLKDIS0_PT_POS 29 /**< PCLKDIS0_PT Position */ 481 #define MXC_F_GCR_PCLKDIS0_PT ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_PT_POS)) /**< PCLKDIS0_PT Mask */ 482 483 /**@} end of group GCR_PCLKDIS0_Register */ 484 485 /** 486 * @ingroup gcr_registers 487 * @defgroup GCR_MEMCTRL GCR_MEMCTRL 488 * @brief Memory Clock Control Register. 489 * @{ 490 */ 491 #define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ 492 #define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ 493 494 #define MXC_F_GCR_MEMCTRL_SYSRAM0ECC_POS 16 /**< MEMCTRL_SYSRAM0ECC Position */ 495 #define MXC_F_GCR_MEMCTRL_SYSRAM0ECC ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_SYSRAM0ECC_POS)) /**< MEMCTRL_SYSRAM0ECC Mask */ 496 497 /**@} end of group GCR_MEMCTRL_Register */ 498 499 /** 500 * @ingroup gcr_registers 501 * @defgroup GCR_MEMZ GCR_MEMZ 502 * @brief Memory Zeroize Control. 503 * @{ 504 */ 505 #define MXC_F_GCR_MEMZ_RAM0_POS 0 /**< MEMZ_RAM0 Position */ 506 #define MXC_F_GCR_MEMZ_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS)) /**< MEMZ_RAM0 Mask */ 507 508 #define MXC_F_GCR_MEMZ_RAM1_POS 1 /**< MEMZ_RAM1 Position */ 509 #define MXC_F_GCR_MEMZ_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS)) /**< MEMZ_RAM1 Mask */ 510 511 #define MXC_F_GCR_MEMZ_RAM2_POS 2 /**< MEMZ_RAM2 Position */ 512 #define MXC_F_GCR_MEMZ_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS)) /**< MEMZ_RAM2 Mask */ 513 514 #define MXC_F_GCR_MEMZ_RAM3_POS 3 /**< MEMZ_RAM3 Position */ 515 #define MXC_F_GCR_MEMZ_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS)) /**< MEMZ_RAM3 Mask */ 516 517 #define MXC_F_GCR_MEMZ_RAM4_POS 4 /**< MEMZ_RAM4 Position */ 518 #define MXC_F_GCR_MEMZ_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM4_POS)) /**< MEMZ_RAM4 Mask */ 519 520 #define MXC_F_GCR_MEMZ_RAM5_POS 5 /**< MEMZ_RAM5 Position */ 521 #define MXC_F_GCR_MEMZ_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM5_POS)) /**< MEMZ_RAM5 Mask */ 522 523 #define MXC_F_GCR_MEMZ_RAM6_POS 6 /**< MEMZ_RAM6 Position */ 524 #define MXC_F_GCR_MEMZ_RAM6 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM6_POS)) /**< MEMZ_RAM6 Mask */ 525 526 #define MXC_F_GCR_MEMZ_RAM7_POS 7 /**< MEMZ_RAM7 Position */ 527 #define MXC_F_GCR_MEMZ_RAM7 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM7_POS)) /**< MEMZ_RAM7 Mask */ 528 529 #define MXC_F_GCR_MEMZ_RAM0ECC_POS 8 /**< MEMZ_RAM0ECC Position */ 530 #define MXC_F_GCR_MEMZ_RAM0ECC ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0ECC_POS)) /**< MEMZ_RAM0ECC Mask */ 531 532 #define MXC_F_GCR_MEMZ_ICC0_POS 9 /**< MEMZ_ICC0 Position */ 533 #define MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) /**< MEMZ_ICC0 Mask */ 534 535 #define MXC_F_GCR_MEMZ_ICC1_POS 10 /**< MEMZ_ICC1 Position */ 536 #define MXC_F_GCR_MEMZ_ICC1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC1_POS)) /**< MEMZ_ICC1 Mask */ 537 538 #define MXC_F_GCR_MEMZ_USBFIFO_POS 11 /**< MEMZ_USBFIFO Position */ 539 #define MXC_F_GCR_MEMZ_USBFIFO ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_USBFIFO_POS)) /**< MEMZ_USBFIFO Mask */ 540 541 /**@} end of group GCR_MEMZ_Register */ 542 543 /** 544 * @ingroup gcr_registers 545 * @defgroup GCR_SYSST GCR_SYSST 546 * @brief System Status Register. 547 * @{ 548 */ 549 #define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ 550 #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ 551 552 /**@} end of group GCR_SYSST_Register */ 553 554 /** 555 * @ingroup gcr_registers 556 * @defgroup GCR_RST1 GCR_RST1 557 * @brief Reset 1. 558 * @{ 559 */ 560 #define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ 561 #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ 562 563 #define MXC_F_GCR_RST1_PT_POS 1 /**< RST1_PT Position */ 564 #define MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS)) /**< RST1_PT Mask */ 565 566 #define MXC_F_GCR_RST1_SDHC_POS 6 /**< RST1_SDHC Position */ 567 #define MXC_F_GCR_RST1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SDHC_POS)) /**< RST1_SDHC Mask */ 568 569 #define MXC_F_GCR_RST1_OWM_POS 7 /**< RST1_OWM Position */ 570 #define MXC_F_GCR_RST1_OWM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWM_POS)) /**< RST1_OWM Mask */ 571 572 #define MXC_F_GCR_RST1_CRC_POS 9 /**< RST1_CRC Position */ 573 #define MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS)) /**< RST1_CRC Mask */ 574 575 #define MXC_F_GCR_RST1_AES_POS 10 /**< RST1_AES Position */ 576 #define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */ 577 578 #define MXC_F_GCR_RST1_SPI0_POS 11 /**< RST1_SPI0 Position */ 579 #define MXC_F_GCR_RST1_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI0_POS)) /**< RST1_SPI0 Mask */ 580 581 #define MXC_F_GCR_RST1_CSI2PHY_POS 14 /**< RST1_CSI2PHY Position */ 582 #define MXC_F_GCR_RST1_CSI2PHY ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CSI2PHY_POS)) /**< RST1_CSI2PHY Mask */ 583 584 #define MXC_F_GCR_RST1_SMPHR_POS 16 /**< RST1_SMPHR Position */ 585 #define MXC_F_GCR_RST1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SMPHR_POS)) /**< RST1_SMPHR Mask */ 586 587 #define MXC_F_GCR_RST1_I2S_POS 19 /**< RST1_I2S Position */ 588 #define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) /**< RST1_I2S Mask */ 589 590 #define MXC_F_GCR_RST1_I2C2_POS 20 /**< RST1_I2C2 Position */ 591 #define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) /**< RST1_I2C2 Mask */ 592 593 #define MXC_F_GCR_RST1_DVS_POS 24 /**< RST1_DVS Position */ 594 #define MXC_F_GCR_RST1_DVS ((uint32_t)(0x1UL << MXC_F_GCR_RST1_DVS_POS)) /**< RST1_DVS Mask */ 595 596 #define MXC_F_GCR_RST1_SIMO_POS 25 /**< RST1_SIMO Position */ 597 #define MXC_F_GCR_RST1_SIMO ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SIMO_POS)) /**< RST1_SIMO Mask */ 598 599 #define MXC_F_GCR_RST1_PCIF_POS 26 /**< RST1_PCIF Position */ 600 #define MXC_F_GCR_RST1_PCIF ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PCIF_POS)) /**< RST1_PCIF Mask */ 601 602 #define MXC_F_GCR_RST1_CSI2_POS 27 /**< RST1_CSI2 Position */ 603 #define MXC_F_GCR_RST1_CSI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CSI2_POS)) /**< RST1_CSI2 Mask */ 604 605 #define MXC_F_GCR_RST1_CPU1_POS 31 /**< RST1_CPU1 Position */ 606 #define MXC_F_GCR_RST1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CPU1_POS)) /**< RST1_CPU1 Mask */ 607 608 /**@} end of group GCR_RST1_Register */ 609 610 /** 611 * @ingroup gcr_registers 612 * @defgroup GCR_PCLKDIS1 GCR_PCLKDIS1 613 * @brief Peripheral Clock Disable. 614 * @{ 615 */ 616 #define MXC_F_GCR_PCLKDIS1_UART2_POS 1 /**< PCLKDIS1_UART2 Position */ 617 #define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) /**< PCLKDIS1_UART2 Mask */ 618 619 #define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ 620 #define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ 621 622 #define MXC_F_GCR_PCLKDIS1_SMPHR_POS 9 /**< PCLKDIS1_SMPHR Position */ 623 #define MXC_F_GCR_PCLKDIS1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SMPHR_POS)) /**< PCLKDIS1_SMPHR Mask */ 624 625 #define MXC_F_GCR_PCLKDIS1_SDHC_POS 10 /**< PCLKDIS1_SDHC Position */ 626 #define MXC_F_GCR_PCLKDIS1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SDHC_POS)) /**< PCLKDIS1_SDHC Mask */ 627 628 #define MXC_F_GCR_PCLKDIS1_OWM_POS 13 /**< PCLKDIS1_OWM Position */ 629 #define MXC_F_GCR_PCLKDIS1_OWM ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_OWM_POS)) /**< PCLKDIS1_OWM Mask */ 630 631 #define MXC_F_GCR_PCLKDIS1_CRC_POS 14 /**< PCLKDIS1_CRC Position */ 632 #define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) /**< PCLKDIS1_CRC Mask */ 633 634 #define MXC_F_GCR_PCLKDIS1_AES_POS 15 /**< PCLKDIS1_AES Position */ 635 #define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */ 636 637 #define MXC_F_GCR_PCLKDIS1_SPI0_POS 16 /**< PCLKDIS1_SPI0 Position */ 638 #define MXC_F_GCR_PCLKDIS1_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI0_POS)) /**< PCLKDIS1_SPI0 Mask */ 639 640 #define MXC_F_GCR_PCLKDIS1_PCIF_POS 18 /**< PCLKDIS1_PCIF Position */ 641 #define MXC_F_GCR_PCLKDIS1_PCIF ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_PCIF_POS)) /**< PCLKDIS1_PCIF Mask */ 642 643 #define MXC_F_GCR_PCLKDIS1_I2S_POS 23 /**< PCLKDIS1_I2S Position */ 644 #define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) /**< PCLKDIS1_I2S Mask */ 645 646 #define MXC_F_GCR_PCLKDIS1_I2C2_POS 24 /**< PCLKDIS1_I2C2 Position */ 647 #define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) /**< PCLKDIS1_I2C2 Mask */ 648 649 #define MXC_F_GCR_PCLKDIS1_WDT0_POS 27 /**< PCLKDIS1_WDT0 Position */ 650 #define MXC_F_GCR_PCLKDIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT0_POS)) /**< PCLKDIS1_WDT0 Mask */ 651 652 #define MXC_F_GCR_PCLKDIS1_CSI2_POS 30 /**< PCLKDIS1_CSI2 Position */ 653 #define MXC_F_GCR_PCLKDIS1_CSI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CSI2_POS)) /**< PCLKDIS1_CSI2 Mask */ 654 655 #define MXC_F_GCR_PCLKDIS1_CPU1_POS 31 /**< PCLKDIS1_CPU1 Position */ 656 #define MXC_F_GCR_PCLKDIS1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CPU1_POS)) /**< PCLKDIS1_CPU1 Mask */ 657 658 /**@} end of group GCR_PCLKDIS1_Register */ 659 660 /** 661 * @ingroup gcr_registers 662 * @defgroup GCR_EVENTEN GCR_EVENTEN 663 * @brief Event Enable Register. 664 * @{ 665 */ 666 #define MXC_F_GCR_EVENTEN_DMA_POS 0 /**< EVENTEN_DMA Position */ 667 #define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */ 668 669 #define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */ 670 #define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */ 671 672 /**@} end of group GCR_EVENTEN_Register */ 673 674 /** 675 * @ingroup gcr_registers 676 * @defgroup GCR_REVISION GCR_REVISION 677 * @brief Revision Register. 678 * @{ 679 */ 680 #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ 681 #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ 682 683 /**@} end of group GCR_REVISION_Register */ 684 685 /** 686 * @ingroup gcr_registers 687 * @defgroup GCR_SYSIE GCR_SYSIE 688 * @brief System Status Interrupt Enable Register. 689 * @{ 690 */ 691 #define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0 /**< SYSIE_ICEUNLOCK Position */ 692 #define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) /**< SYSIE_ICEUNLOCK Mask */ 693 694 /**@} end of group GCR_SYSIE_Register */ 695 696 /** 697 * @ingroup gcr_registers 698 * @defgroup GCR_ECCERR GCR_ECCERR 699 * @brief ECC Error Register 700 * @{ 701 */ 702 #define MXC_F_GCR_ECCERR_RAM_POS 0 /**< ECCERR_RAM Position */ 703 #define MXC_F_GCR_ECCERR_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM_POS)) /**< ECCERR_RAM Mask */ 704 705 /**@} end of group GCR_ECCERR_Register */ 706 707 /** 708 * @ingroup gcr_registers 709 * @defgroup GCR_ECCCED GCR_ECCCED 710 * @brief ECC Not Double Error Detect Register 711 * @{ 712 */ 713 #define MXC_F_GCR_ECCCED_RAM_POS 0 /**< ECCCED_RAM Position */ 714 #define MXC_F_GCR_ECCCED_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM_POS)) /**< ECCCED_RAM Mask */ 715 716 /**@} end of group GCR_ECCCED_Register */ 717 718 /** 719 * @ingroup gcr_registers 720 * @defgroup GCR_ECCIE GCR_ECCIE 721 * @brief ECC IRQ Enable Register 722 * @{ 723 */ 724 #define MXC_F_GCR_ECCIE_RAM_POS 0 /**< ECCIE_RAM Position */ 725 #define MXC_F_GCR_ECCIE_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM_POS)) /**< ECCIE_RAM Mask */ 726 727 /**@} end of group GCR_ECCIE_Register */ 728 729 /** 730 * @ingroup gcr_registers 731 * @defgroup GCR_ECCADDR GCR_ECCADDR 732 * @brief ECC Error Address Register 733 * @{ 734 */ 735 #define MXC_F_GCR_ECCADDR_ECCERRAD_POS 0 /**< ECCADDR_ECCERRAD Position */ 736 #define MXC_F_GCR_ECCADDR_ECCERRAD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GCR_ECCADDR_ECCERRAD_POS)) /**< ECCADDR_ECCERRAD Mask */ 737 738 /**@} end of group GCR_ECCADDR_Register */ 739 740 #ifdef __cplusplus 741 } 742 #endif 743 744 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_GCR_REGS_H_ 745
