1 /** 2 * @file gcfr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gcfr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_GCFR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_GCFR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gcfr 67 * @defgroup gcfr_registers GCFR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module. 69 * @details Global Control Function Register. 70 */ 71 72 /** 73 * @ingroup gcfr_registers 74 * Structure type to access the GCFR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t reg0; /**< <tt>\b 0x00:</tt> GCFR REG0 Register */ 78 __IO uint32_t reg1; /**< <tt>\b 0x04:</tt> GCFR REG1 Register */ 79 __IO uint32_t reg2; /**< <tt>\b 0x08:</tt> GCFR REG2 Register */ 80 __IO uint32_t reg3; /**< <tt>\b 0x0C:</tt> GCFR REG3 Register */ 81 } mxc_gcfr_regs_t; 82 83 /* Register offsets for module GCFR */ 84 /** 85 * @ingroup gcfr_registers 86 * @defgroup GCFR_Register_Offsets Register Offsets 87 * @brief GCFR Peripheral Register Offsets from the GCFR Base Peripheral Address. 88 * @{ 89 */ 90 #define MXC_R_GCFR_REG0 ((uint32_t)0x00000000UL) /**< Offset from GCFR Base Address: <tt> 0x0000</tt> */ 91 #define MXC_R_GCFR_REG1 ((uint32_t)0x00000004UL) /**< Offset from GCFR Base Address: <tt> 0x0004</tt> */ 92 #define MXC_R_GCFR_REG2 ((uint32_t)0x00000008UL) /**< Offset from GCFR Base Address: <tt> 0x0008</tt> */ 93 #define MXC_R_GCFR_REG3 ((uint32_t)0x0000000CUL) /**< Offset from GCFR Base Address: <tt> 0x000C</tt> */ 94 /**@} end of group gcfr_registers */ 95 96 /** 97 * @ingroup gcfr_registers 98 * @defgroup GCFR_REG0 GCFR_REG0 99 * @brief Register 0. 100 * @{ 101 */ 102 #define MXC_F_GCFR_REG0_CNNX16_0_PWR_EN_POS 0 /**< REG0_CNNX16_0_PWR_EN Position */ 103 #define MXC_F_GCFR_REG0_CNNX16_0_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_0_PWR_EN_POS)) /**< REG0_CNNX16_0_PWR_EN Mask */ 104 105 #define MXC_F_GCFR_REG0_CNNX16_1_PWR_EN_POS 1 /**< REG0_CNNX16_1_PWR_EN Position */ 106 #define MXC_F_GCFR_REG0_CNNX16_1_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_1_PWR_EN_POS)) /**< REG0_CNNX16_1_PWR_EN Mask */ 107 108 #define MXC_F_GCFR_REG0_CNNX16_2_PWR_EN_POS 2 /**< REG0_CNNX16_2_PWR_EN Position */ 109 #define MXC_F_GCFR_REG0_CNNX16_2_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_2_PWR_EN_POS)) /**< REG0_CNNX16_2_PWR_EN Mask */ 110 111 #define MXC_F_GCFR_REG0_CNNX16_3_PWR_EN_POS 3 /**< REG0_CNNX16_3_PWR_EN Position */ 112 #define MXC_F_GCFR_REG0_CNNX16_3_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_3_PWR_EN_POS)) /**< REG0_CNNX16_3_PWR_EN Mask */ 113 114 /**@} end of group GCFR_REG0_Register */ 115 116 /** 117 * @ingroup gcfr_registers 118 * @defgroup GCFR_REG1 GCFR_REG1 119 * @brief Register 1. 120 * @{ 121 */ 122 #define MXC_F_GCFR_REG1_CNNX16_0_RAM_EN_POS 0 /**< REG1_CNNX16_0_RAM_EN Position */ 123 #define MXC_F_GCFR_REG1_CNNX16_0_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_0_RAM_EN_POS)) /**< REG1_CNNX16_0_RAM_EN Mask */ 124 125 #define MXC_F_GCFR_REG1_CNNX16_1_RAM_EN_POS 1 /**< REG1_CNNX16_1_RAM_EN Position */ 126 #define MXC_F_GCFR_REG1_CNNX16_1_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_1_RAM_EN_POS)) /**< REG1_CNNX16_1_RAM_EN Mask */ 127 128 #define MXC_F_GCFR_REG1_CNNX16_2_RAM_EN_POS 2 /**< REG1_CNNX16_2_RAM_EN Position */ 129 #define MXC_F_GCFR_REG1_CNNX16_2_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_2_RAM_EN_POS)) /**< REG1_CNNX16_2_RAM_EN Mask */ 130 131 #define MXC_F_GCFR_REG1_CNNX16_3_RAM_EN_POS 3 /**< REG1_CNNX16_3_RAM_EN Position */ 132 #define MXC_F_GCFR_REG1_CNNX16_3_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_3_RAM_EN_POS)) /**< REG1_CNNX16_3_RAM_EN Mask */ 133 134 /**@} end of group GCFR_REG1_Register */ 135 136 /** 137 * @ingroup gcfr_registers 138 * @defgroup GCFR_REG2 GCFR_REG2 139 * @brief Register 2. 140 * @{ 141 */ 142 #define MXC_F_GCFR_REG2_CNNX16_0_ISO_POS 0 /**< REG2_CNNX16_0_ISO Position */ 143 #define MXC_F_GCFR_REG2_CNNX16_0_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_0_ISO_POS)) /**< REG2_CNNX16_0_ISO Mask */ 144 145 #define MXC_F_GCFR_REG2_CNNX16_1_ISO_POS 1 /**< REG2_CNNX16_1_ISO Position */ 146 #define MXC_F_GCFR_REG2_CNNX16_1_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_1_ISO_POS)) /**< REG2_CNNX16_1_ISO Mask */ 147 148 #define MXC_F_GCFR_REG2_CNNX16_2_ISO_POS 2 /**< REG2_CNNX16_2_ISO Position */ 149 #define MXC_F_GCFR_REG2_CNNX16_2_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_2_ISO_POS)) /**< REG2_CNNX16_2_ISO Mask */ 150 151 #define MXC_F_GCFR_REG2_CNNX16_3_ISO_POS 3 /**< REG2_CNNX16_3_ISO Position */ 152 #define MXC_F_GCFR_REG2_CNNX16_3_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_3_ISO_POS)) /**< REG2_CNNX16_3_ISO Mask */ 153 154 #define MXC_F_GCFR_REG2_CNNX16_0_DATA_RET_EN_POS 16 /**< REG2_CNNX16_0_DATA_RET_EN Position */ 155 #define MXC_F_GCFR_REG2_CNNX16_0_DATA_RET_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_0_DATA_RET_EN_POS)) /**< REG2_CNNX16_0_DATA_RET_EN Mask */ 156 157 #define MXC_F_GCFR_REG2_CNNX16_1_DATA_RET_EN_POS 17 /**< REG2_CNNX16_1_DATA_RET_EN Position */ 158 #define MXC_F_GCFR_REG2_CNNX16_1_DATA_RET_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_1_DATA_RET_EN_POS)) /**< REG2_CNNX16_1_DATA_RET_EN Mask */ 159 160 #define MXC_F_GCFR_REG2_CNNX16_2_DATA_RET_EN_POS 18 /**< REG2_CNNX16_2_DATA_RET_EN Position */ 161 #define MXC_F_GCFR_REG2_CNNX16_2_DATA_RET_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_2_DATA_RET_EN_POS)) /**< REG2_CNNX16_2_DATA_RET_EN Mask */ 162 163 #define MXC_F_GCFR_REG2_CNNX16_3_DATA_RET_EN_POS 19 /**< REG2_CNNX16_3_DATA_RET_EN Position */ 164 #define MXC_F_GCFR_REG2_CNNX16_3_DATA_RET_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_3_DATA_RET_EN_POS)) /**< REG2_CNNX16_3_DATA_RET_EN Mask */ 165 166 #define MXC_F_GCFR_REG2_CNNX16_0_RAM_DATA_RET_EN_POS 20 /**< REG2_CNNX16_0_RAM_DATA_RET_EN Position */ 167 #define MXC_F_GCFR_REG2_CNNX16_0_RAM_DATA_RET_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_0_RAM_DATA_RET_EN_POS)) /**< REG2_CNNX16_0_RAM_DATA_RET_EN Mask */ 168 169 #define MXC_F_GCFR_REG2_CNNX16_1_RAM_DATA_RET_EN_POS 21 /**< REG2_CNNX16_1_RAM_DATA_RET_EN Position */ 170 #define MXC_F_GCFR_REG2_CNNX16_1_RAM_DATA_RET_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_1_RAM_DATA_RET_EN_POS)) /**< REG2_CNNX16_1_RAM_DATA_RET_EN Mask */ 171 172 #define MXC_F_GCFR_REG2_CNNX16_2_RAM_DATA_RET_EN_POS 22 /**< REG2_CNNX16_2_RAM_DATA_RET_EN Position */ 173 #define MXC_F_GCFR_REG2_CNNX16_2_RAM_DATA_RET_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_2_RAM_DATA_RET_EN_POS)) /**< REG2_CNNX16_2_RAM_DATA_RET_EN Mask */ 174 175 #define MXC_F_GCFR_REG2_CNNX16_3_RAM_DATA_RET_EN_POS 23 /**< REG2_CNNX16_3_RAM_DATA_RET_EN Position */ 176 #define MXC_F_GCFR_REG2_CNNX16_3_RAM_DATA_RET_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_3_RAM_DATA_RET_EN_POS)) /**< REG2_CNNX16_3_RAM_DATA_RET_EN Mask */ 177 178 /**@} end of group GCFR_REG2_Register */ 179 180 /** 181 * @ingroup gcfr_registers 182 * @defgroup GCFR_REG3 GCFR_REG3 183 * @brief Register 3. 184 * @{ 185 */ 186 #define MXC_F_GCFR_REG3_CNNX16_0_RST_POS 0 /**< REG3_CNNX16_0_RST Position */ 187 #define MXC_F_GCFR_REG3_CNNX16_0_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_0_RST_POS)) /**< REG3_CNNX16_0_RST Mask */ 188 189 #define MXC_F_GCFR_REG3_CNNX16_1_RST_POS 1 /**< REG3_CNNX16_1_RST Position */ 190 #define MXC_F_GCFR_REG3_CNNX16_1_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_1_RST_POS)) /**< REG3_CNNX16_1_RST Mask */ 191 192 #define MXC_F_GCFR_REG3_CNNX16_2_RST_POS 2 /**< REG3_CNNX16_2_RST Position */ 193 #define MXC_F_GCFR_REG3_CNNX16_2_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_2_RST_POS)) /**< REG3_CNNX16_2_RST Mask */ 194 195 #define MXC_F_GCFR_REG3_CNNX16_3_RST_POS 3 /**< REG3_CNNX16_3_RST Position */ 196 #define MXC_F_GCFR_REG3_CNNX16_3_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_3_RST_POS)) /**< REG3_CNNX16_3_RST Mask */ 197 198 /**@} end of group GCFR_REG3_Register */ 199 200 #ifdef __cplusplus 201 } 202 #endif 203 204 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_GCFR_REGS_H_ 205
