1 /** 2 * @file flc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup flc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_FLC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_FLC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup flc 67 * @defgroup flc_registers FLC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 69 * @details Flash Memory Control. 70 */ 71 72 /** 73 * @ingroup flc_registers 74 * Structure type to access the FLC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */ 78 __IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */ 79 __IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC CTRL Register */ 80 __R uint32_t rsv_0xc_0x23[6]; 81 __IO uint32_t intr; /**< <tt>\b 0x24:</tt> FLC INTR Register */ 82 __R uint32_t rsv_0x28_0x2f[2]; 83 __IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */ 84 __O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC ACTRL Register */ 85 __R uint32_t rsv_0x44_0x7f[15]; 86 __IO uint32_t welr0; /**< <tt>\b 0x80:</tt> FLC WELR0 Register */ 87 __IO uint32_t rlr0; /**< <tt>\b 0x84:</tt> FLC RLR0 Register */ 88 __IO uint32_t welr1; /**< <tt>\b 0x88:</tt> FLC WELR1 Register */ 89 __IO uint32_t rlr1; /**< <tt>\b 0x8C:</tt> FLC RLR1 Register */ 90 __IO uint32_t welr2; /**< <tt>\b 90:</tt> FLC WELR2 Register */ 91 __IO uint32_t rlr2; /**< <tt>\b 0x94:</tt> FLC RLR2 Register */ 92 __IO uint32_t welr3; /**< <tt>\b 0x98:</tt> FLC WELR3 Register */ 93 __IO uint32_t rlr3; /**< <tt>\b 0x9C:</tt> FLC RLR3 Register */ 94 __IO uint32_t welr4; /**< <tt>\b 0xA0:</tt> FLC WELR4 Register */ 95 __IO uint32_t rlr4; /**< <tt>\b 0xA4:</tt> FLC RLR4 Register */ 96 } mxc_flc_regs_t; 97 98 /* Register offsets for module FLC */ 99 /** 100 * @ingroup flc_registers 101 * @defgroup FLC_Register_Offsets Register Offsets 102 * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. 103 * @{ 104 */ 105 #define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */ 107 #define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */ 108 #define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */ 109 #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */ 110 #define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */ 111 #define MXC_R_FLC_WELR0 ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: <tt> 0x0080</tt> */ 112 #define MXC_R_FLC_RLR0 ((uint32_t)0x00000084UL) /**< Offset from FLC Base Address: <tt> 0x0084</tt> */ 113 #define MXC_R_FLC_WELR1 ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: <tt> 0x0088</tt> */ 114 #define MXC_R_FLC_RLR1 ((uint32_t)0x0000008CUL) /**< Offset from FLC Base Address: <tt> 0x008C</tt> */ 115 #define MXC_R_FLC_WELR2 ((uint32_t)0x00000090UL) /**< Offset from FLC Base Address: <tt> 0x0090</tt> */ 116 #define MXC_R_FLC_RLR2 ((uint32_t)0x00000094UL) /**< Offset from FLC Base Address: <tt> 0x0094</tt> */ 117 #define MXC_R_FLC_WELR3 ((uint32_t)0x00000098UL) /**< Offset from FLC Base Address: <tt> 0x0098</tt> */ 118 #define MXC_R_FLC_RLR3 ((uint32_t)0x0000009CUL) /**< Offset from FLC Base Address: <tt> 0x009C</tt> */ 119 #define MXC_R_FLC_WELR4 ((uint32_t)0x000000A0UL) /**< Offset from FLC Base Address: <tt> 0x00A0</tt> */ 120 #define MXC_R_FLC_RLR4 ((uint32_t)0x000000A4UL) /**< Offset from FLC Base Address: <tt> 0x00A4</tt> */ 121 /**@} end of group flc_registers */ 122 123 /** 124 * @ingroup flc_registers 125 * @defgroup FLC_ADDR FLC_ADDR 126 * @brief Flash Write Address. 127 * @{ 128 */ 129 #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ 130 #define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ 131 132 /**@} end of group FLC_ADDR_Register */ 133 134 /** 135 * @ingroup flc_registers 136 * @defgroup FLC_CLKDIV FLC_CLKDIV 137 * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 138 * MHz clock for Flash controller. 139 * @{ 140 */ 141 #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ 142 #define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ 143 144 /**@} end of group FLC_CLKDIV_Register */ 145 146 /** 147 * @ingroup flc_registers 148 * @defgroup FLC_CTRL FLC_CTRL 149 * @brief Flash Control Register. 150 * @{ 151 */ 152 #define MXC_F_FLC_CTRL_WR_POS 0 /**< CTRL_WR Position */ 153 #define MXC_F_FLC_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WR_POS)) /**< CTRL_WR Mask */ 154 155 #define MXC_F_FLC_CTRL_ME_POS 1 /**< CTRL_ME Position */ 156 #define MXC_F_FLC_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_ME_POS)) /**< CTRL_ME Mask */ 157 158 #define MXC_F_FLC_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ 159 #define MXC_F_FLC_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ 160 161 #define MXC_F_FLC_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */ 162 #define MXC_F_FLC_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */ 163 164 #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ 165 #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ 166 #define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ 167 #define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ 168 #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ 169 #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ 170 #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ 171 #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ 172 173 #define MXC_F_FLC_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ 174 #define MXC_F_FLC_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ 175 176 #define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ 177 #define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ 178 179 #define MXC_F_FLC_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ 180 #define MXC_F_FLC_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ 181 #define MXC_V_FLC_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ 182 #define MXC_S_FLC_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ 183 #define MXC_V_FLC_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ 184 #define MXC_S_FLC_CTRL_UNLOCK_LOCKED (MXC_V_FLC_CTRL_UNLOCK_LOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ 185 186 /**@} end of group FLC_CTRL_Register */ 187 188 /** 189 * @ingroup flc_registers 190 * @defgroup FLC_INTR FLC_INTR 191 * @brief Flash Interrupt Register. 192 * @{ 193 */ 194 #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ 195 #define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ 196 197 #define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ 198 #define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ 199 200 #define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ 201 #define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ 202 203 #define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ 204 #define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ 205 206 /**@} end of group FLC_INTR_Register */ 207 208 /** 209 * @ingroup flc_registers 210 * @defgroup FLC_DATA FLC_DATA 211 * @brief Flash Write Data. 212 * @{ 213 */ 214 #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ 215 #define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ 216 217 /**@} end of group FLC_DATA_Register */ 218 219 /** 220 * @ingroup flc_registers 221 * @defgroup FLC_ACTRL FLC_ACTRL 222 * @brief Access Control Register. Writing the ACTRL register with the following values in 223 * the order shown, allows read and write access to the system and user Information 224 * block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl 225 * = 0x9608b2c1. When unlocked, a write of any word will disable access to system 226 * and user information block. Readback of this register is always zero. 227 * @{ 228 */ 229 #define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ 230 #define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ 231 232 /**@} end of group FLC_ACTRL_Register */ 233 234 /** 235 * @ingroup flc_registers 236 * @defgroup FLC_WELR0 FLC_WELR0 237 * @brief WELR0 238 * @{ 239 */ 240 #define MXC_F_FLC_WELR0_WELR0_POS 0 /**< WELR0_WELR0 Position */ 241 #define MXC_F_FLC_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */ 242 243 /**@} end of group FLC_WELR0_Register */ 244 245 /** 246 * @ingroup flc_registers 247 * @defgroup FLC_RLR0 FLC_RLR0 248 * @brief RLR0 249 * @{ 250 */ 251 #define MXC_F_FLC_RLR0_RLR0_POS 0 /**< RLR0_RLR0 Position */ 252 #define MXC_F_FLC_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */ 253 254 /**@} end of group FLC_RLR0_Register */ 255 256 /** 257 * @ingroup flc_registers 258 * @defgroup FLC_WELR1 FLC_WELR1 259 * @brief WELR1 260 * @{ 261 */ 262 #define MXC_F_FLC_WELR1_WELR1_POS 0 /**< WELR1_WELR1 Position */ 263 #define MXC_F_FLC_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */ 264 265 /**@} end of group FLC_WELR1_Register */ 266 267 /** 268 * @ingroup flc_registers 269 * @defgroup FLC_RLR1 FLC_RLR1 270 * @brief RLR1 271 * @{ 272 */ 273 #define MXC_F_FLC_RLR1_RLR1_POS 0 /**< RLR1_RLR1 Position */ 274 #define MXC_F_FLC_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */ 275 276 /**@} end of group FLC_RLR1_Register */ 277 278 /** 279 * @ingroup flc_registers 280 * @defgroup FLC_WELR2 FLC_WELR2 281 * @brief WELR2 282 * @{ 283 */ 284 #define MXC_F_FLC_WELR2_WELR2_POS 0 /**< WELR2_WELR2 Position */ 285 #define MXC_F_FLC_WELR2_WELR2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR2_WELR2_POS)) /**< WELR2_WELR2 Mask */ 286 287 /**@} end of group FLC_WELR2_Register */ 288 289 /** 290 * @ingroup flc_registers 291 * @defgroup FLC_RLR2 FLC_RLR2 292 * @brief RLR2 293 * @{ 294 */ 295 #define MXC_F_FLC_RLR2_RLR2_POS 0 /**< RLR2_RLR2 Position */ 296 #define MXC_F_FLC_RLR2_RLR2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR2_RLR2_POS)) /**< RLR2_RLR2 Mask */ 297 298 /**@} end of group FLC_RLR2_Register */ 299 300 /** 301 * @ingroup flc_registers 302 * @defgroup FLC_WELR3 FLC_WELR3 303 * @brief WELR3 304 * @{ 305 */ 306 #define MXC_F_FLC_WELR3_WELR3_POS 0 /**< WELR3_WELR3 Position */ 307 #define MXC_F_FLC_WELR3_WELR3 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR3_WELR3_POS)) /**< WELR3_WELR3 Mask */ 308 309 /**@} end of group FLC_WELR3_Register */ 310 311 /** 312 * @ingroup flc_registers 313 * @defgroup FLC_RLR3 FLC_RLR3 314 * @brief RLR3 315 * @{ 316 */ 317 #define MXC_F_FLC_RLR3_RLR3_POS 0 /**< RLR3_RLR3 Position */ 318 #define MXC_F_FLC_RLR3_RLR3 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR3_RLR3_POS)) /**< RLR3_RLR3 Mask */ 319 320 /**@} end of group FLC_RLR3_Register */ 321 322 /** 323 * @ingroup flc_registers 324 * @defgroup FLC_WELR4 FLC_WELR4 325 * @brief WELR4 326 * @{ 327 */ 328 #define MXC_F_FLC_WELR4_WELR4_POS 0 /**< WELR4_WELR4 Position */ 329 #define MXC_F_FLC_WELR4_WELR4 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR4_WELR4_POS)) /**< WELR4_WELR4 Mask */ 330 331 /**@} end of group FLC_WELR4_Register */ 332 333 /** 334 * @ingroup flc_registers 335 * @defgroup FLC_RLR4 FLC_RLR4 336 * @brief RLR4 337 * @{ 338 */ 339 #define MXC_F_FLC_RLR4_RLR4_POS 0 /**< RLR4_RLR4 Position */ 340 #define MXC_F_FLC_RLR4_RLR4 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR4_RLR4_POS)) /**< RLR4_RLR4 Mask */ 341 342 /**@} end of group FLC_RLR4_Register */ 343 344 #ifdef __cplusplus 345 } 346 #endif 347 348 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_FLC_REGS_H_ 349
