1 /** 2 * @file fcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup fcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_FCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_FCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup fcr 67 * @defgroup fcr_registers FCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 69 * @details Function Control Register. 70 */ 71 72 /** 73 * @ingroup fcr_registers 74 * Structure type to access the FCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t fctrl0; /**< <tt>\b 0x00:</tt> FCR FCTRL0 Register */ 78 __IO uint32_t autocal0; /**< <tt>\b 0x04:</tt> FCR AUTOCAL0 Register */ 79 __IO uint32_t autocal1; /**< <tt>\b 0x08:</tt> FCR AUTOCAL1 Register */ 80 __IO uint32_t autocal2; /**< <tt>\b 0x0C:</tt> FCR AUTOCAL2 Register */ 81 __IO uint32_t urvbootaddr; /**< <tt>\b 0x10:</tt> FCR URVBOOTADDR Register */ 82 __IO uint32_t urvctrl; /**< <tt>\b 0x14:</tt> FCR URVCTRL Register */ 83 __IO uint32_t xo32mks; /**< <tt>\b 0x18:</tt> FCR XO32MKS Register */ 84 __R uint32_t rsv_0x1c; 85 __IO uint32_t ts0; /**< <tt>\b 0x20:</tt> FCR TS0 Register */ 86 __IO uint32_t ts1; /**< <tt>\b 0x24:</tt> FCR TS1 Register */ 87 __IO uint32_t adcreftrim0; /**< <tt>\b 0x28:</tt> FCR ADCREFTRIM0 Register */ 88 __IO uint32_t adcreftrim1; /**< <tt>\b 0x2C:</tt> FCR ADCREFTRIM1 Register */ 89 __IO uint32_t adcreftrim2; /**< <tt>\b 0x30:</tt> FCR ADCREFTRIM2 Register */ 90 } mxc_fcr_regs_t; 91 92 /* Register offsets for module FCR */ 93 /** 94 * @ingroup fcr_registers 95 * @defgroup FCR_Register_Offsets Register Offsets 96 * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. 97 * @{ 98 */ 99 #define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */ 100 #define MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: <tt> 0x0004</tt> */ 101 #define MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: <tt> 0x0008</tt> */ 102 #define MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: <tt> 0x000C</tt> */ 103 #define MXC_R_FCR_URVBOOTADDR ((uint32_t)0x00000010UL) /**< Offset from FCR Base Address: <tt> 0x0010</tt> */ 104 #define MXC_R_FCR_URVCTRL ((uint32_t)0x00000014UL) /**< Offset from FCR Base Address: <tt> 0x0014</tt> */ 105 #define MXC_R_FCR_XO32MKS ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: <tt> 0x0018</tt> */ 106 #define MXC_R_FCR_TS0 ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: <tt> 0x0020</tt> */ 107 #define MXC_R_FCR_TS1 ((uint32_t)0x00000024UL) /**< Offset from FCR Base Address: <tt> 0x0024</tt> */ 108 #define MXC_R_FCR_ADCREFTRIM0 ((uint32_t)0x00000028UL) /**< Offset from FCR Base Address: <tt> 0x0028</tt> */ 109 #define MXC_R_FCR_ADCREFTRIM1 ((uint32_t)0x0000002CUL) /**< Offset from FCR Base Address: <tt> 0x002C</tt> */ 110 #define MXC_R_FCR_ADCREFTRIM2 ((uint32_t)0x00000030UL) /**< Offset from FCR Base Address: <tt> 0x0030</tt> */ 111 /**@} end of group fcr_registers */ 112 113 /** 114 * @ingroup fcr_registers 115 * @defgroup FCR_FCTRL0 FCR_FCTRL0 116 * @brief Function Control 0. 117 * @{ 118 */ 119 #define MXC_F_FCR_FCTRL0_USBCLKSEL_POS 16 /**< FCTRL0_USBCLKSEL Position */ 120 #define MXC_F_FCR_FCTRL0_USBCLKSEL ((uint32_t)(0x3UL << MXC_F_FCR_FCTRL0_USBCLKSEL_POS)) /**< FCTRL0_USBCLKSEL Mask */ 121 122 #define MXC_F_FCR_FCTRL0_I2C0DGEN0_POS 20 /**< FCTRL0_I2C0DGEN0 Position */ 123 #define MXC_F_FCR_FCTRL0_I2C0DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS)) /**< FCTRL0_I2C0DGEN0 Mask */ 124 125 #define MXC_F_FCR_FCTRL0_I2C0DGEN1_POS 21 /**< FCTRL0_I2C0DGEN1 Position */ 126 #define MXC_F_FCR_FCTRL0_I2C0DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN1_POS)) /**< FCTRL0_I2C0DGEN1 Mask */ 127 128 #define MXC_F_FCR_FCTRL0_I2C1DGEN0_POS 22 /**< FCTRL0_I2C1DGEN0 Position */ 129 #define MXC_F_FCR_FCTRL0_I2C1DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN0_POS)) /**< FCTRL0_I2C1DGEN0 Mask */ 130 131 #define MXC_F_FCR_FCTRL0_I2C1DGEN1_POS 23 /**< FCTRL0_I2C1DGEN1 Position */ 132 #define MXC_F_FCR_FCTRL0_I2C1DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN1_POS)) /**< FCTRL0_I2C1DGEN1 Mask */ 133 134 #define MXC_F_FCR_FCTRL0_I2C2DGEN0_POS 24 /**< FCTRL0_I2C2DGEN0 Position */ 135 #define MXC_F_FCR_FCTRL0_I2C2DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN0_POS)) /**< FCTRL0_I2C2DGEN0 Mask */ 136 137 #define MXC_F_FCR_FCTRL0_I2C2DGEN1_POS 25 /**< FCTRL0_I2C2DGEN1 Position */ 138 #define MXC_F_FCR_FCTRL0_I2C2DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN1_POS)) /**< FCTRL0_I2C2DGEN1 Mask */ 139 140 /**@} end of group FCR_FCTRL0_Register */ 141 142 /** 143 * @ingroup fcr_registers 144 * @defgroup FCR_AUTOCAL0 FCR_AUTOCAL0 145 * @brief Automatic Calibration 0. 146 * @{ 147 */ 148 #define MXC_F_FCR_AUTOCAL0_ACEN_POS 0 /**< AUTOCAL0_ACEN Position */ 149 #define MXC_F_FCR_AUTOCAL0_ACEN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACEN_POS)) /**< AUTOCAL0_ACEN Mask */ 150 151 #define MXC_F_FCR_AUTOCAL0_ACRUN_POS 1 /**< AUTOCAL0_ACRUN Position */ 152 #define MXC_F_FCR_AUTOCAL0_ACRUN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACRUN_POS)) /**< AUTOCAL0_ACRUN Mask */ 153 154 #define MXC_F_FCR_AUTOCAL0_LDTRM_POS 2 /**< AUTOCAL0_LDTRM Position */ 155 #define MXC_F_FCR_AUTOCAL0_LDTRM ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LDTRM_POS)) /**< AUTOCAL0_LDTRM Mask */ 156 157 #define MXC_F_FCR_AUTOCAL0_GAININV_POS 3 /**< AUTOCAL0_GAININV Position */ 158 #define MXC_F_FCR_AUTOCAL0_GAININV ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_GAININV_POS)) /**< AUTOCAL0_GAININV Mask */ 159 160 #define MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 /**< AUTOCAL0_ATOMIC Position */ 161 #define MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */ 162 163 #define MXC_F_FCR_AUTOCAL0_MU_POS 8 /**< AUTOCAL0_MU Position */ 164 #define MXC_F_FCR_AUTOCAL0_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_MU_POS)) /**< AUTOCAL0_MU Mask */ 165 166 #define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS 23 /**< AUTOCAL0_HIRC96MACTMROUT Position */ 167 #define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS)) /**< AUTOCAL0_HIRC96MACTMROUT Mask */ 168 169 /**@} end of group FCR_AUTOCAL0_Register */ 170 171 /** 172 * @ingroup fcr_registers 173 * @defgroup FCR_AUTOCAL1 FCR_AUTOCAL1 174 * @brief Automatic Calibration 1. 175 * @{ 176 */ 177 #define MXC_F_FCR_AUTOCAL1_INITTRM_POS 0 /**< AUTOCAL1_INITTRM Position */ 178 #define MXC_F_FCR_AUTOCAL1_INITTRM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITTRM_POS)) /**< AUTOCAL1_INITTRM Mask */ 179 180 /**@} end of group FCR_AUTOCAL1_Register */ 181 182 /** 183 * @ingroup fcr_registers 184 * @defgroup FCR_AUTOCAL2 FCR_AUTOCAL2 185 * @brief Automatic Calibration 2 186 * @{ 187 */ 188 #define MXC_F_FCR_AUTOCAL2_DONECNT_POS 0 /**< AUTOCAL2_DONECNT Position */ 189 #define MXC_F_FCR_AUTOCAL2_DONECNT ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_DONECNT_POS)) /**< AUTOCAL2_DONECNT Mask */ 190 191 #define MXC_F_FCR_AUTOCAL2_ACDIV_POS 8 /**< AUTOCAL2_ACDIV Position */ 192 #define MXC_F_FCR_AUTOCAL2_ACDIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_ACDIV_POS)) /**< AUTOCAL2_ACDIV Mask */ 193 194 /**@} end of group FCR_AUTOCAL2_Register */ 195 196 /** 197 * @ingroup fcr_registers 198 * @defgroup FCR_URVCTRL FCR_URVCTRL 199 * @brief RISC-V Control Register. 200 * @{ 201 */ 202 #define MXC_F_FCR_URVCTRL_MEMSEL_POS 0 /**< URVCTRL_MEMSEL Position */ 203 #define MXC_F_FCR_URVCTRL_MEMSEL ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_MEMSEL_POS)) /**< URVCTRL_MEMSEL Mask */ 204 205 #define MXC_F_FCR_URVCTRL_IFLUSHEN_POS 1 /**< URVCTRL_IFLUSHEN Position */ 206 #define MXC_F_FCR_URVCTRL_IFLUSHEN ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_IFLUSHEN_POS)) /**< URVCTRL_IFLUSHEN Mask */ 207 208 /**@} end of group FCR_URVCTRL_Register */ 209 210 /** 211 * @ingroup fcr_registers 212 * @defgroup FCR_XO32MKS FCR_XO32MKS 213 * @brief RISC-V Control Register. 214 * @{ 215 */ 216 #define MXC_F_FCR_XO32MKS_CLK_POS 0 /**< XO32MKS_CLK Position */ 217 #define MXC_F_FCR_XO32MKS_CLK ((uint32_t)(0x7FUL << MXC_F_FCR_XO32MKS_CLK_POS)) /**< XO32MKS_CLK Mask */ 218 219 #define MXC_F_FCR_XO32MKS_EN_POS 7 /**< XO32MKS_EN Position */ 220 #define MXC_F_FCR_XO32MKS_EN ((uint32_t)(0x1UL << MXC_F_FCR_XO32MKS_EN_POS)) /**< XO32MKS_EN Mask */ 221 222 #define MXC_F_FCR_XO32MKS_DRIVER_POS 8 /**< XO32MKS_DRIVER Position */ 223 #define MXC_F_FCR_XO32MKS_DRIVER ((uint32_t)(0x7UL << MXC_F_FCR_XO32MKS_DRIVER_POS)) /**< XO32MKS_DRIVER Mask */ 224 225 #define MXC_F_FCR_XO32MKS_PULSE_POS 11 /**< XO32MKS_PULSE Position */ 226 #define MXC_F_FCR_XO32MKS_PULSE ((uint32_t)(0x1UL << MXC_F_FCR_XO32MKS_PULSE_POS)) /**< XO32MKS_PULSE Mask */ 227 228 #define MXC_F_FCR_XO32MKS_CLKSEL_POS 12 /**< XO32MKS_CLKSEL Position */ 229 #define MXC_F_FCR_XO32MKS_CLKSEL ((uint32_t)(0x3UL << MXC_F_FCR_XO32MKS_CLKSEL_POS)) /**< XO32MKS_CLKSEL Mask */ 230 #define MXC_V_FCR_XO32MKS_CLKSEL_NONE ((uint32_t)0x0UL) /**< XO32MKS_CLKSEL_NONE Value */ 231 #define MXC_S_FCR_XO32MKS_CLKSEL_NONE (MXC_V_FCR_XO32MKS_CLKSEL_NONE << MXC_F_FCR_XO32MKS_CLKSEL_POS) /**< XO32MKS_CLKSEL_NONE Setting */ 232 #define MXC_V_FCR_XO32MKS_CLKSEL_TEST ((uint32_t)0x1UL) /**< XO32MKS_CLKSEL_TEST Value */ 233 #define MXC_S_FCR_XO32MKS_CLKSEL_TEST (MXC_V_FCR_XO32MKS_CLKSEL_TEST << MXC_F_FCR_XO32MKS_CLKSEL_POS) /**< XO32MKS_CLKSEL_TEST Setting */ 234 #define MXC_V_FCR_XO32MKS_CLKSEL_ISO ((uint32_t)0x2UL) /**< XO32MKS_CLKSEL_ISO Value */ 235 #define MXC_S_FCR_XO32MKS_CLKSEL_ISO (MXC_V_FCR_XO32MKS_CLKSEL_ISO << MXC_F_FCR_XO32MKS_CLKSEL_POS) /**< XO32MKS_CLKSEL_ISO Setting */ 236 #define MXC_V_FCR_XO32MKS_CLKSEL_IPO ((uint32_t)0x3UL) /**< XO32MKS_CLKSEL_IPO Value */ 237 #define MXC_S_FCR_XO32MKS_CLKSEL_IPO (MXC_V_FCR_XO32MKS_CLKSEL_IPO << MXC_F_FCR_XO32MKS_CLKSEL_POS) /**< XO32MKS_CLKSEL_IPO Setting */ 238 239 /**@} end of group FCR_XO32MKS_Register */ 240 241 /** 242 * @ingroup fcr_registers 243 * @defgroup FCR_TS0 FCR_TS0 244 * @brief Temp Sensor trim0 245 * @{ 246 */ 247 #define MXC_F_FCR_TS0_GAIN_POS 0 /**< TS0_GAIN Position */ 248 #define MXC_F_FCR_TS0_GAIN ((uint32_t)(0xFFFUL << MXC_F_FCR_TS0_GAIN_POS)) /**< TS0_GAIN Mask */ 249 250 /**@} end of group FCR_TS0_Register */ 251 252 /** 253 * @ingroup fcr_registers 254 * @defgroup FCR_TS1 FCR_TS1 255 * @brief Temp Sensor trim1 256 * @{ 257 */ 258 #define MXC_F_FCR_TS1_OFFSET_POS 0 /**< TS1_OFFSET Position */ 259 #define MXC_F_FCR_TS1_OFFSET ((uint32_t)(0x3FFFUL << MXC_F_FCR_TS1_OFFSET_POS)) /**< TS1_OFFSET Mask */ 260 261 #define MXC_F_FCR_TS1_TS_OFFSET_SIGN_POS 14 /**< TS1_TS_OFFSET_SIGN Position */ 262 #define MXC_F_FCR_TS1_TS_OFFSET_SIGN ((uint32_t)(0x3FFFFUL << MXC_F_FCR_TS1_TS_OFFSET_SIGN_POS)) /**< TS1_TS_OFFSET_SIGN Mask */ 263 264 /**@} end of group FCR_TS1_Register */ 265 266 /** 267 * @ingroup fcr_registers 268 * @defgroup FCR_ADCREFTRIM0 FCR_ADCREFTRIM0 269 * @brief Temp Sensor trim1 270 * @{ 271 */ 272 #define MXC_F_FCR_ADCREFTRIM0_VREFP_POS 0 /**< ADCREFTRIM0_VREFP Position */ 273 #define MXC_F_FCR_ADCREFTRIM0_VREFP ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFP_POS)) /**< ADCREFTRIM0_VREFP Mask */ 274 275 #define MXC_F_FCR_ADCREFTRIM0_VREFM_POS 8 /**< ADCREFTRIM0_VREFM Position */ 276 #define MXC_F_FCR_ADCREFTRIM0_VREFM ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFM_POS)) /**< ADCREFTRIM0_VREFM Mask */ 277 278 #define MXC_F_FCR_ADCREFTRIM0_VCM_POS 16 /**< ADCREFTRIM0_VCM Position */ 279 #define MXC_F_FCR_ADCREFTRIM0_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM0_VCM_POS)) /**< ADCREFTRIM0_VCM Mask */ 280 281 #define MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS 24 /**< ADCREFTRIM0_VX2_TUNE Position */ 282 #define MXC_F_FCR_ADCREFTRIM0_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS)) /**< ADCREFTRIM0_VX2_TUNE Mask */ 283 284 /**@} end of group FCR_ADCREFTRIM0_Register */ 285 286 /** 287 * @ingroup fcr_registers 288 * @defgroup FCR_ADCREFTRIM1 FCR_ADCREFTRIM1 289 * @brief Temp Sensor trim1 290 * @{ 291 */ 292 #define MXC_F_FCR_ADCREFTRIM1_VREFP_POS 0 /**< ADCREFTRIM1_VREFP Position */ 293 #define MXC_F_FCR_ADCREFTRIM1_VREFP ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFP_POS)) /**< ADCREFTRIM1_VREFP Mask */ 294 295 #define MXC_F_FCR_ADCREFTRIM1_VREFM_POS 8 /**< ADCREFTRIM1_VREFM Position */ 296 #define MXC_F_FCR_ADCREFTRIM1_VREFM ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFM_POS)) /**< ADCREFTRIM1_VREFM Mask */ 297 298 #define MXC_F_FCR_ADCREFTRIM1_VCM_POS 16 /**< ADCREFTRIM1_VCM Position */ 299 #define MXC_F_FCR_ADCREFTRIM1_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM1_VCM_POS)) /**< ADCREFTRIM1_VCM Mask */ 300 301 #define MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS 24 /**< ADCREFTRIM1_VX2_TUNE Position */ 302 #define MXC_F_FCR_ADCREFTRIM1_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS)) /**< ADCREFTRIM1_VX2_TUNE Mask */ 303 304 /**@} end of group FCR_ADCREFTRIM1_Register */ 305 306 /** 307 * @ingroup fcr_registers 308 * @defgroup FCR_ADCREFTRIM2 FCR_ADCREFTRIM2 309 * @brief Temp Sensor trim1 310 * @{ 311 */ 312 #define MXC_F_FCR_ADCREFTRIM2_VREFP_POS 0 /**< ADCREFTRIM2_VREFP Position */ 313 #define MXC_F_FCR_ADCREFTRIM2_VREFP ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM2_VREFP_POS)) /**< ADCREFTRIM2_VREFP Mask */ 314 315 #define MXC_F_FCR_ADCREFTRIM2_VREFM_POS 8 /**< ADCREFTRIM2_VREFM Position */ 316 #define MXC_F_FCR_ADCREFTRIM2_VREFM ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM2_VREFM_POS)) /**< ADCREFTRIM2_VREFM Mask */ 317 318 #define MXC_F_FCR_ADCREFTRIM2_VCM_POS 16 /**< ADCREFTRIM2_VCM Position */ 319 #define MXC_F_FCR_ADCREFTRIM2_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM2_VCM_POS)) /**< ADCREFTRIM2_VCM Mask */ 320 321 #define MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS 24 /**< ADCREFTRIM2_VX2_TUNE Position */ 322 #define MXC_F_FCR_ADCREFTRIM2_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS)) /**< ADCREFTRIM2_VX2_TUNE Mask */ 323 324 /**@} end of group FCR_ADCREFTRIM2_Register */ 325 326 #ifdef __cplusplus 327 } 328 #endif 329 330 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_FCR_REGS_H_ 331
